JPS5978573A - Semiconductor device - Google Patents

Abstract

PURPOSE:To put an N conductivity type region and a P conductivity type region into an ohmic contact by providing a through hole in a semiconductor substrate and burying a metal or a metal silicide in the through hole. CONSTITUTION:The through hole penetrating a P type polycrystalline Si 7 and an N type polycrystalline Si 8 formed on the Si substrate 1 is formed, and the P type polycrystalline Si 7 and the N type polycrystalline Si 8 are connected in ohmic manner by burying the metal or the metallic silicide in the through hole. A through hole penetrating a P type diffused layer 4 and an N type diffused layer 2 formed on the Si substrate 1 is formed, and the P type diffused layer 4 and the N type diffused layer 2 are connected in ohmic manner by burying the metal or the metallic silicide in the through hole. Therefore, the occupation area for mutually connecting regions of different conductivity types reduces, and then a semiconductor device of a high density and a high integration degree can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device in which semiconductor regions of different conductivity types are ohmically interconnected and wired at high density.

(Prior Art) In semiconductor LSIs, polycrystalline silicon and silicon single crystal substrate surfaces (diffusion layers) containing impurities at a high concentration are also used as wiring materials. With wiring made of this type of semiconductor material, it is easy to connect interconnections having the same four conductivity types to each other, but when interconnections having different conductivity types are connected to each other, it is difficult to obtain an ohmic connection.

FIG. 1 shows a conventional example of interconnecting wiring having N and P conductivity types. The 14th article is an example of interconnecting polycrystalline silicon of different conductivity types. In the figure, 1 is a silicon substrate, 5 is a silicon oxide film, 6 is AJ electrode wiring,
7 indicates polycrystalline silicon having an n-conductivity type, and 8 indicates polycrystalline silicon having an n-conductivity type. Here, IIj: the polycrystalline silicon 7 having the n conductivity type and the polycrystalline silicon 8 having the n conductivity type are not directly connected, but are connected via the A1 electrode wiring 6. FIG. 1 CB) shows a conventional example in which diffusion layers of different conductivity types are connected. 1 is a silicon substrate, 2 is an n-swelled diffusion layer, 3 is an n-swollen diffusion layer containing a high concentration impurity, 4 is a p-swelled diffusion layer, 5 is a silicon oxide film, and 6 is an AJ-electrode. Here, although the p-swelling diffusion layer 4 and the n-swelling diffusion layer 2 are in contact with each other, ohmic contact is not obtained since they form a pn junction.

The p-swelled diffusion layer 4 and the n-swelled diffusion layer 2 are connected via the AJ-electrode 6 and the n-swelled diffusion layer 3 containing high concentration impurities.

As is clear from the conventional example shown in FIG. There was a drawback that the wiring area occupied by the electrodes was large.

(Objective of the Invention) An object of the present invention is to provide a new technique for obtaining a high-density, highly integrated semiconductor device by reducing the area occupied by interconnecting regions of different conductivity types.

Another object of the present invention is to configure the semiconductor substrate as a power supply line by embedding a metal or metal silicide in contact with the diffusion layer on the surface of the semiconductor substrate and the semiconductor substrate, thereby achieving high density and high integration. The purpose of the present invention is to provide a semiconductor device.

(Structure of the Invention) In order to achieve the above object, the present invention provides an N conductivity type region and a P conductivity type region.
In a semiconductor device having a conductivity type region, a through hole is provided and metal or metal silicide is buried in the through hole, and the N conductivity type region and the P conductivity type region are brought into contact. The gist of the invention is a semiconductor device having characteristics.

Furthermore, the gist of the present invention is a semiconductor device including embedding metal or metal silicide in a part of the source diffusion region of a MOS (MOS) run sinter, and bringing the source diffusion region into contact with a semiconductor substrate.

Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

FIG. 2 shows an embodiment of the present invention, in which J is a silicon substrate, 2 is an n-swelled diffusion layer, 4 is a p-swelled diffusion layer, 5 is a silicon oxide film, and 6 is a metal. silicide, 7 indicates p-expanded crystal silicon, and 8 indicates n-expanded crystal silicon.

The 24th example is an example in which a through hole communicating with the p-expanded crystal silicon 7 and the n-expanded crystal silicon 8 is formed, and a metal or metal silicide 6 is buried in this through-hole.
The sill expanded crystal silicon 7 and the n expanded crystal silicon 8 are ohmically connected through one through hole.

FIG. 2(B) is similar to FIG. 2(A), except that p-expanded crystalline silicon 7 and n-expanded crystalline silicon 8 are formed through a silicon oxide film 5, and one through hole is formed. Alternatively, the p-expanded crystal silicon and the n-expanded crystal silicon 8 can be ohmically connected.

In this case, the p-expanded crystalline silicon 7 and the n-expanded crystalline silicon 8 do not come into direct contact with each other except through the metal or metal silicide at the through-hole forming portion.

FIG. 2(C) is an example in which a through hole communicating with the p-swelled diffusion layer 4 and the n-type diffusion layer 12 is formed, and a metal or metal silicide is placed in this through hole. The sill expansion diffusion layer 4 and the n expansion diffusion layer 2 are ohmically connected.As is clear from this embodiment, according to the present invention, semiconductor regions of different conductivity types can be ohmically connected with one through hole. This makes it possible to reduce the number of through holes and greatly reduce the area occupied by the wiring, compared to the case where the wiring is connected in a plane using a metal wiring material as described in the conventional example.

FIG. 3 shows an embodiment for manufacturing the device of the present invention. FIG. 3fa) shows a cross-sectional view of the structure in which p-expanded crystalline silicon 7 and n-expanded crystalline silicon 8 are formed by a well-known method and then patterned. In the figure, the reference numerals of the constituent materials shown are the same as those in FIG. 2(A) l (0). next,
A resist pattern 10 is formed and parallel plate dry etching (OF4+H, atmosphere) is performed at desired positions as shown in FIG.
b) Through holes 11. through semiconductors having different conductivity types as shown in FIG. If' is provided. Here, the hole 11 communicates with the p-expanded crystal silicon 7 and the n-expanded crystal silicon 8, and the hole 11' communicates with the p-expanded diffusion layer 4 and the n-expanded diffusion layer 2. Of course, depending on the configuration of the diffusion layer pattern and the polycrystalline pattern, holes communicating with polycrystalline silicon of different conductivity types and the diffusion layer can also be formed in this step.

Next, as shown in Figure 3 (0), a directional deposition method (
metal (601), which is difficult to deposit on the side walls of steps), for example, by vapor deposition or metal ion beam deposition in plasma.
Deposit. Here, A1 was deposited at room temperature. Note that 5' indicates a silicon oxide film.

Next, as shown in FIG. 3(d), metal 6 (H glue 7 to 7) is applied using Regime 10 as a stencil.

In this case, the resist is AZI370 (trade name).7 to 7 was carried out in ultrasonic acetone.

The device of the present invention can be realized through the steps described above. In this embodiment, the metal is buried in the through hole by lift-off, but the present invention can of course be practiced without using the hole 7.

That is, after through-hole etching, the resist is removed and wiring metal is formed. It goes without saying that the device of the present invention can also be realized by forming a metal pattern in the vicinity of the through hole by etching and then etching the metal pattern in the vicinity of the through hole.

FIG. 4 shows another embodiment of the invention. In the figure, numeral 5 is a silicon substrate, 5 is a silicon oxide film, 7 is p-expanded crystal silicon, and 8 is n-expanded crystal silicon. This embodiment is an improved version of FIGS. 2(A) and 2(B). That is,
The p-expanded crystal silicon 7 and the n-expanded crystal silicon 8 are arranged on the same plane, and a through hole is formed at the boundary thereof, and a metal 6' is buried therein. This is how you do it (Figure 2 Buddha).

Compared to the embodiment (B), it was not possible to reduce the unevenness on the surface of the semiconductor element.
By embedding metal in each through hole, an ohmic connection can be made.

FIG. 5 shows another embodiment of the invention. 1 is a silicon substrate, 2 is an n-swelled diffusion layer, and 4 is a p-swelled diffusion layer. This embodiment is an improved version of FIG. 2(0). That is, by providing a through hole at the end of the p-swelled diffusion layer 4, instead of burying the metal J, semiconductor materials of different conductivity types are ohmically connected. According to this embodiment, the area required for forming the through hole can be reduced and the depth of the through hole can be made shallower than the embodiment shown in FIG. 2(C).

FIG. 6(A) shows an embodiment in which the device of the present invention is applied to a CMO8 integrated circuit. 1 is a p-type silicon substrate, 2 is an n-swelled diffusion layer, 31.32 is an n-swelled diffusion layer, and is an n-channel MO.
S) Constitutes the source and drain of the run sinter QN. 41.42 is p swelling diffusion layer and p channel MO8)
It constitutes the source and drain of the run sinter Q and P. (B) The figure shows a connection diagram of p-channel and n-channel MOS) run sinter. 51 is a silicon oxide film, 61
．． 62 is a buried metal layer, and 8 is n-expanded crystal silicon. The buried metal 61 connects the n-swelled diffusion layer 31, which becomes the source of the n-channel MOS transistor Q8, and the p-type silicon substrate 1 ohmically, and forms an electrode line.
ss can be constructed from a p-type silicon substrate. In addition, the buried metal 62 connects the diffusion layer 42 which becomes the source of the p-channel MO8) and the n-swelled diffusion layer 2 ohmically to the n-swelled diffusion layer 2, and the power supply line/vDD is composed of the n-swelled diffusion layer 2. can do. Therefore, traditional CMO
The power line wiring using the A1 electrode wiring can be removed from the S circuit, and the A! The area occupied by the electrode wiring can be greatly reduced.

In the above embodiments, AJ and other metals can be used as the metal buried in the through hole.
A! When other metals are used, the relationship between the concentrations in the p conductivity type region and the n conductivity type region is as shown in Table 1.

In this table, "dark" in the lower column of the N-conducting metal region means "
10" or more, and "light" means "
101 g", and "thin" in the lower column of the P conductivity type region means less than r 1 '01 sJ,
"Dark" means "1OIIl" or more.

Table 1 (Effects of the Invention) As explained above, according to the present invention, regions of different conductivity types can be ohmically connected through a single through hole, and a high-density and highly integrated semiconductor device can be realized. It can be realized.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the structure of a conventional semiconductor device, Figure 2 (A)
~(0), Figure 4, Figure 5, Figure 6 (A), (B)
3 shows an example of the present invention, and FIGS. 3(a) to 3(fd) show an example of the manufacturing method of the present invention. l...Silicon substrate, 2...N swelling diffusion layer, 3,31°32...N swelling diffusion layer, 4,41.42...P swelling diffusion layer, 5.51.5'... Silicon oxide film, 6, 6, 6
, 61° 601 , 62...metal buried layer, 7...p
Expanded crystalline silicon, 8...n Expanded crystalline silicon, 9.
...Contact hole, 10...Resist, 11.11'
... Hole, 601 ... Metal patent applicant Figure 1 Rod Figure 2 Figure 3 Figure 4

Claims (3)

[Claims] (1) In a semiconductor device having an N conductivity type region and a P conductivity type region, by providing a through hole and burying metal or metal silicide in the through hole, the N conductivity type region and the P conductivity type region can be separated. A semiconductor device characterized in that a conductive type region is brought into contact with the conductive type region. (2) The semiconductor device according to claim 1, wherein in the MO8 integrated circuit, the semiconductor substrate constitutes a power supply line. (3) A semiconductor device comprising burying metal or metal silicide in a part of the source diffusion region of a MOS l-run sinter, and bringing the source diffusion region into contact with a semiconductor substrate.