JPS5978552A - 半導体受光素子の製造方法 - Google Patents

半導体受光素子の製造方法

Info

Publication number
JPS5978552A
JPS5978552A JP57189666A JP18966682A JPS5978552A JP S5978552 A JPS5978552 A JP S5978552A JP 57189666 A JP57189666 A JP 57189666A JP 18966682 A JP18966682 A JP 18966682A JP S5978552 A JPS5978552 A JP S5978552A
Authority
JP
Japan
Prior art keywords
chip
positioning
terminal
alignment
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57189666A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6317336B2 (https=
Inventor
Takeyumi Abe
阿部　剛弓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57189666A priority Critical patent/JPS5978552A/ja
Publication of JPS5978552A publication Critical patent/JPS5978552A/ja
Publication of JPS6317336B2 publication Critical patent/JPS6317336B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0441—Apparatus for sealing, encapsulating, glassing, decapsulating or the like

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP57189666A 1982-10-28 1982-10-28 半導体受光素子の製造方法 Granted JPS5978552A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57189666A JPS5978552A (ja) 1982-10-28 1982-10-28 半導体受光素子の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57189666A JPS5978552A (ja) 1982-10-28 1982-10-28 半導体受光素子の製造方法

Publications (2)

Publication Number Publication Date
JPS5978552A true JPS5978552A (ja) 1984-05-07
JPS6317336B2 JPS6317336B2 (https=) 1988-04-13

Family

ID=16245138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57189666A Granted JPS5978552A (ja) 1982-10-28 1982-10-28 半導体受光素子の製造方法

Country Status (1)

Country Link
JP (1) JPS5978552A (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01169029U (https=) * 1988-05-19 1989-11-29
JPH0611670U (ja) * 1991-05-14 1994-02-15 株式会社マテックマツザキ 鋏の枢着ネジ軸

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56144562A (en) * 1980-04-11 1981-11-10 Hitachi Ltd Apparatus for manufacturing base for ceramic package

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56144562A (en) * 1980-04-11 1981-11-10 Hitachi Ltd Apparatus for manufacturing base for ceramic package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01169029U (https=) * 1988-05-19 1989-11-29
JPH0611670U (ja) * 1991-05-14 1994-02-15 株式会社マテックマツザキ 鋏の枢着ネジ軸

Also Published As

Publication number Publication date
JPS6317336B2 (https=) 1988-04-13

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