JPS5976475A - Manufacture of mos semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an MOS transistor having a short channel by a method wherein a thick field oxide film is formed while it is half buried in the peripheral edge of a semiconductor substrate, a gate electrode is provided on the substrate surrounded by the film, the entire surface is coated with a silanol compound which contains an impurity, thus diffusing an impurity therefrom, and a source and a drain region are formed by using ion implantation jointly therewith. CONSTITUTION:The thick field oxide film 2 is formed while it is half buried in the peripheral edge of the P type Si substrate 1, and the gate electrode 4 composed of a polycrystalline Si is provided, at the center of the surface of the substrate 1 surrounded by the film, via a gate insulation film 5. Next, the entire surface including these is spin-coated with the silanol compound 6 which contains the N type impurity, which is hardened by baking at approx. 400 deg.C for an hour. At this time, the compound 6 changes thin on an element forming region 3 and thick at a part of stepwise difference. Thereafter, the N type impurity ions are implanted into the thin part of the compound 6 by utilizing the part, extrusion diffusion is performed by heat treatment, and accordingly the deep source region 7 and drain region 8 are obtained at the center.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing an MO8 semiconductor device, and particularly to a method for manufacturing an MO3 semiconductor device having a short channel.

(b) Prior art Recently, MO3 semiconductor devices, especially MOS LSIs, have been required to have higher operating speeds, larger scale integration, and lower power consumption, and there is an urgent need to miniaturize the MOS transistors that will make up the IC. . One method for this is to shorten the channel length of a MOS transistor. However, in the method of diffusing the source and drain regions using the self-aligned effect using the gate electrode as a mask, the diffusion occurs in the lateral direction. It was not a suitable method to obtain a short channel because it could not be ignored that the channel would also expand.

(C) Objective An object of the present invention is to provide a method for manufacturing an MO8 semiconductor device that is more suitable for forming a short channel in view of the conventional drawbacks.

Another object of the present invention is to provide a method for manufacturing an MO8 semiconductor device that can be miniaturized using conventional manufacturing techniques.

) configuration The present invention is comprised of the following steps.

(1) A process of forming a thick field oxide film partially buried in the semiconductor substrate.

(2) A step of forming a gate electrode on the element formation region surrounded by the field oxide film.

(3) A step of applying a silanol compound containing impurities to the substrate surface by a spin-on method.

(4) Step of ion-implanting deep second source and second drain regions through a silanol compound.

(5) heat treating the substrate to diffuse the shallow first source and first drain regions;

(E) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 6.

The first step of the present invention is as shown in FIG.
A thick field oxide film (2) is partially embedded in 1).
).

In this process, a P-type silicon substrate (1) with a specific resistance of 2Ω・cm is used.
The element formation region (3) of 1 is coated with a silicon nitride film, and
A buried field oxide film (2) with a thickness of about 1 μm is formed by thermal oxidation treatment in a steam atmosphere at 100° C.

After that, the second step of the present invention in which the silicon nitride film is selectively removed is as shown in FIG. The goal is to form a

In this step, a thin gate oxide film (5) of approximately 300X is formed on the surface of the element formation region (3), and then a gate oxide film (5) of approximately 8X
A polysilicon film having a thickness of about 3000 A' containing 1020/c of phosphorus is deposited, and a desired gate electrode (4) is formed by photolithography.

The third step of the present invention, as shown in FIG. 3, consists in applying a silanol compound (6) containing an N-type impurity to the surface of the substrate (1).

In this step, the substrate (1) is placed on a rotating disk, and a liquid silanol compound (main component Rn Si (OH)+-n
) onto the substrate (1), and the substrate (1) is rotated to spread the silanol compound over the entire surface using centrifugal force. At this time, a thick layer of silanol compound (6) (
It has the property of being attached. After that, silanol compound (6
) is baked at about 400℃ for 1 hour to harden it. It is clear from FIG. 3 that the silanol compound (6) adheres thinly to the flat parts of the field oxide film (2) and the element formation region (3), and thickly adheres to the stepped parts. Gate electrode (4) and field oxide film (2)
Since it adheres thickly to about 2 μm inside from the end, a masking effect can be obtained.

The fourth step of the present invention, as shown in FIG. 4, consists in ion-implanting deep N-type second source and drain regions (7) and (8) through a silanol compound (6).

This step is one of the features of the present invention, in which N-type impurities are ion-implanted using the difference in thickness of the silanol compound (6) to form deep second source and drain regions (7).
) (81 is formed. The ion implantation is performed with phosphorus (P) at an acceleration energy of 60 KeV and a dose of ~5XlOcm.
A drain region (71(8)) is formed to a depth of about 0.2μ. A second source and a second drain region (71(8)
The width is masked with a thick silanol compound (6), so it is formed approximately 2 μm inward from the edges of the gate electrode (4) and field oxide film (2).

The fifth step of the present invention, as shown in FIG. 5, consists in heating the entire substrate (1) to diffuse shallow N-type first source and drain regions (9) and (10).

This step is one of the features of the present invention, in which the entire substrate (1) is heated to remove N such as arsenic contained in the silanol compound (6).
Type impurities are diffused into the surface of the substrate (1) to form shallow first source and first drain regions (91 (10)).

At this time, the aforementioned deep second source and second drain regions (7) and (8) are also driven in. As a result, the channel length of the first source and drain regions (91
00) and is extremely shallow, minimizing lateral diffusion.

The final step of the present invention is to form the source and drain electrodes 1 (12), as shown in FIG.

In this step, after removing the sila and nol compounds (6) by notching, the gate electrode (4) is removed (an oxide film OJ is formed on the surface of the element formation region (3), and then the source is formed by aluminum evaporation through the contact hole. and drain electrode (1
1), form Q21.

(f) Effect According to the present invention, the deep second north and second drain regions (7) and (8) are formed in the first base and the deep second drain regions (7) and (8) by utilizing the difference in the deposited film thickness in spin-on coating of the silanol compound (6). Since the first drain region (91) can be formed inside the first drain region (101), the channel length can be determined by the shallow first drain region (9) and the first drain region (9) QO.For this reason, the channel length needs to take almost no account of lateral diffusion. Therefore, the channel length can be set to the same width as the gate electrode (4).

Therefore, if the gate electrode (4) is formed to have an extremely narrow IJ, MOS transistors having a short channel can be easily mass-produced.

[Brief explanation of drawings]

1 to 6 are cross-sectional views for explaining the present invention. Explanation of main figure numbers (1) is semiconductor substrate, (2) is field oxide film, (3)
) is the element formation region, (4) is the gate electrode, (6) is the silanol compound, (71 (81 is the second source and second drain region, (91 (10) 6 is the first source and the first
In the drain region Fig. 1 7 1 δ Fig. 6

Claims (1)

[Claims] 1. A step of forming a thick field oxide film partially buried in the semiconductor substrate, a step of forming a gate electrode on the element formation region surrounded by the field oxide film, and a step of forming a silanol compound containing impurities on the surface of the substrate. A method for manufacturing an MO8 semiconductor device, comprising the steps of coating, ion-implanting the source and drain regions through the silanol compound, and heat-treating the substrate to diffuse the source and drain regions.