JPS5976450A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain ultra-high frequency apparatus by providing a metal grounding plate which is narrower than the width of lead extending direction at the rear surface of frame of insulator and by loading a semiconductor chip through a metal base on the exposed surface within the frame. CONSTITUTION:The width of metal grounding plate 13 is narrower than that of a ceramic frame 11. A semiconductor chip 17 is combined with the metal grounding plate 13 through a metal base 14. In case of loading a device, grounding can be performed simultaneously with loading by securing the grounding plate 13 to the grounding pattern of the substrate. The edges of the grounding plate 13 and lead 16 ae placed in the same plane and these are soldered to wiring pattern of the printed wiring board 18. According to this structure, static capacitane between the lead 16 and grounding plate 13 is reduced and thereby a device which can be used for ultra-high frequency can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device equipped with a package suitable for operation in an ultra-high speed region or an ultra-high frequency region.

Prior Art and Problems Conventionally, the semiconductor device shown in FIG. 1 has been known.

In the figure, 1 is a ceramic plate, IA is a recess for accommodating a semiconductor chip, 2 is a metallized pattern, 3 is a lead, 4 is a semiconductor chip, and 5 is a ground line.

In this conventional example, the metallized pattern 2 on which the semiconductor chip 4 is attached is electrically connected to one of the leads 3,
The lead 3 is connected to the ground line 5 of the circuit or to a line at an appropriate potential.

However, if the above-mentioned configuration has a high operating speed,
For example, if you try to apply it to a semiconductor device used in an ultra-high-speed region where the switching speed is 1 (ns) or less, or a semiconductor device used in an ultra-high frequency region where the operating frequency is high (for example, the frequency is 1 (CG) Iz) or more, metallization・
Due to the parasitic inductance between the pattern 2 and the lead 3 or the parasitic inductance of the ground line 5 itself, waveform distortion such as ringing may occur, resulting in malfunction, or impedance mismatch may occur, causing the input signal to attenuate and stop operation. There are problems such as

OBJECTS OF THE INVENTION The present invention specifically improves the pancage on which a semiconductor chip is mounted so that it is not affected by parasitic inductance, thereby making it usable in an ultra-high frequency region and achieving ultra-high switching speed. Provided is a semiconductor device having the following.

Embodiment of the invention FIG. 2 is a cutaway front view of essential parts of an embodiment of the invention, and FIG.
The figure is a rear view of the main part of the embodiment shown in FIG. 2. still,
This embodiment is an example of application to a flat package.

In the figure, 11 is the first ceramic frame, 12 is the second
13 is a metal grounding plate, 14 is a metal base, 15 is a cap, 16 is a lead, and 17 is a semiconductor chip. Although not shown, the frame 11
A metallized pattern for input/output is formed on the surface of the semiconductor chip 17, and is connected to the semiconductor chip 17 by bonding wires (not shown).

In this embodiment, the semiconductor chip 17 is connected to the metal grounding plate 13 via the metal base 14, so when mounting the semiconductor device, the metal grounding plate 13 is attached to the grounding pattern of the board. By fixing it to the semiconductor chip 17, mounting and grounding can be performed at the same time, and the back surface of the semiconductor chip 17 can be connected to an external circuit (grounding circuit) over the shortest distance.

FIG. 4 is a cutaway front view of essential parts when the semiconductor device shown in FIGS. 2 and 3 is mounted, and the same parts as those explained in connection with FIGS. 2 and 3 are indicated by the same symbols. be.

In the figure, 18 is a substrate, 19 is a ground plane formed on the back surface of the substrate 18, 20 is a ground pattern formed on the front surface of the substrate 18, 21 is a wiring pattern, and 22 is a ground plane 19 and a ground plane filled with a conductive material. Through holes connecting patterns 20 are shown respectively.

Here, as the substrate 18, it is preferable to use a material with low dielectric loss at high frequencies, such as Flow Glass (trade name), which is made by hardening glass filament with Teflon (trade name) into a plate shape, or alumina ceramic.

A metallized film is formed over the entire back surface of the substrate 18, and this is used as a ground plane 19.

The wiring pattern 21 is not just a metallized film, but a microstrip line.

A portion of the surface of the substrate 18 for mounting the semiconductor device is a ground pattern 20 formed of a metallized film.

The ground pattern 20 has a through hole 22 formed thereunder, and is connected to the ground plane 19 through a conductive material filled in the through hole 22.

The ground plate 13 and the tips of the leads 16 are arranged on the same plane so that they can be easily connected to the metallized pattern of the substrate 18 by soldering or the like.

An important feature of this embodiment is that the width of the metal ground plate 130 is made smaller than the width of the package when viewed from the front, that is, the width of the first ceramic frame 11. When mounted as shown in FIG.
This is to prevent the capacitance between lead 1 and lead 3 from increasing and the signal being attenuated there, and to prevent the signal from being attenuated there.
This is to prevent the ground plate 13 from coming into contact with the metallized pattern connected to the metallized pattern 6 and causing a short circuit. In order to reduce such capacitance, it is also effective to reduce the thickness of the grounding plate 13, for example, to about 0.2 [11]. Also. The length by which the ground plate 13 can be retracted from the end of the pa-no-cage may be approximately the same as the thickness of the ground plate 13.

Incidentally, in the above embodiment, the first ceramic frame 11
Material: Alumina (Al2O2) Thickness: 0.6 (drunk) Width: 6 [Tsuru] Depth 210 [False] The lead 16 is: Material: Kohar (product name) Width: 0.4 (m) ) Thickness: approximately 0.1 (mm), and the ground plate 13 is: Material: oxygen-free copper Thickness: 0.2 (mm) Width: 5.5 (mm) Depth: 9.6 (mm) be.

5 and 6 are a cutaway front view and a back view of essential parts showing an embodiment in which the present invention is applied to a leadless package, and are the same parts as those explained in connection with FIGS. 2 to 4. are indicated by the same symbol.

This embodiment differs from the previously described embodiments in that, like a normal leadless package, the input/output terminals are led out using metallized patterns 31 without using leads. Yes, the other configurations and effects are the same.

In this example as well, the edges of the package, and hence the metallization
A distance is provided between the tip of the pattern 31 and the ground plate 13 to the extent that no effect of capacitance occurs, and also has the effect of preventing short circuits. Incidentally, on the back side of the package, the thickness of the metallized pattern 31 and the thickness of the ground plate 13 are different, but the thickness of the ground plate 13 is set to be about 0.2 (n), for example, as described above. In particular, since the difference in thickness can be made minute, the difference in degree can be absorbed by the solder at the time of fixing. It can be implemented as

FIGS. 7 and 8 are a cutaway front view and a back view of essential parts showing an embodiment in which the present invention is applied to a DIP type nookage, and the parts explained with respect to FIGS. 2 to 6 are Identical parts are indicated by the same symbols.

This embodiment differs from the embodiments described with reference to FIGS. 2 to 4 in that the tips of the leads 16 extend downward without being bent.

The implementation of this embodiment is exactly the same as that of a normal DIP type package. That is, the surface plate 16 is inserted into the through hole formed in the board and soldered to the metallized pattern on the back side, and the ground plate 13 is inserted on the front side.
and a ground pattern are soldered together.

Effects of the Invention The semiconductor device of the present invention includes a frame made of an insulator, and a metal bonding member fixed to the back surface of the frame and having a width narrower than the width of the frame along the lead extraction direction. The structure includes a ground plate, a metal base fixed to the surface of the metal ground plate exposed inside the frame, and a semiconductor chip mounted on the metal base. By fixing the metal ground plate to the ground pattern, it is possible to mount the semiconductor device and ground the semiconductor chip.Moreover, since the semiconductor chip is grounded reliably and over the shortest distance, it is possible to connect the package and the board. Parasitic capacitance or parasitic inductance in the parts is significantly reduced, making it suitable for use in ultra-high frequency ranges or ultra-high switching speeds.

[Brief explanation of drawings]

Figure 1 is a perspective view of the main part of the conventional example, Figures 2 and 3 are a cutaway front view and rear view of the main part of an embodiment of the present invention, and Figure 4 is shown in Figures 2 and 3. 5 and 6 are cutaway front views of main parts and back views of other embodiments of the present invention. FIG. 7 is a front view with a main part cut away and a rear view thereof of still another embodiment of the invention. In the figure, 11 is the first ceramic frame, and 12 is the second ceramic frame.
13 is a metal grounding plate, 14 is a metal base, 15 is a cap, 16 is a lead, and 17 is a semiconductor chip. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Kugobe Tamamushi (3 others) Figure 2 Figure 3 Figure 4 Figure 15 Figure 5 Figure 5

Claims (1)

[Claims] A frame made of an insulator, a metal ground plate fixed to the back surface of the frame and having a width narrower than the width of the frame along the lead extraction direction, and a surface of the metal ground plate exposed inside the frame. 1. A semiconductor device comprising: a metal base fixed to a metal base; and a semiconductor chip mounted on the metal base.