JPS5975650A - Heat sink for semiconductor device - Google Patents

Heat sink for semiconductor device

Info

Publication number
JPS5975650A
JPS5975650A JP18560482A JP18560482A JPS5975650A JP S5975650 A JPS5975650 A JP S5975650A JP 18560482 A JP18560482 A JP 18560482A JP 18560482 A JP18560482 A JP 18560482A JP S5975650 A JPS5975650 A JP S5975650A
Authority
JP
Japan
Prior art keywords
heat sink
substrate
silicon nitride
semiconductor device
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18560482A
Other languages
Japanese (ja)
Other versions
JPH0361342B2 (en
Inventor
Katsumi Suzuki
克美 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP18560482A priority Critical patent/JPS5975650A/en
Publication of JPS5975650A publication Critical patent/JPS5975650A/en
Publication of JPH0361342B2 publication Critical patent/JPH0361342B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738Semiconductor materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To improve the radiation efficiency of the semiconductor device, and to mount even an ultra-high density integrated circuit easily by forming a square pole-shaped projection to one side surface of an Si or Ge single crystalline substrate and fixing a surface on the reverse side onto the back of a semiconductor substrate. CONSTITUTION:Silicon nitride films 12 are deposited on both surfaces of the silicon single crystalline substrate 11 through a CVD method, a latticed resist-pattern 13 at desired intervals is formed on either one surface of the films 12 by using optical exposure technique, etc., and another surface is coated with a resist 14. The silicon nitride film 12 is etched and removed through plasma-etching using a gas such as, CF4 gas, etc. while using the resists 13, 14 as protective films to form a desired silicon nitride film pattern 12', and the resists 13, 14 are removed. The substrate 11 is etched and removed selectively up to desired depth in an anisotropic etching liquid while using the silicon nitride films 12, and 12' as protective films to form the heat sink 11'. When the heat sink 11' and the semiconductor substrate 18 are unified, heat generated in a circuit formed on the substrate 18 is discharged effectively into a coolant such as air from the projecting sections of the surface of the heat sink 11'.

Description

【発明の詳細な説明】 この発明は半導体装置にとりつけるヒートシンクに門す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a heat sink attached to a semiconductor device.

近年半導体装置、の微細化・高密度化に伴い、装置から
発生する熱の放散が重要な制題になりつつある。従来か
かる半導体装置は、パターン密度。
In recent years, as semiconductor devices have become smaller and more dense, the dissipation of heat generated from the devices has become an important issue. Conventionally, such semiconductor devices have low pattern density.

特に配線パターン幅が少なくとも数μm以上と比較的大
きかった為、少なくとも冷却用ファン等を用いて熱を外
部へ強制的に放散させれば所望の冷却効果が得られてい
た。ところが、近年、パターン密度の増大に伴って、半
導体装置の単位面積当りから発生する熱の量が増大し、
上記の方法では十分な冷却効果が得られず、温度上昇に
よる半導体装置の特性劣化や前節の短縮が懸念されるよ
うになってきた。本発明は上記のごとき従来の半導体装
置の欠点である放熱効率を改善し、超高密度集積回路を
も容易に実装可能とし、且つ該集積回路の信頼性並びに
寿命をも大幅に商めるものである。以下1本発明の詳細
を図面を参照しながら説明する。
In particular, since the wiring pattern width was relatively large, at least several μm, the desired cooling effect could be obtained by forcibly dissipating heat to the outside using at least a cooling fan or the like. However, in recent years, with the increase in pattern density, the amount of heat generated per unit area of semiconductor devices has increased.
The above-mentioned methods do not provide a sufficient cooling effect, and there have been concerns that the characteristics of the semiconductor device may deteriorate due to temperature rise and the length of the semiconductor device may be shortened. The present invention improves the heat dissipation efficiency, which is a drawback of conventional semiconductor devices as described above, makes it possible to easily implement ultra-high-density integrated circuits, and significantly extends the reliability and life of the integrated circuits. It is. The details of the present invention will be explained below with reference to the drawings.

第1図(alから(f)に至る各図は本発明のヒートシ
ンクを備えた半導体装置を製造するときの工程を順に示
した模式断面図である。先ず、厚さ数6μmないし数組
の11103シリコン単結晶基板11の画表面上に厚さ
数百Nないし数千へのシリコン窒化膜12を通常のCV
I)法又はプラズマCVD法で堆積する((a)図)。
Each of the figures from FIG. 1 (al to (f)) is a schematic cross-sectional view showing the steps of manufacturing a semiconductor device equipped with a heat sink of the present invention in order. A silicon nitride film 12 is deposited on the surface of a silicon single crystal substrate 11 to a thickness of several hundred N to several thousand by conventional CVD.
I) method or plasma CVD method (Figure (a)).

次にシリコン窒化膜12のいずれか一方の表面上に所望
の間隔の格子状若しくはライン・アンド・スペース状し
ジストリパターン13を光学露光技術等を用いて形成し
、もう一方のシリコン窒化膜表面をレジスト14で覆う
((b)図)。しかる後、該レジスト13訃よび14を
保賎膜にして例えばCF4ガス等を用いたプラズマ・エ
ツチングでシリコン特化#2を蝕刻除去して所望のシリ
コン屋化膜パターン12’を形成し。
Next, on one surface of the silicon nitride film 12, a resist pattern 13 in the form of a lattice or line and space with a desired spacing is formed using an optical exposure technique, and the other surface of the silicon nitride film is formed. Cover with resist 14 (Figure (b)). Thereafter, using the resists 13 and 14 as a protective film, the silicon coating #2 is etched away by plasma etching using, for example, CF4 gas to form a desired silicon coating pattern 12'.

レジスト13および14を除去する((C)図)。次に
シリコンへ(化11!;S 12および12’をtri
 眸膜にして。
The resists 13 and 14 are removed (FIG. (C)). Next, to silicon (chemical formula 11!; S 12 and 12' is tri
Make it into your eyes.

fUえd:δi;とうした30重阪夕Cの水酸化カリウ
ム水浴液等の異方性111(刻液中でl 1101  
シリコン単結晶基板lif:所望の深さまで選択的に蝕
刻除去し、続いてシリコン窒化+1!412および12
’を佛とうしたリン酸を用いて蝕刻除去して、lll1
1面を111.11而で囲まれた突起を有する前記シリ
コン単結晶基板の−・部から成るピートシンク11’を
形成する((111図)。シリコン窒化膜12および1
2’tよ必ずしも除去しなくても良い。次に該ヒートシ
ンク11゛の平iF?面に数七へないし数百へ厚のチタ
ン膜15J?上ひ載1−八ないし数百へ厚の白金誤16
を4111択連続的にスパッタ蒸着する((e)図)。
fUed: δi; Anisotropy of potassium hydroxide bath solution of 30 Jusaka Yu C 111 (1101 in cutting solution)
Silicon single crystal substrate lif: selectively etched away to desired depth, followed by silicon nitridation +1!412 and 12
' was removed by etching using phosphoric acid, and lll1
A peat sink 11' is formed of the - section of the silicon single crystal substrate having a protrusion surrounded by 111.11 on one side ((Fig. 111).
2't does not necessarily have to be removed. Next, is the flat iF of the heat sink 11? A 15J titanium film with a thickness of several sevens or hundreds on the surface? Above list 1-8 to several hundred thick platinum error 16
4111 selections are continuously sputter-deposited (Figure (e)).

最後に白金薄膜16の表面上に数μm厚の金−スズ合金
層17を真空蒸着した後、約350℃に加熱し、該金−
スズ会金層17を融解させ、予め任意の回路を形成した
半導体基板18の裏面を該金−スズ合金層17に融着せ
しめ、該ヒートシンクlI′と該半導の代υにスズを用
いても拭く、まだチタン150代夛にタンタルやニッケ
ル又はクロムを用いても艮い。
Finally, a gold-tin alloy layer 17 with a thickness of several μm is vacuum-deposited on the surface of the platinum thin film 16, and then heated to about 350°C.
The tin alloy layer 17 is melted, and the back surface of the semiconductor substrate 18 on which an arbitrary circuit has been formed is fused to the gold-tin alloy layer 17, and tin is used for the heat sink lI' and the semiconductor layer υ. However, it is still possible to use tantalum, nickel, or chromium instead of titanium in the 150s.

上記のようにして形成した半導体装置に於いては、ヒー
トシンク表面に異方性蝕刻液を用いて形成した突起の為
に該半導体装置の表面積が著しく壇人する。すなわち、
半導体基板上に形成された回路に於い−C’A生じた熱
は、良導体を通してヒートシンクに伝導し、該ヒートシ
ンク表面に設けた突起部から窒気等の冷却媒体中に効果
的に放出される。該ヒートシンク表面に形成する突起の
間隔および深さは、予想される回路の発熱蓋に応じて変
えることができ、こうすることにより常に所望の放熱効
果を得ることができる。
In the semiconductor device formed as described above, the surface area of the semiconductor device is significantly increased due to the protrusions formed on the surface of the heat sink using an anisotropic etchant. That is,
Heat generated in a circuit formed on a semiconductor substrate is conducted to a heat sink through a good conductor, and is effectively released into a cooling medium such as nitrogen through a protrusion provided on the surface of the heat sink. . The spacing and depth of the protrusions formed on the heat sink surface can be changed depending on the expected heat generation cover of the circuit, thereby always achieving the desired heat dissipation effect.

また、上記実施例においてはヒートシンクの材料と17
で1111) 1面を主面にもつSi基板を用いたが、
同じダイヤモンド型の格子をもつGcの1111) l
…iを主面にもつ、≠結晶基板忙用い王もよい。
In addition, in the above embodiment, the heat sink material and 17
1111) A Si substrate with one main surface was used, but
1111) l of Gc with the same diamond-shaped lattice
...A ≠crystalline substrate with i on the main surface is also good.

本発明が提供する半導体装置れ次に示すような方法で実
装することにより、一層期著な効果を発揮することがで
きる。第2図は本孔す1」が提供する半導体装置の実装
方法の一例を模式的に示した和親1図である。ヒートシ
ンク23を設けた牛4体装置幻21は空隙を設けて立体
的に配置さJし、支柱22によって固定される。半導体
装置21の外部リードはその外周部近傍の所望の位置に
取り出し、又柱22に設りた相互配線用端子に例えばメ
タライズ導体を用いたチップキャリヤ形実装等の方法に
よって接続される。上記のようにして実装した半導体装
置は冷却効率が高いはηってなく、従来の半導体装置に
比べて小型化がり能となる。
By mounting the semiconductor device provided by the present invention in the following manner, even more remarkable effects can be achieved. FIG. 2 is a diagram schematically showing an example of a method for mounting a semiconductor device provided by Honkosu 1. A four-body cow device 21 provided with a heat sink 23 is arranged three-dimensionally with a gap and is fixed by a support 22. The external leads of the semiconductor device 21 are taken out at desired positions near the outer periphery of the semiconductor device 21 and connected to interconnection terminals provided on the pillars 22 by, for example, chip carrier type mounting using metallized conductors. The semiconductor device mounted as described above has not only high cooling efficiency but also has the ability to be made smaller than conventional semiconductor devices.

本発明の適用は、半導体集積回路に限られるもノテはな
く、半導体レーザや発光ダイオ−)”=9にも卓効を発
揮することは言うまでもない。
The application of the present invention is not limited to semiconductor integrated circuits, but it goes without saying that it is also highly effective for semiconductor lasers and light emitting diodes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は木光り]にょる半4ト休装置の製造方法の一例
を工程11に示しlE′14!、略〜r面図であシ、第
2図は本発明による半導体装置の実装方法の一例を模式
的に示した斜社1図である。図中各番号はそれぞれ次の
ものを示す。 [1・・(1101シリコン単結晶基板、 12・・・
シリコン窒fヒ膜、  13.14・・・レジスト。 12’・・・シリコン窒化膜12の一部で形成したパタ
ーン、  11’、23・・・(l l (l l シ
リコン値結晶基板11の一部で形成したヒートシンク。 15・・・チタン博Ji体、 1G・・・白金薄j摸、
   17・・・金−スズ片金pI膜、  18・・・
半導体基板。 21・・・半導体装置、 22・・・支持性。 埠1図 /cL) rh lC〕 (fン 第2図
An example of the manufacturing method of the half-fourth suspension device is shown in step 11. FIG. 2 is a perspective view schematically showing an example of a method for mounting a semiconductor device according to the present invention. Each number in the figure indicates the following. [1...(1101 silicon single crystal substrate, 12...
Silicon nitride film, 13.14...resist. 12'...Pattern formed from a part of the silicon nitride film 12, 11', 23...(l l (l l Heat sink formed from a part of the silicon value crystal substrate 11) 15...Titanium Hiroshi Ji Body, 1G... platinum thin j model,
17... Gold-tin piece gold pI film, 18...
semiconductor substrate. 21...Semiconductor device, 22...Supportability. Figure 1/cL) rh lC] (Figure 2)

Claims (1)

【特許請求の範囲】[Claims] 11101面Si単結晶基板あるいは(110)面Ge
単結晶基板の片側面に(111)面を側面とする四角柱
状の突起が設けられ、しかも前記片1!It而の反対f
111の而を1表向に半導体装置が形成さ′ILだ半導
体基板の共面に固着すべくしてなる半導体装IFt用ヒ
ートシンク。
11101-plane Si single crystal substrate or (110)-plane Ge
A square prism-shaped protrusion having a (111) plane as a side surface is provided on one side of the single crystal substrate, and the piece 1! It's the opposite of
A heat sink for a semiconductor device IFt, in which a semiconductor device is formed on one surface of 111 and is fixed to the same surface of a semiconductor substrate.
JP18560482A 1982-10-22 1982-10-22 Heat sink for semiconductor device Granted JPS5975650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18560482A JPS5975650A (en) 1982-10-22 1982-10-22 Heat sink for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18560482A JPS5975650A (en) 1982-10-22 1982-10-22 Heat sink for semiconductor device

Publications (2)

Publication Number Publication Date
JPS5975650A true JPS5975650A (en) 1984-04-28
JPH0361342B2 JPH0361342B2 (en) 1991-09-19

Family

ID=16173700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18560482A Granted JPS5975650A (en) 1982-10-22 1982-10-22 Heat sink for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5975650A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089443A (en) * 1990-05-30 1992-02-18 Prime Computer, Inc. Method of making a semiconductor heat sink
EP0999590A2 (en) * 1998-11-05 2000-05-10 Electrovac, Fabrikation Elektrotechnischer Spezialartikel Gesellschaft M.B.H. Heat sink for electric and/or electronic devices
CN106449430A (en) * 2016-11-04 2017-02-22 南开大学 Composite structure heat sink preparation method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089443A (en) * 1990-05-30 1992-02-18 Prime Computer, Inc. Method of making a semiconductor heat sink
EP0999590A2 (en) * 1998-11-05 2000-05-10 Electrovac, Fabrikation Elektrotechnischer Spezialartikel Gesellschaft M.B.H. Heat sink for electric and/or electronic devices
EP0999590A3 (en) * 1998-11-05 2006-04-05 Electrovac, Fabrikation Elektrotechnischer Spezialartikel Gesellschaft M.B.H. Heat sink for electric and/or electronic devices
CN106449430A (en) * 2016-11-04 2017-02-22 南开大学 Composite structure heat sink preparation method

Also Published As

Publication number Publication date
JPH0361342B2 (en) 1991-09-19

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