JPS5974676A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to speed up circuit actions in an SOS MOSFET by a method wherein a source and a drain region are formed only in the neighborhood of a channel region, and a metallic layer is provided in contact with both these regions. CONSTITUTION:The n<+> type source and the drain region 35 and 36 are provided, at a fixed position on a sapphire substrate 21, by alienation each other with a channel region 34 sandwiched therebetween. The metal contained semiconductor layers 37 and 37 are so provided on said substrate 21 as to contact the regions 35, 36 and a field oxide film 25, and a gate electrode 27' which contains the same metal that is contained in the layers 37 is provided on the region 34 via a gate oxide film 31. Further, an insulation wall 30 is provided around this electrode 27'. By the MOSFET of this structure, the regions 35 and 36 are formed only in the neighborhood of the region 34, the layers 37 and 37 formed in contact with the regions 35 and 36, and therefore the electric resistances of the regions 35 and 36 can be effectively reduced. Further, since a metal is introduced to the electrode 27', the electric resistances of a gate and a gate electrode reduce, and accordingly the speed-up of circuit actions can be contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which the film resistance of a semiconductor layer on an insulating substrate is improved, and a method for manufacturing the same.

[Technical background of the invention and its problems]

Conventionally, as an SOS MOS type transistor, for example, the one shown in [1] is known. 1 in the figure is a Zaphire substrate. On this substrate 1 is a four-layered n-medium type source with a field oxide film 2 .

Drain regions 3 and 4 are formed. These sources,
A p-type channel region 5 is provided between the drain regions 3 and 4. Said source.

A dirt oxide film 6 is provided on the drain regions 3, 4 and the channel region 5, and a dirt electrode 7 is provided in a portion of the dirt oxide film 6'2 corresponding to the channel region 5. The SOS MOS transistor with the Koushida structure has the source and drain regions 3 and 4 formed on the sapphire substrate 1, so it is different from the MOS transistor made of a bulk silicon substrate. , the pn junction capacitance is reduced, which has the advantage of reducing parasitic capacitance and speeding up circuit operation.

On the other hand, the electrical resistance value of the semiconductor layer that becomes the source and drain regions 3 and 4 and the wiring region (not shown) is determined by its film resistance (
ρ8), and the film resistance is inversely proportional to the depth of the semiconductor layer 1). That is, ρsocr. However, in order to lower ρ8, the bulk type MOS shown in FIG.
, 10 and n, the method of increasing L by re-diffusing impurities in the wiring layer (not shown) using a diffusion layer is SO.
This cannot be implemented with SMOS type transistors. In addition, in FIG. 2, 11 is a field oxide film, 12 is a dirt oxide film,
13 indicates a date electrode. Recently, SOSM
As OS type transistors are miniaturized, the thickness of the semiconductor layer becomes thinner and the source and drain regions 3 and 4 become thinner.
This is an even bigger problem since ρ8 tends to increase.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a semiconductor device and a method for manufacturing the same, which can reduce the electrical resistance of the source and drain regions in a MOS transistor having an insulating substrate, thereby increasing the speed of circuit operation. The purpose is to provide

[Existing requirements of the invention]

The first invention of the present application provides source and drain regions of a first conductivity type spaced apart from each other on an insulating substrate, and further provides a metal-containing semiconductor region so as to be in contact with the source and drain regions. A dirt electrode containing the same metal as that contained in the metal-containing semiconductor region is provided on the second conductivity type channel region between the drain regions via a gate oxide film, and an insulating wall is further provided around the dirt electrode. This reduces the electrical resistance of the source and drain regions and the gate electrode, thereby increasing the speed of circuit operation.

In the second invention of the present application, after forming a semiconductor layer on an insulating substrate, a dirt electrode is formed on the vaginal semiconductor layer with a gate insulating film interposed therebetween, and the gate electrode is used as a mask. The semiconductor layer is doped with impurities, an insulating wall is provided around the dirt electrode, metal atoms are introduced into the semiconductor layer using the dirt electrode and the insulating wall as a mask, and heat treatment is performed to form a source in the semiconductor layer. By forming the source and drain regions separately from each other, and forming a metal-containing semiconductor region in contact with the source and drain regions and a gate electrode containing the same metal as the metal, the source and drain regions are separated from each other.
The electrical resistance of the front electrode is reduced, thereby increasing the speed of circuit operation.

Furthermore, the insulating wall around the gate electrode according to the first and second inventions of the present application increases the distance between the metal atom-containing gate and the metal atom-containing semiconductor layer formed in contact with the source and drain regions. As a result, residues such as oxides of metal atoms generated during the manufacturing process are
This has the effect of preventing electrical short circuits between the r-gate, the source, and the drain, and improving the reliability of the SO8MOS type transistor according to the present invention.

[Embodiments of the invention]

A case where the present invention is applied to an MO8 type transistor using an ISO8 substrate will be explained based on FIGS. 3(a) to 3(f) and FIG. 4.

[1] After forming the semiconductor layer 22 by epitaxially growing silicon on the sapphire substrate 2 without cutting, a thermal oxide film 23 for the Z sofa is formed on the semiconductor layer 22. Si3N
Four films (not shown) were sequentially formed. Next, after forming a Renost film on the 5j3N4 film excluding the portion that will become the field region, chemical dry etching (C, D, E
, ) method to remove the exposed 5i5N4 film and form 5t6N.
A 4/# turn 24 was formed (as shown in FIG. 3(, )). Next, using the 513N4 pattern 24 as a mask, the thermal oxide film 2 is
After removing the semiconductor layer 22 in the thickness direction, thermal oxidation was performed to form a field oxide film 25 (as shown in FIG. 3(b)).

[11] Next, 813N4 pattern 24 and thermal oxide film 23
After peeling off, a thin oxide film 26, which will become a gate oxide film, is formed on the semiconductor layer 22 by thermal oxidation treatment. Subsequently, a polycrystalline silicon layer (not shown) was deposited on the entire surface and then patterned to form a gate electrode 27 made of polycrystalline silicon. Next, using the dirt electrode 27 as a mask, n-type impurity ions such as phosphorus are ion-implanted into the semiconductor layer 22 to form an n-medium ion-implanted layer 28.28 that will become the source and drain regions, and then the entire surface is subjected to CVD.
- An oxide film 29 was formed (as shown in FIG. 3(c)). After this, by reactive ion etching (R, I, E) method,
The CVD oxide film 29 and thin oxide film 26 were anisotropically etched to leave the oxide film 29 only around the dirt electrode 27 to form an insulating wall 30 and a dirt oxide film 3. Thereafter, molybdenum MO is ion-implanted from above to form an MO ion-implanted layer 32. which becomes a metal-containing semiconductor region into the semiconductor layer 22 and dirt electrode 27, respectively.
33 (as shown in FIG. 3(d)).

[iii] Next, heat treatment was performed. As a result, the ion-implanted layer 28 formed in the semiconductor layer 22 diffuses in the depth direction and the lateral direction', and becomes n medium-sized source and drain regions 35 and 36 through the channel region 34.
The MO ion-implanted layer 32 in 2 is similarly diffused to the base 21.
The concentration of molybdenum that reaches the surface is I x 10 ”7c
The resulting MO-containing semiconductor layers 37, 37 had a thickness of m3 or more. At this time, the specific resistance of the MO-containing semiconductor layer 37 is approximately 0.1 mΩ.
・Become a deputy. This value is 35.3 in the drain area.
While the specific resistance of No.6 is about 2.5+y+Ω·m, it is about 1/25th of that. Note that the concentration of molybdenum is 1
If it is less than x1016/c77+3, the electrical resistance of the MO-containing semiconductor layer 37 cannot be sufficiently reduced. Still, at the same time Mo
The ions are diffused in the thickness direction into the gate electrode 27, and the dirt electrode 27 becomes an MO-containing dirt electrode 27', thereby reducing the electrical resistance of the gate electrode 27. The way the electrical resistance decreases is the source.

The specific resistance of the rust, which is approximately the same as in the case of the drain, is about 1 to 2 mΩ when dogged with phosphorus, but is reduced to about 0.1 mΩ by further implanting MO ions. Subsequently, an interlayer insulating film 38 was formed on the entire surface (Fig. 3(e)).
(as shown) Next, the interlayer insulating film 38 for the drain region 36 and a portion of the Mo-containing gate electrode 27' is removed to form contact holes 39, . After forming 99, M on the entire surface
A film was deposited and patterned to form M wiring 40.40. Thereafter, a protective film 41 was formed on the entire surface, and a window for a bonding pad was opened to manufacture a 508MO8u transistor (as shown in FIGS. 3(f) and 4). Note that FIG. 4 is a plan view of FIG. 3(f), and as can be seen from FIG. 4, the Mo-containing semiconductor layer 37 in contact with the source region 35 is also used as a distribution region.

As shown in FIGS. 3(f) and 4, the MO8 type transistor manufactured as described above has n-medium sized source and drain regions 35 and 36 placed at predetermined positions on the sapphire substrate 21, sandwiching the channel region 34 between them. A source is placed on the same substrate 21 and spaced apart from each other.

A Mo-containing semiconductor layer 37.37 is provided in contact with the drain regions 35, 36 and the field oxide film 25, a Mo-containing dirt electrode 27' is provided on the channel region 34 via the gate oxide film 31, and further r-) electrode 27'
It has a structure in which an insulating wall 30 is provided around the .

According to the MO8 type transistor having the above-described structure, the source and drain regions 35 and 36 are formed only in the vicinity of the channel region 34, and the specific resistance of these source and drain regions 35 and s is higher than that of these source and drain regions. Area smaller than 35°36 (01mΩ・cm)
Since the Mo-containing semiconductor layers 97 and 37 are formed in contact with each other, in the method of the present invention, the electric potential of the source and drain regions 35 and 36 is reduced compared to the conventional source and drain regions formed only from semiconductor layers in which impurities are diffused at a high concentration. The resistance can be effectively reduced. Furthermore, since the gate electrode is also introduced, the electrical resistance of the dirt electrode serving as the gate and wiring is also reduced.

Therefore, the circuit operation can be made faster than the conventional 508MO8 type transistor shown in FIG. fact,
The oscillation frequency of the 41-stage ring oscillator formed by the SO8MO8 type transistor formed according to the present invention is compared with the frequency of the SO8MO8 type transistor constructed by the conventional method in the same pattern as shown in the following table.

In the table below, methods for introducing metal atoms into the semiconductor layer include (1) ion implantation method, (2) CVD method+
(3) sputter deposition method + heat treatment, and platinum, molybdenum, and parazoum were used as metal atoms, respectively.

From the above table, it was confirmed that the SO8MO8 type transistor according to the present invention can increase the oscillation frequency by about 10 to 40% compared to the conventional transistor, thereby increasing the circuit operation by about 10 to 40%.

Furthermore, an insulating wall 30 around the dart electrode 27 in the present invention
This has the effect of improving the electrical reliability between the MO-containing dirt electrode 27 and the Mo-containing semiconductor layer.

If this insulating wall 30 is thick, when Mo is ion-implanted, the Mo-containing portion in the dirt electrode 27 and the Mo-containing semiconductor layer 37 in contact with the source and drain regions 35 and 36 are separated by a distance equal to the thickness of the dirt oxide film. During the subsequent thermal process, the residual liquid of No oxide becomes f-) oxidation 1]4% 3J
A gully is generated on the first wall of the gate electrode 27 and the source and drain regions. 5, 36
The withstand voltage between the two ends will deteriorate. Kate electrode, 27 fM OB
t:D Ee green wall 30 at 6000X (2) Film thickness No.C
VD - When formed with oxide film and without forming an insulating wall.
With 1 loop, the latter has a yield rate of about 40% of the former, and in the 1000-hour initial operation test, the former had almost no defects, whereas the latter had about 20 percent of defects. Ta. As a result, it was confirmed that the insulating wall 30 around the gate electrode of the present invention improves the reliability including the yield of the SO8MO8 type transistor.

In the above embodiments, sapphire was used as the non-sustainable substrate, but the present invention is not limited to this, and for example, spinel, an SjO film on a Si substrate, or s 13N4 jQ may be used.

In the above embodiments, impurity doping into the semiconductor layer was performed by ion implantation, but the present invention is not limited to this, and thermal diffusion may also be used. Furthermore, in the above embodiment, impurity ion implantation was performed before forming an insulating wall around the gate electrode.
The manufacturing method is not limited to this. For example, in Figure 5 (
As shown in a), an insulating wall 3θ was formed, and Mo ion implantation layers 42 and 43 were formed on the semiconductor layer 22 and the cathode electrode 27. Subsequently, as shown in FIG. 2B, after ion-implanting phosphorus into the semiconductor layer 22, heat treatment is performed taking advantage of the fact that the diffusion coefficient of phosphorus is larger than that of Mo. , 36, a Mo-containing semiconductor layer 37, 37 and a Mo-containing gate electrode 27' may be formed to connect these source and drain regions 35 and 36. In this way, the effective channel length can be made approximately the same as the width of the gate electrode 27'.

In the above embodiment, the ion implantation method is used as a means for introducing molybdenum into the semiconductor layer, but the method is not limited to this. For example, a Mo layer may be formed on the entire surface of the insulating substrate including the gate electrode and the semiconductor layer using a sputter deposition method or a CVD method, and then heat treated to introduce the Mo layer into the semiconductor layer.

That is, first, as shown in FIG.
An O layer 44 was formed over the entire surface by sinter deposition or CVD. Subsequently, as shown in FIG. 4B, a heat treatment is performed to diffuse molybdenum in the Mo layer 44 into the semiconductor layer 22 and the dirt electrode 27, and the Mo-containing semiconductor layer 45 and Mo
Containing gate electrode 27 and source and drain regions 46.
After forming 47, the Mo layer 44 remaining on the surface was removed with aqua regia. In this way, M
Since the Mo-containing semiconductor layer 45 with a high O content concentration can be formed, the electrical resistance of the source and drain regions 46 and 47 can be further reduced.

In the above embodiments, the diffusion of molybdenum introduced into the semiconductor layer is carried out by heat treatment, but the method is not limited to this for thermal annealing. Irradiation or ion beam irradiation may also be performed. In the examples shown in FIGS. 3 and 5 above, the Mo ion-implanted layer was diffused until it reached the substrate, but the present invention is not limited to this. The thermal diffusion temperature may also be lowered to make the depth of the Mo-containing semiconductor layer shallower so that it does not reach the substrate.

In the above embodiment, molybdenum was used as the metal atom, but examples include tungsten, platinum, gold, palladium, nickel, cobalt, iron, chromium, tantalum, niobium, vanadium, hafnium, zirconium, titanium, etc. May be used.

〔Effect of the invention〕

As detailed above, the present invention provides a semiconductor device and a method for manufacturing the same, which can improve circuit operation by about 10 to 40% by reducing the electrical resistance of source and drain regions and date electrodes compared to the conventional one. It is possible.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional SO8MO8 type transistor.
FIG. 2 is a cross-sectional view of an MO8 type transistor using a conventional bulk silicon substrate, FIGS. 3(a) to (f) are plan views of an SO8MO3 type transistor according to the present invention, and FIGS. FIGS. 6(a) and 6(b) are cross-sectional views showing a method for manufacturing an SO8MO3 type transistor according to another embodiment of the invention in order of steps. 21... Sapphire base, 22... Semiconductor layer, 27
...Kate electrode, 27'...Mo-containing dirt electrode, 28...N-type impurity ion implantation layer, 29...CV
D - Oxide film, 30... Insulating wall, 31... Kate oxide film 1, ? 2, ? 3, 42, 4.3-
Mo ion implantation layer, 34...channel region, 35
．． 46... Source region, 36.47... Drain region, 37.45... MO-containing semiconductor layer, 39... Contact hole, 40... A2 wiring, 4th... Protective film, 44 ...Mo layer. Applicant's Representative Patent Attorney Takehiko Suzue No. 10-7 (a) Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. An insulating substrate, a first conductivity type source and drain region provided on the substrate at a distance from each other, and a metal provided on the substrate in contact with the source and drain regions. a gate electrode containing the same metal as the metal contained in the metal-containing semiconductor region and provided on the channel region of the second conductivity type between the source and drain regions via a gate oxide film; , and an insulating wall provided around a gate electrode. 2 The insulating substrate is zaphire or spinel. The semiconductor device according to claim 1, wherein the semiconductor device is one of a 5IO2 film on a St substrate or a 5i5N4 film. 3. The semiconductor device according to claim 1, wherein the metal-containing semiconductor region is in contact with an insulating substrate. 4. In the metal-containing semiconductor region, I x 10”7cm
The semiconductor device according to claim 1, characterized in that the semiconductor device contains three or more metal atoms. 5. A step of forming a semiconductor layer on an insulating substrate, a step of forming a dirt electrode on this semiconductor layer via a dirt insulating film, and adding impurities to the semiconductor layer using the gate electrode as a mask. a step of providing an insulating wall around the gate electrode; a step of introducing metal atoms into the semiconductor layer and the gate electrode using the gate electrode and the insulating wall as a mask; Manufacturing a semiconductor device comprising the steps of applying heat treatment to form source and drain regions in a semiconductor layer separately from each other, and forming a metal-containing semiconductor region in contact with the source and drain regions. Method. 6. Claims characterized in that the insulating wall is formed by forming an insulating film on the entire surface of the semiconductor layer and insulating layer on an insulating substrate including dart electrodes, and then removing this insulating film anisotropically. 6. The method for manufacturing a semiconductor device according to item 5. 7 At least one of ion implantation, sputter deposition, and CVD as a means of introducing metal atoms into the semiconductor layer.
Claim 5, characterized in that two methods are used.
A method for manufacturing a semiconductor device according to section 1. 8. Claim 5, characterized in that at least one of heating, heat ray irradiation, laser light irradiation, electron beam irradiation, and ion beam irradiation is performed as means for diffusing the metal atoms that have entered 2rfI into the semiconductor layer. A method of manufacturing the semiconductor device described above. 9. Claim 5, characterized in that in the step of anisotropically removing the insulating film to form the insulating wall, a reactive ion etching method is used as an anisotropic removing means for the insulating film. A method for manufacturing a semiconductor device according to section 1. 10. Metal atoms include molybdenum, tungsten, platinum, gold, haladium, nickel, cobalt, iron, chromium,
6. The method of manufacturing a semiconductor device according to claim 5, wherein at least 951 types of tantalum, niobium, vanadium, hafnium, zirconium, and titanium are used.