JPS5972735U

JPS5972735U - One-dimensional array element

Info

Publication number: JPS5972735U
Application number: JP16796882U
Authority: JP
Inventors: 上西　勝三; 岩「淵」　俊之; 勝昭坂本
Original assignee: 沖電気工業株式会社
Priority date: 1982-11-08
Filing date: 1982-11-08
Publication date: 1984-05-17

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の一次元アレイ化素子の製造方法を示す模
式図、第２図はこの考案の一次元アレイ化素子の一実施
例のパターン化接続図、第３図はこの考案の一次元アレ
イ化素子の一実施例を示す接続図、第４図は第３図の一
次元アレイ化素子における駆動回路ＩＣの構成の一例を
示すブロック図、第５図はこの考案の一次元アレイ化素
子の他の実施例を示す接続図である。ａ□〜屯、ｂ□〜ｂ５，１１・・・素子、１２・・・セ
レクタ端子、１３．３３・・・駆動回路ＩＣ，１４，１
５・・・接続点、１６・・・電源、信号入力端子、１７
・・・パターン化接続線、２１・・・データ入力線、２
２・・・第１クロツク線、２３・・・シフトレジスタ、
２ノ・・・第２クロックＬ２５−・・ラッチ、２６・・
・ドライバ、２７・・・出力線。Fig. 1 is a schematic diagram showing a conventional method for manufacturing one-dimensional arrayed elements, Fig. 2 is a patterned connection diagram of an embodiment of the one-dimensional arrayed element of this invention, and Fig. 3 is a one-dimensional one-dimensional arrayed element of this invention. FIG. 4 is a block diagram showing an example of the configuration of the drive circuit IC in the one-dimensional arrayed element of FIG. 3, and FIG. 5 is the one-dimensional arrayed element of this invention. It is a connection diagram which shows another Example. a□~tun, b□~b5, 11... element, 12... selector terminal, 13.33... drive circuit IC, 14, 1
5... Connection point, 16... Power supply, signal input terminal, 17
...Patterned connection line, 21...Data input line, 2
2...first clock line, 23...shift register,
2 No. 2nd clock L25--Latch, 26...
・Driver, 27...output line.

Claims

[Scope of utility model registration request]

A large number of elements arranged on the same substrate are divided into blocks, and in each block, the elements of adjacent blocks are connected by patterned connection lines in numerical order and reverse numerical order on the substrate. , a one-dimensional array element formed by connecting the patterned connection lines of the two or four adjacent blocks to one drive circuit element.