JPS6024120U - line display device - Google Patents
line display deviceInfo
- Publication number
- JPS6024120U JPS6024120U JP11259583U JP11259583U JPS6024120U JP S6024120 U JPS6024120 U JP S6024120U JP 11259583 U JP11259583 U JP 11259583U JP 11259583 U JP11259583 U JP 11259583U JP S6024120 U JPS6024120 U JP S6024120U
- Authority
- JP
- Japan
- Prior art keywords
- line
- display
- line display
- shift register
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Audible And Visible Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図及び第2図は従来のライン表示装置を示すブロッ
ク図、第3図は本考案の一実施例を示すブロック図、第
4図は第3図におけるライン表示器の具体的構成例を示
す回路図、第5図及び第6図は本考案の他の実施例を示
す要部回路図である。
2.21・・・コントローラ、2A・・・制御回路、4
A、4B、4C・・・ライン表示器、5A、 5B、
5C・・・信号ケーブル、LED・・・表示素子、
SR・・・シフトレジスタ。1 and 2 are block diagrams showing a conventional line display device, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 shows a specific example of the configuration of the line display device in FIG. 3. The circuit diagrams shown in FIGS. 5 and 6 are main circuit diagrams showing other embodiments of the present invention. 2.21...Controller, 2A...Control circuit, 4
A, 4B, 4C... Line indicator, 5A, 5B,
5C...signal cable, LED...display element,
SR...Shift register.
Claims (1)
素子を配列する少なくとも1つのライン表示器上の該表
示素子の順次点灯制御で表示するライン表示装置におい
て、上記ライン表示器は上記表示素子及び該表示素子に
順次各ビット出力を与えて点灯制御するシフトレジスタ
を有する構成とし、ライン表示すべき制御信号を発生す
るコント、 ローラはライン表示器のシフトレジスタに
クロック信号とリセット信号を与えるための信号ケーブ
ルで1つのライン表示器と結合し、各ライン表示器間は
前段のライン表示器のシフトレジスタの最終ビット出力
を後段のライン表示器のシフトレジスタのクロック入力
とする構成にしたことを特徴とするライン表示装置。In a line display device that displays the progressing operating state of a system line by sequential lighting control of display elements on at least one line indicator in which display elements are arranged according to the system line, the line indicator is configured to display the display elements and the display elements. It has a configuration that includes a shift register that sequentially supplies each bit output to the display element to control lighting, a controller that generates control signals for line display, and a roller that supplies clock signals and reset signals to the shift register of the line display. It is characterized by being connected to one line display by a cable, and between each line display, the final bit output of the shift register of the previous line display is used as the clock input of the shift register of the subsequent line display. line display device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11259583U JPS6024120U (en) | 1983-07-20 | 1983-07-20 | line display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11259583U JPS6024120U (en) | 1983-07-20 | 1983-07-20 | line display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6024120U true JPS6024120U (en) | 1985-02-19 |
Family
ID=30260967
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11259583U Pending JPS6024120U (en) | 1983-07-20 | 1983-07-20 | line display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6024120U (en) |
-
1983
- 1983-07-20 JP JP11259583U patent/JPS6024120U/en active Pending
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