JPS5968680A - Level measuring device - Google Patents

Level measuring device

Info

Publication number
JPS5968680A
JPS5968680A JP17931582A JP17931582A JPS5968680A JP S5968680 A JPS5968680 A JP S5968680A JP 17931582 A JP17931582 A JP 17931582A JP 17931582 A JP17931582 A JP 17931582A JP S5968680 A JPS5968680 A JP S5968680A
Authority
JP
Japan
Prior art keywords
waveform
points
time
discrimination
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17931582A
Other languages
Japanese (ja)
Inventor
「淵」 辰夫
Tatsuo Fuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17931582A priority Critical patent/JPS5968680A/en
Publication of JPS5968680A publication Critical patent/JPS5968680A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/12Measuring rate of change

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE:To shorten the measurement time, by measuring a little earlier the waveform level than usual if the stabilizing time characteristic of a waveform has reproducibility. CONSTITUTION:A means which attains a pair of time data close to each other after stabilization of a waveform to be measured, a means which discriminates whether one waveform level is within a set limit value, a means which attains the inclination of the rise time of the waveform, and a means which repeats said measurement if the waveform level is not within the allowable limit are provided. When the measuring principle is indicated, waveform levels at points A and B are measured, and the inclination of the rise time is attained on a basis of the difference of waveform level between points A and B if the value at the point A is within the set limit, but discrimination of the inclination is judged to be terminated if it is not within the set limit. When discrimination is not terminated because values at points A and B are not within the limit, waveform levels at points C and D are measured similarly; and when discrimination is not terminated with points C and D, the final discrimination is performed only with a normal discrimination position E.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体集積回路特に相補MO8型集積回路のD
C(直流)測定に用いた場合に適するレベル測定装置に
関する。
Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit, particularly a complementary MO8 type integrated circuit.
The present invention relates to a level measuring device suitable for use in C (direct current) measurement.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

生勇1体(l+fl定装随においては、第11のタイム
チャートのようにDC回路払gt時同中に、高圧或いは
電流が被測定物(集稙助:路)に加わシ、成る点(端子
、ビン)の高圧または& 訛を判定する。しかしながら
通算は第2図に示すように、測定したいデータが完全に
安定してしまった後判定しているので、安定まで多くの
時間を必要とし、カ」定に長時間を要していた。
In the l + fl fixed installation, as shown in the 11th time chart, at the same time as the DC circuit is turned on, there is a point where high voltage or current is applied to the object to be measured (Shukensuke: path). However, as shown in Figure 2, the total is judged after the data to be measured has become completely stable, so it takes a long time to stabilize. , it took a long time to fix.

そこで、本発明者は、八も2図の安定時間特性に再現性
がある場合、ごλ2図の位置aで判定した方が測定時間
を短かくできる点に着目した。
Therefore, the inventor of the present invention focused on the fact that when the stability time characteristics in the λ2 diagram are reproducible, the measurement time can be shortened by making the determination at the position a in the λ2 diagram.

〔発明の目的〕[Purpose of the invention]

発明ユ、は上配実怪に鉦みてなさjたもので、波形の安
定時間特性に再現性がある場ひ、波形レベルを早めに計
」定することにより、測定時間短縮できるレベル測定装
置を提u(シようとするものである。
The invention was based on a practical experience, and it is a level measuring device that can shorten the measurement time by measuring the waveform level early if the waveform stabilization time characteristics are reproducible. It is something that is intended to be done.

〔発明の概要〕[Summary of the invention]

本発明は、被測定波形の安定化後、近接した一対の時間
データを得、前記時間データの一方の時の波形レベルと
傾きが許容リミット内にある時得られた波形f直から、
被測定波形の安定値を再現できるようにしたものである
The present invention obtains a pair of adjacent time data after stabilizing the measured waveform, and from the waveform f obtained when the waveform level and slope of one of the time data are within the permissible limit,
This allows the stable value of the measured waveform to be reproduced.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して本発明の一夾施例を説明する。第3
図は本実施例の迎j定原理を示したもので、まずA、B
点の波形レベルを測定し、A点での値が設定リミット内
に入っているか否かを判断し、もし設定リミット内であ
れはAとBの差よシ立ち上がシ (立ち下がシの場合で
も同じ)時間の傾きを求めて、この領置も予定リミット
内であるとき判定が終了したものとする。
Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Third
The figure shows the fixed principle of this embodiment. First, A, B
Measure the waveform level at point A, judge whether the value at point A is within the set limit, and if it is within the set limit, calculate the difference between A and B as The same applies in the case of 2)) The slope of the time is calculated, and the determination is deemed to have been completed when this placement is also within the scheduled limit.

A、B点で判定が終了しない場合C,D点についてもA
、B点の場合と同様に行なう。勿論求める波形レベルの
値はA点または0点からE点側にシフトした値として求
める。もしC,D点でも判定が終了しない場合は通常の
判定位置であるE点で、このE点での値のみ最終的に判
定するものとする。
If the judgment does not end at points A and B, also A for points C and D.
, carry out the same procedure as for point B. Of course, the value of the waveform level to be determined is determined as a value shifted from point A or point 0 to point E. If the determination is not completed even at points C and D, the determination is made at point E, which is the normal determination position, and only the value at point E is finally determined.

第4図は上記第3図の原理を具体化した測定装置で、(
1)はカウンタ (タイマ)、2〜5は時間データ収納
用ラッチで、ラッテ2には安定時間開始点0−)Aのデ
ータが、ラッチ3にはA→Bのデータが、ラッテ4には
B−)Cのデータが、ラッチ5にはC−+Dのデータ 
(それぞれ設定値)が収納さnる。6はカウンタ、7は
デコーダ、8は単安定マルチバイブレータ、9はフリッ
プフロップ、10はシフトレジスタ、11〜14はラッ
チ、15.16はコンパレータ、17はA/Dコンバー
タ、18はBIN(2進)/BCD (2進化10進)
変換部、19はDCコンパレータ、20〜22はA−D
点の設定リミットデータが入るラッチ、23はカウンタ
、24はデコーダ、25はラッチ、26は減算器、27
−36はアンド回路、37〜42はオア回路、43.4
4はインバータである。
Figure 4 shows a measuring device that embodies the principle shown in Figure 3 above.
1) is a counter (timer), 2 to 5 are latches for storing time data, Latte 2 holds the data of stable time start point 0-)A, Latch 3 holds the data from A→B, and Latte 4 holds the data of stable time starting point 0-)A. B-) Data of C is stored in latch 5, data of C-+D is stored in latch 5.
(each setting value) is stored. 6 is a counter, 7 is a decoder, 8 is a monostable multivibrator, 9 is a flip-flop, 10 is a shift register, 11 to 14 are latches, 15.16 is a comparator, 17 is an A/D converter, 18 is a BIN (binary) )/BCD (binary coded decimal)
Conversion unit, 19 is a DC comparator, 20 to 22 are A-D
23 is a counter, 24 is a decoder, 25 is a latch, 26 is a subtracter, 27
-36 is an AND circuit, 37-42 is an OR circuit, 43.4
4 is an inverter.

次に第4図の栴成の動作を説明する。第3図の安定時間
開始点0→A、A−)B、B−)C,C→Dの時間をと
るため、第4図のカウンタ1をタイマに使用し、ラッチ
2〜5はタイマ1に時間をセットする時間データが入っ
ている。カウンタ6はリセットされているので、デコー
ダ7はラッチ2〜5にラッチされたデータよシラツテ2
を選択し、0→Aのデータがカウンタ1にセットされる
。ゲート34よリスタート信号が入シ、フリップフロッ
プ9をプリセットし、10 KHzクロックのゲート3
6を開き、カウンタ1がダウンカウントを始める。カウ
ント値が10“になるとボローパルスが発生し、カウン
タ6をゝ+1“ し、次のA−)Bのタイマデータをカ
ウンタ1にセットする。すると10 KHzクロックは
入っているので、カウンタlはすぐにダウンカウントを
始める。以下同様にタイマが順次動作し、デコーダ1よ
りゲート39を通り、フリップフロップ9を介して10
 iG3.zクロックを止める。
Next, the operation of the separator shown in FIG. 4 will be explained. In order to take the time from the stabilization time starting point 0→A, A-)B, B-)C, C→D in FIG. 3, counter 1 in FIG. 4 is used as a timer, and latches 2 to 5 are Contains time data to set the time. Since the counter 6 has been reset, the decoder 7 uses the data latched in the latches 2 to 5 to
is selected, and data from 0 to A is set in counter 1. A restart signal is input from the gate 34, presetting the flip-flop 9, and starting the gate 3 of the 10 KHz clock.
6 and counter 1 starts counting down. When the count value reaches 10'', a borrow pulse is generated, the counter 6 is incremented by 1, and the next timer data of A-)B is set in the counter 1. Then, since the 10 KHz clock is on, the counter l immediately starts counting down. Thereafter, the timers operate sequentially in the same manner, passing through the gate 39 from the decoder 1, and passing through the flip-flop 9 to the 10
iG3. z Stop the clock.

一方、カウンタ1のボロー信号によ、9A−D点の測定
値を読むため、A/Dコンバータ17にスタート信号を
送る。またシフトレジスタ10より各パルスを発生する
。A/Dコンノ(−タ17で変換されたデータはA点、
0点の時ゲート3)によシラツテ25にラッチされる0
次にB点、D点の時は、前にラッチされたA点。
On the other hand, in response to the borrow signal from the counter 1, a start signal is sent to the A/D converter 17 in order to read the measured values at points 9A-D. Further, each pulse is generated from the shift register 10. A/D converter (data converted by -ta 17 is at point A,
When the score is 0, the gate 3) is latched by the gate 25.
Next, at point B and point D, it is the previously latched point A.

0点のデータと現在のデータの差が減算器26よシ出力
でれる。こnを波形の傾きのデータとする。ラッチ11
.12にはA、B点間の判定リミットが、またラッチ1
3.14にはC,D点間のリミットがラッチされている
。ラッチ11、12,13.24のデータはオア回路4
1.42でB点とD点を切シ換えら几てコンパレータ1
5,16で判定される〇 −力、A/Dコンバーク17で変換されたデータは、B
IN/BCD変換部18で2進からBCDコードに震挨
され、DCコンノ(レーク19に入る。このDCコンパ
レーク判定で)くスであり、しかも傾き判定でもバスで
あった時は、ゲート32よシゲート39へ信号を送って
タイマ1をストップし、次のテストへ進む。もしノ(ス
でない時は、ゲート33よシカウンタ2.9 Kクロツ
クラ送υ、DCコンパレータ19のリミットを次のB→
D点、またはD−)E点のリミットに変更する。第5図
は上記動作を示すタイムチャートである。
The difference between the 0 point data and the current data is output from the subtracter 26. Let this n be the data of the slope of the waveform. latch 11
.. 12 has the judgment limit between points A and B, and latch 1
In 3.14, the limit between points C and D is latched. Data of latches 11, 12, 13.24 is OR circuit 4
1. Switch between point B and point D at 42 and comparator 1
5, 16, the data converted by A/D converter 17 is B
The IN/BCD converter 18 converts the binary code into a BCD code, and enters the DC conno (rake 19).If the DC comparator determines that it is a bus, and the slope also determines that it is a bus, then the Send a signal to the gate 39 to stop timer 1 and proceed to the next test. If not, gate 33, counter 2.9
Change to the limit of point D or D-) point E. FIG. 5 is a time chart showing the above operation.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によれば、波形レベルを早めに
測定するようにしたので、乗積回路のD CIiJ定な
どの場合測定時間を大幅に短縮できるレベル測定装置が
提供できるものである。
As explained above, according to the present invention, since the waveform level is measured early, it is possible to provide a level measuring device that can significantly shorten the measurement time when determining the DCIiJ of a multiplication circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は乗積回路のDC測定タイミングを示す波形図、
第2図はその被測定波形図、第3図は本発明の一実施例
の測定原理を示す波形図、第4図は同実施例の具体的構
成図、第5図は同構成の動作を示すタイムチャートであ
る。 1・・・カウンタ (タイマ)、2〜5・・・ラッチ、
6・・・カウンタ、7・−デコーダ、9・・・フリップ
フロップ、10・・・シフトレジスタ、IJ〜14・・
・ラッチ、ノ5,16・・−コンパレータ、17・・・
A/Dコンバータ、18・・・BIN/BCD変換部、
19・・・DCコンパレータ、20〜22・・・ラッチ
、23・・・カウンタ、24・・−デコーダ、25・・
・ラッチ、26・・・減算・詣。 出願人代理人 弁理士 鈴  江  武 ′彦: − Q () 叉夕幀耐−傾一
Figure 1 is a waveform diagram showing the DC measurement timing of the multiplication circuit.
Fig. 2 is a waveform diagram to be measured, Fig. 3 is a waveform diagram showing the measurement principle of an embodiment of the present invention, Fig. 4 is a specific configuration diagram of the embodiment, and Fig. 5 shows the operation of the same configuration. FIG. 1...Counter (timer), 2-5...Latch,
6... Counter, 7... Decoder, 9... Flip-flop, 10... Shift register, IJ~14...
・Latch, No. 5, 16... - Comparator, 17...
A/D converter, 18...BIN/BCD conversion section,
19...DC comparator, 20-22...Latch, 23...Counter, 24...-decoder, 25...
・Latch, 26... Subtraction/Pilgrimage. Applicant's representative Patent attorney Takeshi Suzue: - Q ()

Claims (1)

【特許請求の範囲】[Claims] 被測定波形の安定化後、近接した一対の時間データを得
る手段と、前記時間データの一方の時の波形レベルが設
定リミット値内にあるが否かを判定する手段と、前記各
時間データの差から前記波形の立ち上がりまたは立ち下
がシ時間の傾きを得る手段と、前記波形レベルと傾へか
許容リミット内にある時測足を終了し許容リミット同I
/cない時は前記同様の測定を繰シ返えし行なう手段と
を具備したことを特徴とするレベル沖j定装置。
After the waveform to be measured is stabilized, means for obtaining a pair of adjacent time data; means for determining whether a waveform level at one of the time data is within a set limit value; means for obtaining the slope of the rising or falling time of the waveform from the difference; and means for terminating the measurement when the waveform level and slope are within the permissible limit;
1. A level off-shore measuring device, characterized in that it is equipped with means for repeatedly carrying out the same measurements as described above when the above-mentioned conditions are not met.
JP17931582A 1982-10-13 1982-10-13 Level measuring device Pending JPS5968680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17931582A JPS5968680A (en) 1982-10-13 1982-10-13 Level measuring device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17931582A JPS5968680A (en) 1982-10-13 1982-10-13 Level measuring device

Publications (1)

Publication Number Publication Date
JPS5968680A true JPS5968680A (en) 1984-04-18

Family

ID=16063679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17931582A Pending JPS5968680A (en) 1982-10-13 1982-10-13 Level measuring device

Country Status (1)

Country Link
JP (1) JPS5968680A (en)

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