JPH06351170A - Charge current detecting circuit - Google Patents

Abstract

PURPOSE:To provide a charge current detecting circuit for quickly and accurately detecting the end of charge of an electrostatic capacitance. CONSTITUTION:A current is detected in different timings with a couple of sample and hold circuits 20, 21 and the signal held by the sample and hold circuits 20, 21 is subtracted in a subtractor 22 to obtain a difference of current. The difference obtained is compared with the reference voltages V1, V2, V3, with comparatos 23, 24, 25. A current difference is decided depending on the result of comparison to control the timing of sample of the sample and hold circuits 20, 21. When a difference is fixed to almost zero, a charge end signal is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charging current detecting circuit, and more particularly to a charging current detecting circuit for detecting the completion of charging of a capacitance.

When measuring resistance, a method is generally used in which a constant voltage is applied to an object to be measured and the current flowing through the object is measured. However, the electronic components and printed wiring boards that are the objects of measurement generally contain capacitance, and if the measurement is performed as it is, in addition to the current supplied to the resistor at the beginning of the measurement, the charging current to the capacitance is also the current. As a result, a measurement error occurs, and accurate resistance measurement cannot be performed.

However, this charging current has a characteristic that it gradually decreases with a coefficient determined according to the value of electrostatic capacity and the value of resistance, and finally becomes zero. Therefore, in order to perform resistance measurement with high accuracy, control is required to start measurement when the charging current becomes zero or reaches a value that is not affected by an error. In order to carry out this control, a circuit for judging the measurement start point was necessary.

[0004]

2. Description of the Related Art FIG. 7 shows a block diagram of an embodiment of the present invention. In the figure, 10 indicates a measurement target. Measurement target 1
Reference numeral 0 denotes an electronic component, a printed wiring board, etc., which includes a capacitance as well as a resistance. Therefore, the equivalent circuit of the measuring object 10 has a resistance R
And a capacitor C in parallel.

Reference numeral 11 represents a resistance measuring device. The resistance measuring device 11 includes a switch 12, a current detector 13, a DC power supply 14,
Voltage detector 15, charging current detector 16, A / D converter 1
The measurement target 10 is connected between the terminals T ₁₁ and T ₁₂ and includes a controller 7, and a controller 19.

The terminal T ₁₁ has a switch 12 and a current detector 1.
3 is connected to the positive side of the DC power supply 14. The terminal T ₁₂ is connected to the negative side of the DC power supply 14.

The switch 12 is controlled by a switch control signal from the controller 19, and is turned on when the resistance is measured and turned off after the measurement is completed. The current detection unit 13 detects the current I ₁₁ flowing through the terminal T ₁₁ when the switch 12 is turned on, generates a current detection signal corresponding to the detection current I ₁₁ , and charges the current detection unit 16 and the A / D converter 1.
Supply to 7.

The charging current detector 16 detects the charging current of the capacitor C on the basis of the current detection signal, and when the charging of the capacitor C is completed, supplies a charging completion signal to the controller 19.

The A / D converter 17 has a current detector 13
The current detection signal supplied from is converted into a digital signal and supplied to the controller 19.

The voltage detector 15 is connected to both ends of the DC power supply 14, detects the voltage of the DC power supply 14, generates a voltage detection signal according to the voltage, and supplies the voltage detection signal to the A / D converter 18. The A / D converter 18 converts the voltage detection signal supplied from the voltage detection unit 15 into a digital signal and supplies the digital signal to the controller 19.

The controller 19 receives a measurement instruction signal from the outside, a charging completion signal from the charging current detector 16, a digital signal corresponding to the current I ₁₁ flowing from the A / D converter 17 to the measurement object 10, and the A / D converter 18. A digital signal corresponding to the voltage of the DC power supply 14 is supplied from the DC power supply 14 to generate a switch control signal for controlling the switch 12 and the measurement target 10
Calculate the resistance value of. At this time, the resistance R of the measurement target 10
Is calculated from the voltage V applied to the measuring object 10 and the current I flowing through the measuring object 10 by the voltage V as R = V / I.

FIG. 8 shows a block diagram of an example of the conventional charging current detector 16. The conventional charging current detector 16 is composed of a differentiating circuit 40 and a comparator 41.

The differentiating circuit 40 includes a resistor R ₂ and a capacitor C
₂ , the change in the current detection signal detected by the current detection unit 13 is alleviated and the result is supplied to the non-inverting input terminal of the comparator 41. A reference voltage is applied to the inverting input terminal of the comparator 41, the comparator 41 compares the current detection signal supplied via the differentiating circuit 40 with the reference voltage, and when the current detection signal becomes smaller than the reference voltage, it becomes high level. Output a signal.

Conventionally, the output of the comparator 41 has been used as a charge completion signal.

Next, the operation of the entire apparatus will be described. FIG. 8 shows an operation explanatory diagram of the controller 19.

When the resistance is to be measured by the resistance measuring device 11, the measuring object 10 is connected to the terminals T ₁₁ and T ₁₂ ,
A measurement instruction signal is supplied by operating a switch or the like. The measurement instruction signal is supplied to the controller 19, and the controller 19 first turns on the switch 12 according to the measurement signal (steps S1 and S2).

Next, the controller 19 controls the charging current detector 1
It is determined whether the charging completion signal is supplied from 6 (step S3). The controller 19 waits until the charging completion signal is supplied, and if the charging completion signal is supplied, it means that the charging of the electrostatic capacitance in the measurement target 10 is completed.
Since the resistance can be measured, the controller 19 next reads the current value from the current detection unit 13 via the A / D converter 17 and the voltage value from the voltage detection unit 15 via the A / D converter 18. The resistance value is read, the resistance value is calculated from the above-mentioned equation (1), and the result is output (step S4).

After calculating the resistance value, the controller 19 turns off the switch 12 by the switch control signal and completes the measurement operation (step S5).

[0019]

However, the conventional charging current detection circuit relaxes the current detection signal by the differentiation circuit,
Since the comparison with the reference voltage was performed by the comparator, FIG.
As shown in (A), when the current changes rapidly or when a high frequency is input to the circuit, it resonates with the differentiating circuit and FIG.
When oscillation occurs as shown in (B) or when the change in current is gradual as shown in FIG. 10 (C), the sensitivity becomes dull as shown in FIG. 10 (B), and detection cannot be performed. Since the differentiating circuit has a capacitor, there is a problem that a waiting time after the current detection signal is supplied is required and it takes a long time for measurement.

Furthermore, since minute fluctuations in the current detection signal cannot be detected, there is a problem in that the completion of charging cannot be detected accurately.

The present invention has been made in view of the above points, and an object of the present invention is to provide a charging current detection circuit that can detect the completion of charging the electrostatic capacitance quickly and accurately.

[0022]

FIG. 1 shows a block diagram of the principle of the present invention. The current change detection means 2 detects the current supplied to the electrostatic capacitance 1 at a detection interval according to the clock signal,
The amount of change in current at the detection interval is detected.

The clock control means 3 is a current change detection means 2
The synchronization of the clock signal supplied to the current change detecting means 2 is controlled in accordance with the amount of change in the current detected in.

The charging completion detecting means 4 is the current change detecting means 2
Change amount of current detected by the clock control means 3
The completion of charging is detected when the synchronization of the clock signals controlled by 2 does not change for a predetermined time.

[0025]

The change in current is detected by the current change detection means at a detection interval corresponding to the synchronization of the clock signals, and the clock control means controls the clock signal which determines the detection interval according to the change amount. Since the amount detection range can be changed, a large signal is not input even when the current changes rapidly, oscillation does not occur, and this can be detected accurately even if the amount of current change is minute. .

[0026]

FIG. 2 shows a block diagram of an embodiment of the present invention.

The charging current detector 16 of this embodiment comprises sample and hold circuits 20, 21, a subtractor 22, and comparators 23, 2.
4, 25, a reference voltage generation circuit 26, and a detection control circuit 27. A current detection signal is supplied from the current detection unit 13 to the sample hold circuits 20 and 21, and the current detection signals are held at different timings according to the clock signals CK ₁ and CK ₂ from the detection control circuit 27.

The current detection signal held in the sample hold circuits 20 and 21 is supplied to the subtractor 22. The subtractor 22 subtracts the current detection signal held in the sample hold circuit 21 from the current detection signal held in the sample hold circuit 20, and supplies the difference signal Va of both current detection signals to the comparators 23, 24, 25. To do.

The comparators 23, 24 and 25 are connected to the subtractor 22.
The difference signal Va thus supplied is generated by the reference voltage generator 26.
Reference voltage V₁, V₂, V₃(V₁<V₂<V₃)When
The detection control circuit 27 compares and detects a signal according to the magnitude result.
Supply to. The comparator 23 receives the difference signal V from the subtractor 22.
a is the minimum reference voltage V generated by the reference voltage generator 26
₁And the difference signal Va is compared with the reference voltage V₁Greater than
High level (Hi) when low, low level when low
The signal of (Lo) is output. Is the comparator 24 a subtractor 22?
Of the differential signal Va generated by the reference voltage generator 26
Reference voltage V between ₂And the difference signal Va is compared with the reference voltage V
₂Higher level (Hi) when larger, smaller than
A low level (Lo) signal is output to. Comparator 25
Represents the difference signal Va from the subtractor 22 as the reference voltage generator 26.
Maximum reference voltage V generated by₃And the difference signal V
a is the reference voltage V₃Higher level (H
i), outputs a low level (Lo) signal when small
To do.

Summarizing the above, the comparators 23, 24, 2
When the difference signal Va is smaller than the reference voltage V ₁ (Va <V ₁ ), the output of 5 is Lo, Lo, Lo, and when the difference signal Va is between the reference voltage V ₁ and the reference voltage V ₂ ( Hi, Lo, Lo when V ₁ <Va <V ₂ ) and Hi, Hi, Lo when the difference signal Va is between the reference voltage V ₂ and the reference voltage V ₃ (V ₂ <Va < ₃ ). , Differential signal V
When a is larger than the reference voltage V ₃ , it becomes Hi, Hi, Hi. Therefore, the difference signal level can be discriminated according to the output patterns of the comparators 23, 24, 25.

The outputs of the comparators 23, 24 and 25 are supplied to the detection control circuit 27.

FIG. 3 shows a block diagram of the detection control circuit 27.
The detection control circuit 27 is a ROM (read only memory)
28, counters 29, 30, 31, clock generator 3
2, 33 and flip-flops 34 and 35,
Clocks CK ₁ and CK ₂ that generate a charge completion signal and supply it to the controller 19 and control the timing of sample and hold by the sample and hold circuits 20 and 21.
Is generated and supplied to the sample hold circuits 20 and 21.

4 and 5 are explanatory diagrams of the operation of the detection control circuit 27. The outputs of the comparators 23, 24, 25 are supplied to the ROM 28 as addresses, and 5-bit digital data is output. At this time, the ROM 28 outputs the output patterns of the comparators 23, 24, 25 as Lo,
Decimal value "16", Hi, Lo, L when Lo, Lo
When it is o, it outputs a decimal value "8", when it is Hi, Hi, Lo, it outputs a decimal value "6", and when it is Hi, Hi, Hi, it outputs a decimal value "4".

The output data of the ROM 28 is supplied to the counter 30, and only the most significant 1 bit is supplied to the counter 29. The counter 30 is a down counter, and a clock signal CK ₁₂ as shown in FIG. 5B is supplied from the clock generator 33, and the ROM 2 is supplied in response to this clock signal.
Count down the data from 8 and count value "0"
The output signal CD rising at
A read clock signal CK ₁₃ (FIG. 5) output every 20 clocks of the clock signal CK ₁₂ as shown in FIG.
(E)), and the clear signal CL that is output one clock later than the clock signal CK ₁₃ as shown in FIG. 6D is output.

The output signal CD of the counter 30 is supplied to the set terminal for setting the output of the flip-flop 34,
The read clock CK ₁₃ of the counter 30 is a clock terminal for controlling the read of the ROM 28 and the counter 2
9 clock terminals. Further, the clear signal CL of the counter 30 is supplied to a reset terminal that resets the flip-flops 34 and 35.

The ROM 28 supplies data to the counter 30 when the clock CK ₁₃ goes high. The flip-flop 34 outputs the output signal C of the counter 30.
It is set at the rising edge of D and reset at the rising edge of the clear signal CL of the counter 30. The clock CK ₁₁ as shown from the clock generator 32 in FIG. 6 (A) is supplied to the set terminal to the flip-flop 35, the output is set at the rising edge of the clock CK _11, the counter 30 of the clear signal CL It is reset at the rising edge.

The clock CK ₁₁ is a clock that rises one clock later than the clear signal CL.

The counter 31 counts the clear signal CL of the counter 30, and when the count reaches 4, the output rises. The output of the counter 31 is supplied to the reset terminal of the counter 29. The counter 29 starts counting when the most significant 1 bit of the ROM 28 becomes a binary value “1” and counts the clock CK ₁₃ . The output of the counter 29 is the clock CK ₁₃ is 4 counts a high level instructs the charging completion, and when the output of the counter 31 is reset to a high level before the clock CK ₁₃ is 4 counts low It is set as a level and indicates that charging is not completed.

The S (set) input of the flip-flop 34 is set to high level. The flip-flop 34 sets the output to the high level when the S input becomes the high level.
The output of the flip-flop 34 is supplied to the sample hold circuit 20 as the clock CK ₁ .

According to the above configuration, the flip-flop 3
The output clock CK _{1 of} 5 is the clear signal C of the counter 30.
At the rising edge of L (FIG. 5D) (time t ₁ , t ₈ ),
Reset, clock CK of clock generator 32
₁₁ (FIG. 5 (A)) is set at the rising edge (time t ₂ , t ₉ ), and the clock generator 33 is set as shown in FIG. 5 (C).
A signal that rises every 20 counts of the clock CK ₁₃ (time t ₂ , t ₉ ) and is at high level for 18 counts (time t _{2 to} t ₈ ) is obtained.

The output clock CK ₂ of the flip-flop 34 is set at the rising edge of the output signal CD of the counter 30 (time t ₃ , t ₄ , t ₅ , t ₆ ) and the clear signal CL of the counter 30 (see FIG. D)) is reset at the rising edge (time t ₁ , t ₈ ). The output signal CD of the counter 30 counts down the data read from the ROM 28 at time t ₀ and rises when it becomes “0”. At this time, the output data value of the ROM 28 is determined according to the output pattern of the comparators 23, 24, 25, that is, the difference between the detected currents, and the larger the difference, the smaller the value.

If the output data value of the ROM 28 is large,
That is, until the count value of the counter 30 becomes “0”,
The time until the output signal CD rises becomes longer, and conversely, if it is smaller, it becomes "0", that is, the output signal CD
It takes less time to get up. Therefore, the output clock CK ₂ of the flip-flop 34 is the time t ₃ shown in FIG. 5F when the output data of the ROM 28 is “4”, and the time shown in FIG. 5G when the output data is “6”. t _4, the time t ₅ that shown in FIG. 5 (H) when the output data is "8", when the output data is "16" rises at time t ₆ shown in FIG. 5 (I), the counter 30 clear signal At the time t _{8 when} CL rises, a signal that falls is obtained.

Therefore, the times T ₁ , T ₂ , T ₃ , T ₄ from the rise of the output clock CK ₁ (FIG. 5C) of the flip-flop 35 to the rise of the output clock CK ₂ of the flip-flop 34 are: The larger the output data of the ROM 28, the larger (T ₁ <T ₂ <T ₃ <T
₄ ). The sampling and holding circuit 20 is sampled at the rising edge of the output clock CK ₁ of the flip-flop 35, and the sampling and holding circuit 21 is sampled at the rising edge of the output clock CK ₂ of the flip-flop 34. The time from the sampling of 20 to the sampling and holding circuit 21 performing sampling becomes long, and a minute change is detected by lengthening the interval of sampling T.

Further, the counter 29 outputs the counter 30 read clock CK ₁₃ to a decimal value output while the most significant bit of the output data of the ROM 28 is a binary value “1”, that is, when the difference between the detected currents is minimum. While "16" is being output, the charging completion signal is output after counting 4 clocks. This means that the state in which the difference between the detected currents is minimum continues, that is, the charge completion signal is output after the difference between the detected currents becomes sufficiently small.

As described above, the charging current detecting section 27 outputs the charging completion signal to the controller 19 after the change in the current flowing through the measuring object 11 becomes almost zero.

FIG. 6 shows a diagram for explaining the effect of the charging current detector 19. As shown in FIG. 6A, when the change in the detected current is rapid and the difference Va ₁ between the detected currents becomes large, the next sampling period T ₁₁ is reduced to reduce the next sampling period. The difference Va ₂ between the detected currents at T ₁₁ is not so large that the oscillation of the circuit is prevented by alleviating the abrupt change in the difference Va ₄ .

Further, as shown in FIG. 6B, when the change in the detected current is slow and the difference Va ₃ between the detected currents becomes small, the next sampling period T ₁₂ is increased to increase the next sampling period T _{12. 12} detection current difference Va ₄
Can be increased, and even if the difference Va decreases,
The difference can be detected, and thus even a minute difference can be detected.

[0048]

As described above, according to the present invention, the amount of change in the current can be accurately detected by controlling the detection interval for detecting the current according to the amount of change in the current. It has features such as accurate detection of charging completion.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a detection control circuit according to an embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of the detection control circuit according to the embodiment of the present invention.

FIG. 5 is an operation waveform diagram of the detection control circuit according to the embodiment of the present invention.

FIG. 6 is a diagram for explaining the effect of the detection control circuit of the embodiment of the present invention.

FIG. 7 is a block configuration diagram of a resistance measuring device.

FIG. 8 is an operation explanatory diagram of the resistance measuring device.

FIG. 9 is a configuration diagram of a conventional example.

FIG. 10 is a diagram illustrating an operation of a conventional example.

[Explanation of symbols]

 1 Capacitance 2 Current Change Detection Means 3 Clock Control Means 4 Charging Completion Detection Means 10 Measurement Target 11 Resistance Measuring Device 12 Switch 13 Current Detector 14 Power Supply 15 Voltage Detector 16 Charging Current Detector 17, 18 A / D Converter 19 Controller 20, 21 Sample and Hold Circuit 22 Subtractor 23, 24, 25 Comparator 26 Reference Voltage Generation Section 27 Detection Control Circuit

Claims (4)

[Claims] 1. A charging current detection circuit for detecting completion of charging of an electrostatic capacitance (1), detecting a current supplied to the electrostatic capacitance (1) at a detection interval according to a clock signal, and performing the detection. The current change detection means (2) for detecting the amount of change in the current at intervals, and the current change detection means (2) are supplied according to the amount of change in the current detected by the current change detection means (2). The clock control means (3) for controlling the cycle of the clock signal, and the amount of change in the current detected by the current change detection means (2) and the cycle of the clock signal controlled by the clock control means (3) are both predetermined. A charging current detection circuit comprising: a charging completion detecting means (4) for detecting completion of charging when it does not change with time. 2. The current change detecting means (2) includes a plurality of sample hold circuits (20, 21) for sampling and holding the current at detection intervals according to the clock signal, and a plurality of sample hold circuits (20, 21). 21. The charging current detection circuit according to claim 1, further comprising a subtraction circuit (22) for subtracting the current held in 21) to obtain a difference in current. 3. The clock control means (3) controls the clock signal so that the detection interval becomes shorter as the amount of change in the current detected by the current change detection means (2) becomes larger. The charging current detection circuit according to claim 1 or 2. 4. The charge completion detecting means (4) has a substantially zero amount of change in current detected by the current change detecting means (2), and the clock control means (3) maximizes the detection interval. The charging current detection circuit according to any one of claims 1 to 3, wherein completion of charging is detected when the state of controlling the clock signal continues for a predetermined time as described above.