JPS5966284A - Sampling pulse generating circuit - Google Patents

Abstract

PURPOSE:To obtain an optimum sampling pulse even if phase ditortion or jitter takes place by deciding the sampling phase of a character information signal based on plural sampling data, in a device receiving a character multiplex broadcast. CONSTITUTION:An output signal of a video detecting circuit 21 is converted, frequency-divided and 32 kinds of delay signals having different phase with each other are outputted at a delay circuit 32. A selecting circuit 33 selects either one delay signal as a sampling pulse according to the selecting signal, this signal and a signal giving a further delay to the former delay signal sample a signal to be sampled for plural number of times, and it is dicriminated whether the delay signal selected by the computer 26 is suitable for the sampling of the signal to be sampled. After the processing like this is performed for all the delay signals, the most suited delay signal is selected as the sampling pulse.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] □ The present invention is a method for sampling a text information signal that is transmitted by being interspersed with a television broadcast signal, for example, in an apparatus for receiving text broadcasting. -Relates to a Sansoling truss generation circuit suitable for generating an arm truss.

[Technical background of the invention]

A teletext broadcasting system is a system in which a signal indicating text information is superimposed on a television broadcast signal and transmitted, and the receiving side extracts this text information signal and displays the text information on the screen. be.

Figure 1 (K is TV Hi, ``J, N'' letters on the transmission number, and the number on the information tube: □ □: The character Takui Broadcasting Bond □
The character information signal is shown as a blank line for all pages, for example, at the 21st H of period TV (however, IHK1 police examination period). In addition, VD is Sancho 1Jvlfl1 issue,
HD is a horizontal synchronization signal. Text information signals are shown in Figure 1 (
As shown in b), the header part D1 and r-Yugao Ri.

It consists of The header is part of the clock run-in signal,
The number δR corresponds to the ++f information such as characters displayed in the - direction. Believe ← Various 1! illJ ill! I! No. Ka I
I is included. As shown in Figure 1 (cl), 101010101010
It is an 8 cycle 16 pit digital signal such as 1010, and the framing*-PFC is 1lloo1.
This is an 8-bit digital signal such as 01. In addition, in FIG. 11 (bl), CB is the color burst signal, and the clock run-in signal CR is a signal indicating the standard phase of the character clearing signal, and the framing code FC and data section D8. The signal is sent in synchronization with the clock line signal CR.However, in order to quickly pull the character information signal on the receiving and transmitting sides, the sent It is sufficient to create an A/loose synchronized with the coming clock run-in signal CR and use this as the sampling pulse.

FIG. 2 is a circuit diagram showing a conventional circuit for obtaining the above-mentioned Sunsoling's arm. In the figure, the frequency 13 fs 'c generated by the oscillation circuit 11 (however, fs
c is the carrier color signal frequency), the oscillation output signal is divided into minutes IAj,
In circuit 1.2, it is converted into a signal of solid-liquid<'Z 815 fsc. This signal is used as a synchronizing signal SP, and is synchronized with the clock run-in signal CR as follows. As shown in FIG. 3(a), the flip-flop circuit 13 is brought into a set state by a set signal SI outputted before the clock run-in signal CR. In addition, a signal obtained by inverting the character information signal by an inverter circuit 14 is supplied to the XM child (reset of the flip-flop circuit 13).

As a result, the flip-flop circuit 13 (Tb) in FIG.
The transition signal of the clock run-in signal CR shown in Fig. 3 (
It is reset by the first pulse of C). As a result, a signal as shown in FIG. 3 (di) is obtained at the Q output terminal of the flip-flop circuit 13, and is supplied to the divider circuit 12 as a reset signal. The sample, pulse, and SP (
(See FIG. 3(e)) is obtained. That's it.

[Problems with background technology]:.

However, the above configuration has the following problems. That is, the first one in the lock line-in signal CR
Since the sampling phase is determined by the number of pulses,
For example, this part is distorted due to the influence of noise signals, etc.
2. A sampling pulse 8P with an incorrect phase is obtained, causing a problem.

[Object of the Invention] The present invention has been made to address the above-mentioned circumstances, and is designed to always accurately match the sampled signal even if the sampled signal contains distortion or jitter. An object of the present invention is to provide a sampling pulse generating circuit that can obtain a sampling pulse whose phase is synchronized with the sampling pulse.

[Summary of the invention]

This invention delays nine signals having the same period as the sampling period of the sampled ring signal to generate a plurality of different delayed signals, and selects one delayed signal from among the plurality of nine delayed signals. Then, the sampled signal is sampled multiple times using this signal and a signal obtained by further delaying it, and the values of the corresponding bits of each sampled data are compared, and the bits that differ between the two are determined in advance. If the number is less than the number specified, it is determined that the selected delayed signal is suitable for bending the sampled signal recorded in RiJ. After performing such processing on all delayed signals, a sampling pulse is selected from among the delayed signals determined to be suitable for sampling. Select as. □ [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In figure M4, the signal output from the video detection circuit 2 is supplied to the slice and waveform shaping circuit 22, and the converted character information signal is output as a waveform K at the transistor logic T T L level. be done. This character information signal is supplied to the serial/parallel conversion circuit 23 and sampled using a separately supplied sampling pulse. In this case, the transmitted character information signal is serial data, and the serial/parallel conversion circuit 23 converts this serial data into 8-bit parallel data. This parallel □
Data is supplied to a buffer memory 26 via an r-) circuit 24. In this case, the date circuit 24 has a function of determining whether or not the Fleming code PC exists in the output data of the serial/parallel conversion circuit 23, and
Only when C exists, the output data of the serial/parallel conversion circuit 23 is taken into the pariah memory 25. The data written to the computer 25 is stored in the computer (hereinafter referred to as the CPU) 26. -) After being read out through the circuit 27, it is subjected to predetermined processing, received through the image output circuit 28, and supplied to the fuze, where it is displayed as an image. In addition, C:PU
The calculation contents of 26 are read-only memory (hereinafter referred to as I?OM).
) 29, is stored as Zologram data.

Next, a circuit configuration for generating sampling pulses, which is a feature of the present invention, will be explained.

The output signals of the image detection circuits 2...1 are supplied to the color subcarrier recovery circuit 30, and the output signals of the image detection circuits 2...1 are supplied to the color subcarrier recovery circuit 30, for example, at frequencies f, C (where, fsc, =8. 5
8MHg) signal. This signal is supplied to the frequency dividing circuit 31□ and converted into a signal with a frequency of 815 f@c. This signal is supplied to delay circuit 32. This delay circuit 32 delays the output signal of the frequency dividing circuit 31, thereby blocking 32 types of delayed signals having mutually different phases. In this case, the delay intervals of each delayed signal are equal, and the synchronization of a signal with a river wave number of 815 fsc is 175 n5ec, so the delay interval is set to -L--nsec, that is, approximately 5.5 n5ec2. . Thirty-two types of delayed signals having mutually different phases are supplied to a selection circuit 33. This selection □ selection circuit S
3 selects one of the 32 types of delayed signals as a sampling 241 pulse according to a separately supplied selection signal □, and supplies the selected signal to the serial/parallel conversion circuit 23.
, .

The selection circuit 33 determines which delayed signal is to be selected as the underling pulse in the following manner.

First, an arbitrary delay signal is selected as a sampling pulse in the selection circuit 33, and this sampling pulse is supplied to the first □ shift register 34 as a pulse. Also, this sampling, 4rus SP
is delayed by about 5.5 n@ec in the delay circuit 35 and then supplied to the second shift register 36 as a clock pulse. The character information signal output from the slice and waveform shaping circuit 22 is supplied to the D input of each shift register 35 and 36. Therefore, the text, text, and information signals are in the digits of 5.5 n, set (with a difference of 1) in each shift register s, t, and 3g.

8PB, and this sampled data is supplied to data bus B via I10 port 37. This data bus B includes the CPTJ26. Gate M, 29. ．． In addition to the video and output circuits 28, a work random access memory (hereinafter referred to as work I?AM) 3
8 will be inoculated. Shift register 34. , j,,Q
Each sipling data is stored in the ROM 29 program (
Therefore, cptr; p is compared, and based on the comparison result, it is determined by the selection circuit 33 whether or not the delayed signal selected is suitable for sampling or pulses.A determination result is obtained for one delayed signal. Then, the CPU 26 sends a selection signal for selecting the next delayed signal to I/9A! - is supplied to the selection 1 route 33 via the Thereafter, the sampling, discrimination, and selection of delayed signals are repeated in the same manner, and when this processing is completed for all the delayed signals, the CPU 26 discriminates □Based on the results, NDERINGNO! Optimal □Delay, signal □ for Lus's'P
A: Determination: Determined, the selection signal of this delayed signal is selected by circuit 3.
Supply to 3. In this way, the delay signal most suitable for selecting the character information signal from among the two types of delay signals is selected as the sampling pulse.

Here, the components and operations for determining the sampling A pulse SF will be explained with reference to the signal waveform diagrams of FIGS. 5 to 7 and the flowchart of FIG. 8. In the bad Stellar screen S□1 in Figure 8, the clock run-in signal OR'
The phase of the edge (rising or falling) is detected. This is done as follows:

The CPU 26 supplies the selection circuit 33 via the I10 port 39 with a selection signal for switching the delay signal selected by the selection circuit 3□3 every half period of the clock run-in signal CR. Therefore, at the clock pulse input end of the shift register 34, there is obtained a sample-live/flat-run SPA whose phase is shifted and shifted by 5.5 rttec every half period of the clock run-in signal CR. In addition, the clock/4 pulse input terminal of the shift register 36 has a sun, a de, .
Ringz 2 Luss SP person 5.5. A sampling nors SFB delayed by nnec is obtained. The clock and run-in signals qcR are sampled by these sampling pulses SPA and 8PBK, and the sampled and ring data are stored in shift registers 34 and 31; This sampling is performed for all 32 types of delayed signals. On the other hand, sampling data is supplied to data bus B via I10 port 37, and
The edge of the clock run-in signal 9R is detected at P and U26. Now 2. ．． Tenzo Ring Tsutsurusu SPA,
If 8FB exists near the edge of the clock run-in signal CR, the value (Do+Dt) of the corresponding bit of the sampling data of each shift register 34, 36 will be, for example, based on the phase relationship shown in FIG. 5(a). As is clear (0,
1). However, at the falling edge of the clock run-in signal CR, it becomes (1, 0). On the other hand, if the sampling pulses SPA and 8FB are not near the edge of the clock run-in signal CR, the sampling data ('D'o +
D's) becomes (t, 1)□. However, if the clock run-in signal qCR is Lorelepel, 1 becomes (0, 0). Like this: Sampling Tsugurus 8PA,
If 8FB exists near the edge of the clock run-in signal CR, the sampling data (Do, D,) of the corresponding bits will show different values, and if it does not exist near the edge, , becomes □ so that it shows the same value.The CPU 26 determines whether the value is (0, 1) or □ from among 32 sample □ dates □ ('DOr Dt) obtained according to the delay signals of 32 buildings. 1, 'Q) is detected, and a selection signal for selecting a delayed signal corresponding to the detected sampling data (Do, D,) is supplied to the selection circuit 33. Processing occurs at step 82.
□ When the sampling phase is set to the edge, substantial processing is performed to obtain the optimum sampling pulse for sampling the character information signal. That is, selected in step 82.

Sampling pulse SPA using delayed signal.

The SFB samples the character information signal output from the slice and waveform shaping circuit 22. The shift registers 34, 36 have, for example, 256 pits, and therefore, each shift register 34, 36 obtains 256 bits of sampling data for each delay signal. , C, PU2.6 is shift register 3.4 25
6 sampling days, evening and 2 of shift register 36
56. Compare the sampling data of the individual pinids with the corresponding pinid and examine the level relationship between both data. And this level relationship is (,,1,0) or (0,r)
If the number of bits with different value relationships is equal to or greater than a preset number n, the sampling phase is determined to be appropriate, and if there are fewer than n bits, the sampling phase is determined to be appropriate.

Once the sampling phase is determined to be appropriate, the phase data is stored in the work RAMJ&'. This 1 process is carried out in step S3', 8'4 in line 1. In this case, the sampling pulses 8PA and 8FB exist near the edge of the clock run-in signal CR as described above, so as is clear from FIG. 6(a)', the corresponding δ
The level relationship of the sub-pulling data between the two is usually (1, O') or (0°1). After this, CP
U26 supplies a selection signal for selecting the next delayed □ signal to the selection circuit 3'3. Sampling by the selected delay signal J? The suitability of the sampling and sampling phase of the character information signal is judged again by the pulse 8P and 8PB. This process is performed for all 32 delayed signals in accordance with steps 85 and 86. □ In this way, by sequentially shifting the phase of the delayed signal, the sampling pulse 8PA is obtained.

When 8PB is clocked and a delay signal that does not exist near the main register of signal C'R is selected, the signal shown in FIG.
As is clear from the corresponding Pit comrades' □S □Jibbling data □Noshi 4 relationship is almost the same ('1,''
1')'' or ("o"+o'), which have the same value relationship. Therefore: In such a case, it is judged that the above-mentioned fire extinguishment is appropriate, and the fire is extinguished.
1j'data' is stored in the work RAM 311.4. # is done. In this way, it is distributed to large work RAMJs □
] item data is not limited to just one □, but is usually multiple.

Therefore, in step 87, the CPU 26 detects phase data that exists in the middle in terms of phase from among the plurality of phase data, and selects the slow η signal corresponding to the detected phase data. Select circuit 33 selects the selection signal of
Supply to:. As a result, a sampling pulse having the optimum phase for sampling the character information signal is supplied to the series i-series conversion circuit 2S.CP
Uffi 6 is □ sample jig data from this Sansoling Tsurusu 14 Imported into buffer memory 25 □
Then, the data in the batza memory 25 is subjected to processing for image display as described above.

By the way, in order to judge whether the sampling phase is appropriate or not, the number of samples and jig data of corresponding pits and points whose level relationship is (i, o') or (0,, 1) is not just one, The reason why it is determined that the sampling phase is inappropriate only when there are n or more is as follows. That is, in the character information signal as shown in FIG. 7(a), 1. If phase flea occurs as shown in tb) in the same figure due to transmission distortion, deterioration of reception performance of the receiver, or superimposition of noise signals, the sampling phase of sampling pulse 8PA and SPB as shown in TC) l (d) in the same figure occurs. Even though c is correct, data such as (1°0) or (0', 1) is obtained in parts A and B shown in the figure.

Therefore, □In such a case, the level relationship is (1,
0) or (0', '1.), if the suitability of the sampling phase is judged based on one number, an erroneous judgment result will be obtained. Therefore, in the circuit shown in FIG. 4, it is determined that the sampling phase is inappropriate only when there are n or more samples in which the level relationship is (i, o) or (o, 1). This is also a behavior when a text information signal is stuck.
□ In Fig. 4, 40 is a display circuit, for example 32
It consists of 32 light emitting diodes LED corresponding to each type of delay signal. It is associated with the -LBD configuration. This display circuit 4.0 is configured so that each time the CPU 2.6 determines whether the sampling phase is suitable or not, the light emitting diode F corresponding to the delay signal at that time is displayed.
It is designed to be driven by a drive signal supplied from 26 to I10 port 4. In this case, for example, if the sampling phase is inappropriate, the light emitting diode r will not be lit, but if the sampling phase is appropriate, it will be lit.

This process is shown in the flowchart of FIG.
As described in detail above, in this embodiment, 32 delayed signals with different phases are prepared in advance, and □ 2
The sampling data of 56 character information signals (I) is stored, and the samples and lag phases of character information signals (I) are determined based on the plurality of samples (f9'7ff-y).

, , , , , and 7'c', , :, 1. of the conventional clock run, IN signals C and H. Even if phase distortion or jitter occurs in the character information signal, the 41st sampling position is determined. It is possible to obtain a sampling pulse with the optimum phase for sampling.

In particular, in this embodiment, not only the clock run-in signal CR but also the data portion (see tbt in FIG. 1) is sampled to determine the sampling phase. In this case, sampling 1. Since there is a large amount of data (256 bits) to determine the first digit, the data is flattened accordingly, and the effects of distortion and jitter appear on the character information signal. almost disappears. Since the quality of the sampling data is high in this way, the result of determining the sampling phase determined using this data also becomes highly reliable.

Further, in this embodiment, whether the sampling phase is suitable or not is displayed. Since it is equipped with a display circuit 40,
There is an advantage in that it is possible to judge the number of items stored in the buffer memory 25.

That is, the smaller the distortion and jitter of text, characters, and information signals (i,, 1), the more light-emitting diodes 9 are turned on in the display circuit 40.On the other hand, the larger the distortion - The thicker the diameter, the fewer light emitting diodes will be lit.In this way, the display circuit 400
The user can judge the quality of the text information signal by the size of the lighting box and area.If the lighting area is too small, the jitter and phase distortion of the text information signal will be very large. Therefore, it can be determined that there is a possibility that the quality of the data stored in the buffer memory 25 is poor.

Also, key! By making it possible to select an arbitrary delay signal depending on the operation, the user can, while looking at the display circuit 40,
A delay signal that turns on the light emitting diode can be selected by key operation. As a result, if the light-emitting diode continues to turn on or off, it is possible to forcibly skip some delay signals and select a delay signal that turns on the light-emitting diode by operating a key. Therefore, by doing this, the time required to determine the sampling phase can be shortened.
.

Note that the number of □ delayed signals/□ signals is not limited to 32, and may be, for example, 64. However, in this case, the number of signal lines between the I10 port 39 and the selection circuit SS is not five, but
It needs to be 6 pieces. Also, shift register 34.8
Of course, the number of bits of 6 is not limited to 256 bits.

[Effects of the Invention] As described above, the present invention provides a sampling circuit that can always obtain sampling pulses that are precisely phase-synchronized with the sampled signal even if phase distortion or jitter occurs in the sampled signal. It is possible to provide nine russ generated circadian cases.

[Brief explanation of drawings]

Figures 1 (a) to (e) are signal waveform diagrams for explaining the Mojitae Mikage system, and Figure 2 shows the generation of sampling pulses for sampling the character information signal included in the text multiplex rescue signal. A circuit diagram showing a conventional sampling pulse generation circuit, FIGS. 3(a) to (e) are timing charts for explaining the operation of the circuit in FIG. 2, and FIG. 4 is a sampling pulse generation circuit according to the present invention. Circuit diagram showing one embodiment of the circuit, Fig. 5 (a) 1 lb), Fig. 9 + al l
(b), FIGS. 7(a) to (d) are signal waveform diagrams for explaining the operation of the circuit shown in FIG. It is four-chard. 21.°° video detection circuit, 22.°. slice and waveform shaping circuit, 23.. serial-parallel conversion circuit, 24.27..
・r-to circuit, 25...buffer memory, 26...
CPU, 2B...Video output circuit, 29...ROM. 30... Color subcarrier regeneration circuit, 31... Needle internal circuit, 32. 34... Delay circuit, 33°゛° selection circuit, 3
4゜36...shift register, 37,39.41...
・I10 port, 38...Work RAM, 40...
Display □ Circuit.

Claims (1)

[Claims] a first delay means for delaying a signal having the same period as the sampling period of the sampled signal and generating a plurality of delayed signals each having a constant phase difference; and a plurality of delayed signals generated by the delay means. The first selectable by 1
a first sampling means for sampling the Moe sampled signal a plurality of times using the delayed signal being selected by the first selecting means; a second delay means for delaying the signal; a second sampling means for sampling the sampled signal several times using the delayed signal delayed by the second delay means;
．． The delay is selected by the first selection means only when the sampling data of the second sampling means is compared between corresponding bits, and the number of bits showing different values on the screen is less than the preset number. a determining means for determining that a signal is suitable for sampling the sampled signal; and sampling of the sampled signal from among delayed signals determined by the determining means to be suitable for sampling the sampled and ring signals. a second selection means for selecting a delay signal most suitable for the sampling pulse as a sampling pulse.