JPS5965788A - Timer counter - Google Patents

Abstract

PURPOSE:To simplify plural measuring operations having different resolution and measuring time range by wiring just the prescribed number of a bit to the output terminal group of a counter directly from the least significant digit or a prescribed upper digit in the form of plural groups to use the output of each group as a reference time signal having a different cycle. CONSTITUTION:A reference time signal generating circuit 10 generates a pulse train of the shortest cycle which is used when the measurement of the highest resolution is required. A counter 30 has a number of bits larger than those of a buffer register 41 and a 42. Therefore the position of each bit of the counter to be extracted is not limited to one, and signal lines a-d can be extracted. These signal lines are selected by selecting circuits 61 and 62 on the basis of the values stored in mode registers 21 and 22. The register 41 accepts and latches the count number of each time point by the indication of a signal 81, and a CPU50 measures the interval between two time points. It is possible to select optionally both range of the measurement and resolution according to a purpose since the signal line has the different reference time signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timer/counter that uses a reference time signal pulse train of a constant period and measures the number of pulses to perform a time counter.

The main structure of a timer/counter consists of a circuit that generates a reference time signal (a constant cycle reference signal pulse train) and a counter that performs one count operation in synchronization with changes in the signal. The resolution of measurement time is determined by the period of the reference time signal pulse train. If you use an n-bit counter, 2. ((
The time within the range of the pulse period HA) can be measured, and its resolution is the pulse period.

A general-purpose timer counter is required to have a wide range of measurement time ranges and resolutions. If we try to meet these requirements while considering integration as 81, we will have to provide the reference time signal pulse generation circuit of the Enoki number of gates and a number of counters on one chip. It is difficult to provide a large number of them due to the chip size.

In order to make the above situation clearer, an example of a conventional glue time counter will be explained with reference to FIG.

The period from the reference time signal generation circuit IO is (lμs
・2μS) and (4μ818μ,) sets of reference time signals are generated. Considering the current (lμat2μs) set of signals, the selection circuit 11 selects one of the signals according to the settings of the mode register 21, and the counter 31 sequentially counts this pulse train. The counter 31
In an 8-bit system, 8-bit output is output from an external terminal.

The counter Fi of the counter 31 continues counting, and the desired time measurement is performed as follows. That is, if the buffer register 41 receives the count number of the counter 31 at time 111, it is activated at the rising edge of the signal 81, latches the count number at time l111, and reads it out by the CPU 5Q.

Next, at time 1-2, the signal 81 is activated again at time T.

If the count number is latched and read by the CPL 15Q, the time interval can be easily calculated from the product of the difference between the two count numbers and the period of the selected reference time signal. Since there are four types of reference time signals, the time measurement range and resolution can be arbitrarily selected by selecting them.

Furthermore, by changing the reference time signal during time measurement! It is also possible to measure time corresponding to complex measured phenomena.

However, as the application becomes broader, the circuit becomes more complicated, such as preparing a large number of reference time signals or having multiple counters with different numbers of bits to change the measurement time range, making it difficult to use as a semiconductor integrated circuit. It becomes difficult to configure on a chip. In particular, installing multiple counters is a major obstacle to integration. Furthermore, when switching the reference time signal that drives the counter, for example, if the count data is driven from 0 to 196 with a reference time signal of lμS, and the reference time signal is set to 2μs at that point, the number of count data changes by 2μs. Just multiply by @
It is not possible to determine the time interval, and the count data up to the time of switching must be used for compensation. To do this, record the count data when switching the reference time signal.
A special circuit is required, and if the switching is complicated, it becomes difficult to deal with it due to the processing time and other factors.

The object of the present invention is to eliminate the above-mentioned drawbacks and -II! Provided is a timer counter that can perform a plurality of measurement operations with substantially different resolutions and measurement time ranges using a reference time signal and one binary counter driven by this reference time signal. It's about doing.

Each of the timer counters according to the present invention includes a single reference time signal generating circuit and a counter that measures pulses from the reference time signal generating circuit and weights each bit. lI from the least significant digit!
By wiring a number of bits less than the number of bits of the counter as a group from the concubine or from a predetermined high-order place, and by providing a plurality of these groups, the output of each group has a different cycle. It is characterized by being used as a plurality of reference time signals.

The present invention will be explained in detail below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. The reference time signal generation circuit 10 has the highest resolution.
A pulse train of the rootmost period used when +1J is required is generated and input to the counter 3o. The counter 30 continues to measure pulse failure as a binary count. The number of bits of this counter 3° is the buffer register 4
If 1s42 is 8 bits, select a larger number of bits. Therefore, the position of each bit of the counter from which 8 bits are taken out is not one. In the case of the solid line 1 tally shown in FIG. 2, for example, as shown in FIG.
It has 11 bit numbers from 0-1 to the least significant digits 30-11. As a result, when extracting the 8-bit key line, the lowest digits 30-1 to 30-8 and 9 are output (a
), Shift one bit to get 9 from 30-2 (b), Shift 2 bits below (C), Shift 3 bits (d), and each of these is an 8-bit signal. Take out the line a + b y cr d. These signal lines are respectively selected by certain 1 selection circuits 61+62 according to the values stored in the mode register 21w22. Assuming that the reference time signal generation circuit is lμs and the signal @a is selected, the signal 81 is generated at two times.
The buffer register 41 receives and latches the count number at each time according to the instructions of (,:i'LI
50, the time interval between two times can be measured. The measurement +niλ range is within 256 μs and has a resolution of 1/IS. Next, when the signal line is selected, it is output with a delay of 2 μs from bit 30-2, and
0-3 is delayed by 40 μs. Thereafter, each higher-order bit output is output after waiting for 2 .mu.s, so it is possible to perform the same measurement as if it were a 2 .mu.s reference time signal. At this time, measurement 1 [α circumference is 512 μS++ + Misaki is 2 μS
It is S. Since the reference time signal changes for the signal 1'5j c + d below, the measurement range and the W4 function can be arbitrarily selected depending on the purpose.

As explained in detail above, in the conventional method, a frequency dividing circuit is required to generate the base time signal from the base time signal, and the circuit is complicated. ! Since the 8-bit counter of iI has been changed to an 11-bit counter of 116j, not only the number of pins is reduced, but also additional circuits and the like are saved, making the circuit according to the present invention most suitable for integration. In addition, since there is only one standard reference time signal, even if signal lines a''-d are disconnected and connected in Fig. 2, the count data t of one counter itself is valid. is performed by tljlJn of the CPU 50, so even if the number of switching is quite large during the measurement time, C
There is an advantage that the time measurement calculation by the PU 50 is simple.

Switching of the reference time signal in Fig. 1 C, two words 1δ, 8i1
With the switching of 8. in the embodiment of the present invention shown in FIG. (Although it is complicated because it involves switching two signal lines, it is easily possible with well-known technology by using one 1ν1 (J8NET (insulated field effect transistor) group as shown in Figure 4. The increase in chip area due to this does not require much time.Although FIG. 4 shows one selection circuit m6.1, the other selection circuit 62 is exactly the same.

In this figure, each 8-bit signal of the signal +1 Jatb is switched by the output 21' of the mode register 21 and output as the output 61' of the selection circuit 61. The output 61'ld is manually input to the buffer 7 register 41.

Note that buffer registers 41*42 in FIG. 2 are counter 3.
Although this was explained as having the function of reading the data of 0, it also has the function of writing the data. When the two values match, the CPU sends a match signal as a signal to request all interrupt processing.
Even if one comparator is substituted with a comparator having the function of transmitting data to 50, the advantages of the present invention will not be lost at all.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a block diagram showing an example of monoleprosy according to the present invention, and Fig. 3 is a block diagram showing a monolithic example of the present invention. FIG. 4 is a diagram showing an example of implementing the selection circuit of FIG. 2. 10...Reference time signal generation circuit, 11, 121
61y62...Selection circuit, 21, 22...
...Mode register s 30.31 * 32...
...Counter, 41゜42...Buffer register, 50...et'u0 1st close yF) 3 circles 40th

Claims (1)

[Claims] In a timer/counter that measures the number of pulses from a reference time signal pulse train that generates a pulse train of a constant period and determines the time between the two times from the number of pulses within two times, each has a single reference time signal generation circuit and , a counter that measures pulses from the reference time signal generation circuit and weights each bit, and outputs the bits of the counter directly from the least significant digit or from a predetermined upper digit to the output terminal group of the counter. Each (
1. A timer/counter characterized in that its output is used as a plurality of reference time signals having different periods.