JPS596546A - Etching of insulating film - Google Patents
Etching of insulating filmInfo
- Publication number
- JPS596546A JPS596546A JP11576082A JP11576082A JPS596546A JP S596546 A JPS596546 A JP S596546A JP 11576082 A JP11576082 A JP 11576082A JP 11576082 A JP11576082 A JP 11576082A JP S596546 A JPS596546 A JP S596546A
- Authority
- JP
- Japan
- Prior art keywords
- silicon oxide
- oxide film
- film
- etching
- window
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 17
- 150000001875 compounds Chemical class 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 27
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 27
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 16
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 5
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 abstract description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 3
- 229910000077 silane Inorganic materials 0.000 abstract description 3
- 239000007788 liquid Substances 0.000 abstract 6
- 238000005979 thermal decomposition reaction Methods 0.000 abstract 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 9
- 239000000243 solution Substances 0.000 description 8
- 239000011259 mixed solution Substances 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はｎ型■−■族化合物半導体に選択拡散させるだ
めのマスクとなる絶縁膜のエツチング方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of etching an insulating film that serves as a mask for selective diffusion into an n-type ■-■ group compound semiconductor.
ｎ型ｍ −ｖ族化合物半導体上にｐ型頭域を形成する方
法としては液相エピタキシャル法と拡散法があり、現在
発光ダイオード、レーザー等に広く用いられている。後
者は前者と比較して量産性に富み、ｐｎ接合のプラナ化
が容易であるなどの優れた特長がある。Methods for forming a p-type head region on an n-type m-v group compound semiconductor include a liquid phase epitaxial method and a diffusion method, which are currently widely used in light emitting diodes, lasers, and the like. Compared to the former, the latter has excellent features such as being easier to mass-produce and making it easier to convert the pn junction into a planar one.
ｎ型ＩＩＩ −Ｖ族化合物半導体にｐ型拡散する場合ｐ
型不純物としては…族元素、例えばＺｎが用いられる。When p-type is diffused into an n-type III-V compound semiconductor, p
As the type impurity, a group element such as Zn is used.
酸化珪素膜はＺｎｉ通過させるためＺｎの選択拡散のだ
めのマスクとしては一般に窒化珪素膜やアルミナ膜がよ
く用いられている。Since a silicon oxide film allows Zni to pass through, a silicon nitride film or an alumina film is generally used as a mask for selective diffusion of Zn.
第１図はこの選択拡散のマスクの作製工程を示す。ｎ型
ＩＩＩ −Ｖ族化合物半導体１の上に、直接、窒化珪素
膜又はアルミナ膜２を形成し、更にその上に酸化珪素膜
３を形成する（第１図（ａ） ） ｏこの後、フォトレ
ジスト等を用いて酸化珪素膜３のパターンを形成する（
第１図（ｋ’） ） ｏこの酸化珪素膜３をマスクとし
て窒化珪素膜又はアルミナ膜２をエツチング除去し、拡
散用の窓４を形成する（第１図（Ｃ） ）ｏこの窓あけ
のエツチングではエソテング不足を避けるために過剰エ
ツチングするのが普通である。ところが窒化珪素膜やア
ルミナ膜のエツチング液として用いるリン酸液はＩＩＩ
−Ｖ族化合物をおかしてしまう。そのため過剰エツチ
ングすることができず、基板との界面でエツチング処理
を停止させて、窒化珪素膜又はアルミナ膜を完全に除去
することは非常に困難となりこのことが特性不良の大き
な要因となりている。FIG. 1 shows the manufacturing process of this selective diffusion mask. A silicon nitride film or alumina film 2 is formed directly on the n-type III-V group compound semiconductor 1, and a silicon oxide film 3 is further formed on it (FIG. 1(a)). A pattern of the silicon oxide film 3 is formed using a resist or the like (
Figure 1 (k')) o Using this silicon oxide film 3 as a mask, the silicon nitride film or alumina film 2 is etched away to form a window 4 for diffusion (Figure 1 (C)) In etching, it is common to over-etch to avoid insufficient etching. However, the phosphoric acid solution used as an etching solution for silicon nitride films and alumina films is
- It spoils group V compounds. Therefore, excessive etching cannot be performed, and it is extremely difficult to stop the etching process at the interface with the substrate and completely remove the silicon nitride film or alumina film, which is a major cause of poor characteristics.
本発明はこの問題点を解決するものであり、ｌ−Ｖ族化
合物半導体と窒化珪素膜又はアルミナ膜との間に酸化珪
素膜を介在させて形成しておくことにより、窒化珪素膜
又はアルミナ膜の窓あけエツチング液にｍ −ｖ族化合
物半導体表面がエツチング液におかされることを防ぎ、
かつ完全々選択拡散のだめのマスクを形成出来る絶縁膜
のエツチング方法を提供せんとするものである。The present invention solves this problem by forming a silicon oxide film interposed between the l-V compound semiconductor and the silicon nitride film or alumina film. Preventing the surface of the m-v group compound semiconductor from being exposed to the window etching solution,
It is also an object of the present invention to provide a method of etching an insulating film that can form a mask that allows complete selective diffusion.
以下１本発明の実施例を図面をもとに説明する。An embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明の絶縁膜のエツチング方法を示す工程断
面図である。まず、ｎ型［１−Ｖ族化合物半導体基板１
の表面にシラン（ＳｉＨ４）の熱分解法によって膜厚１
００ｏ人の酸化珪素膜５を形成する゛（第２図（ａ）
） Ｏ次に、シラン及びアンモニアガス系の熱分解決に
より膜厚１６００人の窒化珪素膜６を形成し、再び膜厚
６０００人の酸化珪素膜３を形成する。次に通常の写真
食刻法により弗酸。FIG. 2 is a process sectional view showing the insulating film etching method of the present invention. First, an n-type [1-V group compound semiconductor substrate 1
A film with a thickness of 1 is deposited on the surface of the
A silicon oxide film 5 of 0.000 mm is formed (Fig. 2(a)
) Next, a silicon nitride film 6 with a thickness of 1,600 thick is formed by thermal solution using silane and ammonia gas, and a silicon oxide film 3 with a thickness of 6,000 thick is formed again. Next, hydrofluoric acid was applied using the usual photoetching method.
弗化アンモニウム混合液で酸化珪素膜３を除去し窓７を
形成する（第２図（ｂ） ） Ｏそして、この酸化珪素
膜３をマスクにしてリン酸液で窓部７ｆ：通して窒化珪
素膜６の窓あけを行なう（第２図（Ｃ））。The silicon oxide film 3 is removed using an ammonium fluoride mixed solution to form a window 7 (FIG. 2(b)). Then, using this silicon oxide film 3 as a mask, a phosphoric acid solution is used to remove the silicon nitride through the window 7f. A window is opened in the membrane 6 (FIG. 2(C)).
このエツチング条件は１６０°Ｃ４６分程度で窒化珪素
膜６は完全に選択除去される。このようにすれば、過剰
エツチングの条件で処理してもリン酸液では酸化珪素膜
６のエツチング速度が遅いため窓部８では基板表面は酸
化珪素膜６で被膜されているため損傷はうけない。そし
て最後に酸化珪素膜６の選択除去、ならびに上層の酸化
珪素膜３の除去を弗酸、弗化アンモニウム混合液で同時
処理を行なう（第１図（ｄ） ） ｏ この混合液はＩ
ｌｌ −Ｖ族化合物と反応しないため過剰エツチングの
条件に設定しても窓部９の基板表面には損傷が発生しな
い〇尚、上記実施例においては、窒化珪素膜を用いた実
施例について述べたが、アルミナ膜の場合でも同様の効
果が期待できる。The etching conditions are 160° C. for about 46 minutes, and silicon nitride film 6 is completely selectively removed. In this way, even if the process is performed under excessive etching conditions, the etching speed of the silicon oxide film 6 is slow with the phosphoric acid solution, so the surface of the substrate is coated with the silicon oxide film 6 in the window portion 8, so no damage will occur. . Finally, selective removal of the silicon oxide film 6 and removal of the upper silicon oxide film 3 are simultaneously performed using a mixed solution of hydrofluoric acid and ammonium fluoride (FIG. 1(d)) o This mixed solution is
Since it does not react with II-V group compounds, no damage will occur to the substrate surface of the window portion 9 even if excessive etching conditions are set.In addition, in the above example, an example using a silicon nitride film was described. However, similar effects can be expected in the case of an alumina film.
以上のように１本発明はＩＩＩ −Ｖ族化合物基板表面
に酸化珪素膜の第１膜を形成し、次いで第２膜の窒化珪
素膜を形成する２重膜構造にすることにより、窒化珪素
膜のエツチング液の基板表面への損傷を第１膜の酸化珪
素膜で防止し、かつ基板表面に損傷を与えない液でこの
酸化珪素膜を除去することにより、選択拡散用のマスク
を形成するので、基板に何ら悪影響を辱えること塀ない
。As described above, the present invention has a double-layer structure in which a first silicon oxide film is formed on the surface of a III-V group compound substrate, and then a second silicon nitride film is formed, thereby forming a silicon nitride film. The silicon oxide film of the first film prevents the etching solution from damaging the substrate surface, and by removing this silicon oxide film with a solution that does not damage the substrate surface, a mask for selective diffusion is formed. , it will not cause any negative impact on the board.
第１図（ａ）〜（Ｃ）は従来の選択拡散マスクの形成法
を示す工程断面図、第２図（ａ）〜（ｄ）は本発明の絶
縁膜のエツチング方法の一実施例を示す工程断面図であ
る。
１・・・・・・ｎ型ＩＩＩ −Ｖ族化合物半導体基板、
３・・・・・・酸化珪素膜、６・・・・・・酸化珪素膜
、６・・・・・・窒化珪素膜、７，８・・・・・・窓部
、９・・・・・・拡散窓。
代理人の氏名 弁理士 中 尾 敏 男 はが１名−１
９〔
−セ ミ 。
＋−＋−，＋ｃ−３対
塚 城
−０θ −
１９７−FIGS. 1(a) to (C) are process cross-sectional views showing a conventional selective diffusion mask forming method, and FIGS. 2(a) to (d) show an embodiment of the insulating film etching method of the present invention. It is a process sectional view. 1... n-type III-V group compound semiconductor substrate,
3...Silicon oxide film, 6...Silicon oxide film, 6...Silicon nitride film, 7, 8...Window portion, 9... ...Diffusion window. Name of agent: Patent attorney Toshio Nakao Haga1 person-1
9 [-Semi. +-+-, +c-3 Tsuzuka Castle-0θ-197-
Claims (1)
２膜の絶縁膜をそれぞれ積ねて形成し、前記第２膜を所
定のエツチング液により、選択エツチング処理し、続い
て前記に不活性なエツチング液で前記第１膜を選択的に
除去することを特徴とする絶縁膜のエツチング方法。A first film and a second insulating film are stacked and formed on the surface of a III-V compound semiconductor substrate, and the second film is selectively etched using a predetermined etching solution, and then an inert etching solution is applied to the second film. A method of etching an insulating film, comprising selectively removing the first film using an etching solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11576082A JPS596546A (en) | 1982-07-02 | 1982-07-02 | Etching of insulating film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11576082A JPS596546A (en) | 1982-07-02 | 1982-07-02 | Etching of insulating film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS596546A true JPS596546A (en) | 1984-01-13 |
Family
ID=14670363
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11576082A Pending JPS596546A (en) | 1982-07-02 | 1982-07-02 | Etching of insulating film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596546A (en) |
-
1982
- 1982-07-02 JP JP11576082A patent/JPS596546A/en active Pending
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