JPS5963720A - Growing method for semiconductor single crystal - Google Patents

Growing method for semiconductor single crystal

Info

Publication number
JPS5963720A
JPS5963720A JP57173288A JP17328882A JPS5963720A JP S5963720 A JPS5963720 A JP S5963720A JP 57173288 A JP57173288 A JP 57173288A JP 17328882 A JP17328882 A JP 17328882A JP S5963720 A JPS5963720 A JP S5963720A
Authority
JP
Japan
Prior art keywords
grating
film
layer
single crystal
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57173288A
Other languages
Japanese (ja)
Inventor
Yoshiaki Sano
佐野　芳明
Toshio Nonaka
野中　敏夫
Nagayasu Yamagishi
山岸　長保
Toshimasa Ishida
俊正 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP57173288A priority Critical patent/JPS5963720A/en
Publication of JPS5963720A publication Critical patent/JPS5963720A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Optics & Photonics (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To enable to perform grating work having an ideal groove by forming a grating on a semicondutor substrate by a lift-off method. CONSTITUTION:After forming an Si oxide film 22 on the Si single crystal substrate 21, resists 23 are formed on the film 22 into a reverse pattern to the grating. Next, an oxide Si 24 is formed over the entire surface on the film 22 having the resists 23 into a fixed thickness, and the oxide Si 24 thereon is removed together with the resists 23. Thereby, only the oxide Si 24 formed directly on the film 22 remains on the film 22, and the gratings 25 are formed by this oxide Si film 24. Next, a poly Si layer 26 is formed over the entire surface of the film 22. Thereafter, the layer 26 single-crystallizes by applying heat treatment to the layer 26, and accordingly a single crystal Si layer 27 is obtained. This method makes the curvatures of the buttom and side surfaces of a grating grooves nearly 90 deg., thus enables to realize an infinitesimal curvature radius; therefore a good semiconductor crystal layer can be formed.

Description

【発明の詳細な説明】 この発明は半導体単結晶の成長方法に関するもので、具
体的には、半導体または絶縁体などの基板上に良好な半
導体単結晶層を形成するグラホエピタキシャル法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for growing semiconductor single crystals, and specifically relates to a graphoepitaxial method for forming a good semiconductor single crystal layer on a substrate such as a semiconductor or an insulator. .

従来のグラホエピタキシャル法を第１図を参照して説明
する。第１図において、１１はシリコン単結晶基板であ
シ、まずこの基板１１を熱酸化して表面にシリコン酸化
膜１２を形成する。次に、そのシリコン酸化膜１２上に
図示しないがホトリンによってレジストパターンを形成
した後、そのレジストパターンをマスクとしてシリコン
酸化膜１２のプラズマエツチングを行うことにより、そ
のシリコン酸化膜１２の表面部に第１図（５）に示すよ
うにグレーティング（微細パターン）１３を形成する。The conventional graphoepitaxial method will be explained with reference to FIG. In FIG. 1, reference numeral 11 denotes a silicon single crystal substrate. First, this substrate 11 is thermally oxidized to form a silicon oxide film 12 on its surface. Next, a resist pattern (not shown) is formed on the silicon oxide film 12 using photorin, and then plasma etching is performed on the silicon oxide film 12 using the resist pattern as a mask. A grating (fine pattern) 13 is formed as shown in FIG. 1 (5).

しかる後、マスクとして用いたレジストパターンを除去
する。第１図（８）はそのレジストパターンを除去した
後の装態を示している。次に、シリコン酸化膜１２上に
ＣＶＤ法によって第１図（Ｂ）に示すようにポリシリコ
ン層１４を形成する。しかる後、そのポリシリコン層１
４に対してレーザあるいはヒータによシ加熱処理を施す
。この加熱処理によシポリシリコン層１４は単結晶、化
し、第１図（Ｃ）に示すように単結晶シリコン層１５が
得られる。After that, the resist pattern used as a mask is removed. FIG. 1(8) shows the device after removing the resist pattern. Next, a polysilicon layer 14 is formed on the silicon oxide film 12 by the CVD method as shown in FIG. 1(B). After that, the polysilicon layer 1
4 is subjected to heat treatment using a laser or a heater. By this heat treatment, the polysilicon layer 14 is made into a single crystal, and a single crystal silicon layer 15 is obtained as shown in FIG. 1(C).

このようなグラホエピタキシャル法において、良好な単
結晶を得るためにはグし・−ティング形状が重要な要素
であシ、特にグレーティング溝において底面と側面の曲
率半径（第１図囚においてＲで示す）が５０Ｘ以下であ
ることが必要とされている。In such a graphoepitaxial method, the grating shape is an important element in order to obtain a good single crystal. ) is required to be 50X or less.

しかるに、上記従来のグラホエピタキシャル法では、エ
ツチング加工によりグレーティング１３を形成している
ため、グレーティング溝の底面と側面とにおける曲率半
径を５０Å以下にすることが非常に困難であシ、良好な
半導体単結晶層（単結晶シリコン層１５）が得られない
欠点があった。However, in the conventional graphoepitaxial method described above, since the grating 13 is formed by etching, it is very difficult to reduce the radius of curvature at the bottom and side surfaces of the grating groove to 50 Å or less, and it is difficult to make a good semiconductor layer. There was a drawback that a crystal layer (single crystal silicon layer 15) could not be obtained.

この発明は上記の点に鑑みなされたもので、理想的な一
溝を有するグレーティング加工を行うことができ、基板
上に良好な半導体単結晶層を形成す、ることかできる半
導体単結晶の成長方法を提供することを目的とする。This invention was made in view of the above points, and it is possible to process a grating having an ideal groove, and to grow a semiconductor single crystal that can form a good semiconductor single crystal layer on a substrate. The purpose is to provide a method.

以下この発明の実施例を第２図を参照して説明する。An embodiment of the present invention will be described below with reference to FIG.

第２図（５）において２１はシリコン単結晶基板であり
、まずこの基板２１の表面に熱酸化によってシリコン酸
化膜２２を形成した後、そのシリコン酸化膜２２上にホ
トリソによってレジスト２３を、グレーティングと逆パ
ターンに形成する。In FIG. 2 (5), 21 is a silicon single crystal substrate. First, a silicon oxide film 22 is formed on the surface of this substrate 21 by thermal oxidation, and then a resist 23 is formed on the silicon oxide film 22 by photolithography to form a grating. Form into a reverse pattern.

次に、レジスト２３を有するシリコン酸化膜２２上の全
面に、イオンビームスパッタリングによって第２図（Ｂ
）に示すように酸化シリコン２４を所定厚さに形成する
。Next, the entire surface of the silicon oxide film 22 having the resist 23 is subjected to ion beam sputtering as shown in FIG.
), silicon oxide 24 is formed to a predetermined thickness.

しかる後、レジスト２３を除去して、同時にその上の酸
化シリコン２４を除去（リフトオフ）する。これにより
、シリコン酸化膜２２上には、そのシリコン版化膜２２
上に直接形成された酸化シリコン２４のみが第２図（Ｑ
に示すように残る。この残存ば化シリコン２４によりグ
レーティング２５が形成される。Thereafter, the resist 23 is removed and at the same time the silicon oxide 24 thereon is removed (lifted off). As a result, the silicon version film 22 is formed on the silicon oxide film 22.
Only the silicon oxide 24 formed directly on top is shown in FIG.
remains as shown. A grating 25 is formed by this remaining silicon nitride 24.

続いて、そのグレーティング２５を有するシリコン酸化
）艇２２上の全面に、ＣＶＤ法によって第２図０に示す
ようにポリシリコン層（半導体層）２６を形成する。Subsequently, as shown in FIG. 2, a polysilicon layer (semiconductor layer) 26 is formed on the entire surface of the silicon oxide layer 22 having the grating 25 by the CVD method.

しかる後、そのポリシリコン層２６に対してレーザ、ヒ
ータあるいはフラッシュランプによシ加熱処理を施す。Thereafter, the polysilicon layer 26 is subjected to heat treatment using a laser, a heater, or a flash lamp.

この加熱処理によシボリシリコン層２６は単結晶化し、
第２図（５））に示すように単結晶シリコン層２７が得
られる。Through this heat treatment, the shibori silicon layer 26 becomes single crystal,
A single crystal silicon layer 27 is obtained as shown in FIG. 2(5)).

以上説明したように実施例では、リフトオフ法によりグ
レーティング２５を形成する３、シたがって、ダ、レー
ティング溝の底面と側面の曲率はほぼ９σとなり、−無
限小の抽率半径を実現することができる３、そのため、
理想的な身うホエピタキシャ「・、を行うことができ、
良好な半導体単結晶層（単、番台１晶シリコン層２７）
を形成することがで、きる。As explained above, in the embodiment, the grating 25 is formed by the lift-off method. Therefore, the curvature of the bottom and side surfaces of the rating groove is approximately 9σ, and it is possible to realize an infinitesimal drawing radius. 3. Therefore,
Ideal body epitaxis can be carried out,
Good semiconductor single crystal layer (single, single crystal silicon layer 27)
It is possible to form a .

なお、実施例は；シリコン単結晶基板とシリコン酸化膜
からなる絶縁体基板上に、グレーティン、　　　グを形
成する場合であるが、同様にして半導体基板あるいは金
属基板上にグレーティングを形成することができる。ま
た、実施例は、酸化シリコンをグレーティング形成材料
として用いる場合であるが、導電性シリコンや高融点金
属でグレーティングを形成してもよい。絶縁体基板上に
導電性シリコンや高融点金属でグレーティングを形成し
た場合は、そのグレーティングを配線などに用いること
ができる。Although the example is a case in which a grating is formed on an insulating substrate consisting of a silicon single crystal substrate and a silicon oxide film, it is also possible to form a grating on a semiconductor substrate or a metal substrate in the same way. can. Further, although the embodiment uses silicon oxide as the grating forming material, the grating may be formed of conductive silicon or a high melting point metal. When a grating is formed using conductive silicon or a high-melting point metal on an insulating substrate, the grating can be used for wiring, etc.

以上詳述したようにこ′の発明の半導体単結晶の成長方
法によれば、リフトオフ法を用いているので理想的な溝
を有するグレーティング加工を行うことができ、基板上
に良好な半導体単結晶を形成することができる。As detailed above, according to the semiconductor single crystal growth method of the present invention, since the lift-off method is used, a grating having ideal grooves can be processed, and a good semiconductor single crystal can be grown on the substrate. can be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のグラホエピタキシャル法を示す図、第２
図はこの発明の半導体単結晶の成長方法の実施例を示す
図である。 ２１・・・シリコン単結晶基板、２２・・・シリコン酸
化膜、２　吐・・レジスト、２４・・・酸化シリコン、
ｉ５・・・グレーティング、２６・・・ポリシリコン層
、１ｔニア・・・単結晶シリコン層。 特許出願人　　工業技術院長 第１図 １３ 第２図 ３Figure 1 shows the conventional graphoepitaxial method, Figure 2
The figure shows an example of the method for growing a semiconductor single crystal according to the present invention. 21... Silicon single crystal substrate, 22... Silicon oxide film, 2 Discharge... Resist, 24... Silicon oxide,
i5...Grating, 26...Polysilicon layer, 1tNia...Single crystal silicon layer. Patent applicant Director of the Agency of Industrial Science and Technology Figure 1 13 Figure 2 3

Claims (1)

【特許請求の範囲】[Claims] 基板上にレジストをグレーティングと逆パターンに形成
する工程と、前記レジストを有する基板上の全面にグレ
ーティング形成月相を所定厚さに形成する工程と、前記
レジストを除去して同時にその」二のグレーティング形
成材料を除去することにより、基板上に直接形成されて
残存するグレー・讐イング形成材料によシダレーティン
グを形成す丁”る工程と、そのグレーティングを有する
基板上の全面に半導体層を形成する工程と、その半導体
層に加熱処理を加えることによシ、前記グレーティング
を利用して前記半導体層を単結晶化させる工程とを具備
してなる半導体単結晶の成長方法。A step of forming a resist on a substrate in a pattern opposite to that of the grating, a step of forming a grating-forming moon phase to a predetermined thickness on the entire surface of the substrate having the resist, and removing the resist and simultaneously forming the second grating. By removing the forming material, a process of forming a fern grating using the remaining gray-scale forming material that is directly formed on the substrate, and forming a semiconductor layer on the entire surface of the substrate having the grating. A method for growing a semiconductor single crystal, comprising the steps of: applying a heat treatment to the semiconductor layer to single-crystallize the semiconductor layer using the grating.
JP57173288A 1982-10-04 1982-10-04 Growing method for semiconductor single crystal Pending JPS5963720A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57173288A JPS5963720A (en) 1982-10-04 1982-10-04 Growing method for semiconductor single crystal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57173288A JPS5963720A (en) 1982-10-04 1982-10-04 Growing method for semiconductor single crystal

Publications (1)

Publication Number Publication Date
JPS5963720A true JPS5963720A (en) 1984-04-11

Family

ID=15957666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57173288A Pending JPS5963720A (en) 1982-10-04 1982-10-04 Growing method for semiconductor single crystal

Country Status (1)

Country Link
JP (1) JPS5963720A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62237718A (en) * 1986-04-08 1987-10-17 Oki Electric Ind Co Ltd Substrate for forming single crystal thin film
JPS62238617A (en) * 1986-04-09 1987-10-19 Oki Electric Ind Co Ltd Formation of substrate for forming single crystal thin film
JPH01128421A (en) * 1987-11-13 1989-05-22 Agency Of Ind Science & Technol Glass substrate for semiconductor element and manufacture thereof
JP2001345267A (en) * 2000-03-27 2001-12-14 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62237718A (en) * 1986-04-08 1987-10-17 Oki Electric Ind Co Ltd Substrate for forming single crystal thin film
JPS62238617A (en) * 1986-04-09 1987-10-19 Oki Electric Ind Co Ltd Formation of substrate for forming single crystal thin film
JPH01128421A (en) * 1987-11-13 1989-05-22 Agency Of Ind Science & Technol Glass substrate for semiconductor element and manufacture thereof
JP2001345267A (en) * 2000-03-27 2001-12-14 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device

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