JPS5961125A - Method for liquid-phase epitaxial growth - Google Patents

Method for liquid-phase epitaxial growth

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Publication number
JPS5961125A
JPS5961125A JP57171223A JP17122382A JPS5961125A JP S5961125 A JPS5961125 A JP S5961125A JP 57171223 A JP57171223 A JP 57171223A JP 17122382 A JP17122382 A JP 17122382A JP S5961125 A JPS5961125 A JP S5961125A
Authority
JP
Japan
Prior art keywords
layer
inp
growth
temperature
ingaas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57171223A
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Japanese (ja)
Inventor
Susumu Yamazaki
進 山崎
Jiro Okazaki
岡崎　二郎
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Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57171223A priority Critical patent/JPS5961125A/en
Publication of JPS5961125A publication Critical patent/JPS5961125A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02392—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02461—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02625—Liquid deposition using melted materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02628—Liquid deposition using solutions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Semiconductor Lasers (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Led Devices (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To grow an InP layer without generation of a meltback as well as to form an excellent hetero-junction interface between said InP layer and an InGaAs layer by a method wherein the InGaAs layer is grown on an InP substrate at the specific growth termination temperature, and the InP layer grown at the specific cooling speed in such a manner that it comes in contact with the InGaAs layer. CONSTITUTION:The InP substrate 1, having the raw material of solution of the prescribed composition ratio and the surface 111A as a main surface, is placed in a sliding boat, and it is maintained at an approximate temperature of 630 deg.C for approximtely one hour. Subsequenty, using the temperature program having a growth termination temperature of 580 deg.C or below, the meltback of the InP substrate 1 and the growth of the first InP layer 2, an InGaAs layer 3 and the second InP layer 4 are performed successively while said InP substrate 1 is being cooled when the fixed cooling speed alpha is 2 deg.C/min or above, namely. alpha=2.5 deg.C/min for example. The lattice dismatching of DELTAa/a with the InGaAs layer 3, the InGaAs layers 2 and 3 in room temperature of the semiconductor substrate formed through the above procedures is brought to -0.03%, for example, which is within the tolerance limit.

Description

【発明の詳細な説明】 ＋ａ＋　　発明の技術分野 本発明は液相エピタキシャル成長方法、特にＩｒｌ　（
Ｊ　ａΔｓ　ｌｆｆ１に接して１ｎＰＷ４を形成する液
相エピタキンヤル成長方法に関する。DETAILED DESCRIPTION OF THE INVENTION +a+ Technical Field of the Invention The present invention relates to a liquid phase epitaxial growth method, particularly Irl (
The present invention relates to a liquid phase epitaxial growth method for forming 1nPW4 in contact with J aΔs lff1.

ｔｂ＋　　技術の背景 長波長光通信用の発光素子および受光素子の材料として
ｍ−ｖ族化合物半導体が研究開発されている。と（に、
Ｉｎ７−ｘＧａｚＡｓ中でＩｎＰ基板結晶上に格子整合
させることのできるＩ　ｎ　Ｏ，５３Ｇ　ａ　０．４７
Ａ　ｓはエネルギーギャップが０．７４　ｅ　Ｖであり
発光波長１．６８μｍが得られるので、レーザや発光ダ
イオード（ＬＥＤ）の発光素子あるいはホトダイオード
（ＰＤ）やアバランシュホトダイオード（ＡＰＤ）の受
光素子の材料として有望である。このＩ　ｎ　Ｏ，５３
Ｇ　ａ　Ｏ，４７ΔＳを発光素子に用いる場合には、こ
のＩｎＧａＡｓを活性層として、キャリヤーの閉じ込め
効果を最も大きくすることのできるＩｎＧａＡｓＰ四元
結晶中でも最もエネルギーギャップの大きなＩｎＰクラ
ッド層が活性層をはさんだダブルへテロ（Ｄ　Ｈ）構造
とすることが望ましい。また、受光素子に用いる場合ニ
ハ、このＩｎＧａＡｓを光吸収層とし、その上にＩｎＰ
層をウィンド層兼増倍層として形成することが望ましい
。このように光半導体素子の活性層等にｌ　ｎ　Ｇ　ａ
ＡＳ層を用いる場合には１通雷このＩ　ｎＧａＡ３層に
接してＩｎＰ層が形成されている。Background of the tb+ Technology M-V compound semiconductors are being researched and developed as materials for light emitting elements and light receiving elements for long wavelength optical communications. and(ni,
I n O,53G a 0.47 that can be lattice matched on InP substrate crystal in In7-xGazAs
Since A s has an energy gap of 0.74 eV and an emission wavelength of 1.68 μm, it can be used as a material for light emitting elements of lasers and light emitting diodes (LEDs), or light receiving elements of photodiodes (PDs) and avalanche photodiodes (APDs). It's promising. This I n O, 53
When using GaO, 47ΔS in a light emitting device, this InGaAs is used as the active layer, and an InP cladding layer, which has the largest energy gap among the InGaAsP quaternary crystals and can maximize the carrier confinement effect, separates the active layer. It is desirable to have a sandwich double hetero (DH) structure. In addition, when used in a light-receiving element, this InGaAs is used as a light absorption layer, and InP
Preferably, the layer is formed as a wind layer and multiplication layer. In this way, L n Ga is applied to the active layer of an optical semiconductor device.
When an AS layer is used, an InP layer is formed in contact with the three InGaA layers.

（Ｃ）（メを来技術と問題点 先に述べたＩ　ｎ　Ｐ　／　Ｉ　ｎ　０．５３Ｇ　ａ　
Ｏ，４７Δｓ　／　１ｎＰなるＩ）ＩＩ槽構造液相エピ
タキシャル成長方法によって形成することを試めるなら
ば、最終のＩｎＰ層成長溶液中に先に成長させたＩｎＧ
ａＡｓ層が溶りこむ（ノル１−ハックと称する）ために
。(C) (I n P / I n 0.53G a
O,47Δs/1nP I) If you try to form the II tank structure by the liquid phase epitaxial growth method, the previously grown InG will be added to the final InP layer growth solution.
In order for the aAs layer to dissolve (referred to as nor-1-hack).

ＩｎＧａＡｓ層に接してＩｎＰ層を液相エピタキシャル
成長させることは従来不可能とされＣいた。It was conventionally considered impossible to liquid-phase epitaxially grow an InP layer in contact with an InGaAs layer.

この問題を解決することを目的として１本特許出願人は
先に特願昭５−７−（１５０１０３号によって一つの発
明を提供した。該発明においては、ＩｎＰＪｉＮを成長
させるＩｎＧａＡｓ１ｉｉ面を（１１，１）Ａ面とし、
ＩｎＰ／８液の成長開始温度を５８０（”Ｃ）以下とし
、かつ過冷却度を１０Ｇ℃）Ｂ上とすることによって、
ＩｎＧａＡｓ層？に接するＩｎＰＩｆＷの液相エピタキ
シャル成長を可能にしている。In order to solve this problem, the applicant of the present patent previously provided an invention in Japanese Patent Application No. 150103. In this invention, an InGaAs1ii surface on which InPJiN is grown is 1) Side A,
By setting the growth start temperature of the InP/8 liquid to 580 ("C) or lower, and setting the degree of supercooling to 10G C) or higher,
InGaAs layer? This enables liquid-phase epitaxial growth of InPIfW in contact with the substrate.

すなわち該発明は、　　（１）（１１１）Ａ面のＩｎＧ
ａＡｓ層の上にＩｎＰ溶液を載せたときにメルトハック
が非常に起りにくいこと、および（２）メルトバンクは
ＩｎＰのエピタキシャル成長開始温度およびＩｎＰの過
冷却度に非常に敏感であるが、５８０（’Ｃ）以下の成
長開始温度で１０　〔℃〕以上の過冷却度であればメル
トハックをなしにＩｎＰ層が成長することを見出したこ
とに基づいている。That is, the invention includes (1) (111) InG on the A side;
(2) the melt bank is very sensitive to the InP epitaxial growth initiation temperature and the degree of supercooling of InP; This is based on the discovery that an InP layer can grow without melt hacking if the degree of supercooling is 10° C. or more at a growth start temperature of 10° C. or less.

しかしながら該発明を実施するにあたって、ＩｎＧａＡ
ｓ層の液相エピタキシャル成長開始を品度が最終のＩｎ
Ｐ層の成長開始温度より大幅に高いならば、”’ＩｎＧ
ａＡｓ層成長終了１Ａ　Ｉ　ｎ　ｐ層成長開始までの間
に例えば１０分間を越える待ち時間が介在することとな
り、その間６００（’Ｃ）前後の高温においてＩｎＧａ
ＡＳ層表面が雰囲気ガス例えば水素（１４２）に晒され
るために２表面近傍に結晶欠陥を生ずるなどの劣化を招
いてＩｎＰ層成層成長窓図する特性のＤ　Ｈ構造が得ら
れず例えばＰＤ、ＡＰＤなどの受光素子を作製した場合
暗電流が増大するなどの問題がある。However, in implementing the invention, InGaA
The liquid phase epitaxial growth of the s-layer is started when the quality is final.
If it is significantly higher than the growth start temperature of the P layer, "'InG
There is a waiting time of, for example, more than 10 minutes before the aAs layer growth starts.
Since the surface of the AS layer is exposed to an atmospheric gas such as hydrogen (142), it causes deterioration such as the formation of crystal defects near the 2nd surface, making it impossible to obtain a DH structure with characteristics similar to those in the InP layer growth window. There are problems such as an increase in dark current when a light receiving element such as the above is fabricated.

（ｄｌ　　発明の目的 本発明は、ＩｎＰ／ＩｎＯ，５３ＧａＯ，４７Ａｓ／１
ｎ　ＰのＤＨ構造を液相エピタキシャル成長力法で形成
するに際し、ＩｎＧａＡｓ１ｉｉに接してＩｎＰ層をメ
ルトハックを生ずることなく成長さ・ｕ、かつＩｎＧａ
Ａｓ層とＩｎＰ層との間に良好なヘテロ接合界面を形成
する方法を提供することを目的とする。(dl Purpose of the Invention The present invention is directed to InP/InO, 53GaO, 47As/1
When forming an nP DH structure using the liquid phase epitaxial growth method, an InP layer can be grown in contact with InGaAs1ii without causing melt hacking.
It is an object of the present invention to provide a method for forming a good heterojunction interface between an As layer and an InP layer.

（ｅｌ　　発明の構成 本発明の前記目的は、（１１１）Ａ面を主面とするイン
ジウム・燐（ＩｒｉＰ）基板上にインジウム・ガリウム
・砒素（ＩｎＧａＡｓ）層を成長終了温度を５８０（’
ｃ）以下として成長させ、続けてインジウム・燐（Ｉｎ
Ｐ）層を前記インジウム・ガリウム・砒素（ＩｎＧａＡ
ｓ）層に接して。(el) Structure of the Invention The object of the present invention is to grow an indium gallium arsenic (InGaAs) layer on an indium phosphorous (IriP) substrate having a (111)A plane as its main surface at a growth finishing temperature of 580 ('
c) grown as below, followed by indium phosphorous (In
P) layer is made of the indium-gallium-arsenic (InGaA) layer.
s) in contact with the layer.

前記特願昭５７−０５０１０３号の方法によって成長さ
せることにより達成される。This can be achieved by growing according to the method described in Japanese Patent Application No. 57-050103.

更に特に本発明を受光素子等に用いられるＩｎＰ　／　
Ｉ　ｎ　Ｇ　ａΔｓ　／　Ｉ　ｎ　ＰのＤＨ構造の成長
に実施するに際しては、冷却速度を２（’Ｃ／ｍ１ｎ）
以上に選択することにより１例えば厚さ２　〔μｍ〕程
度以上の［ｎＧａＡ３層を含む前記Ｄ１１構造を。More particularly, the present invention can be applied to InP/
When growing the DH structure of I n GaΔs / I n P, the cooling rate was set to 2 ('C/m1n).
By making the above selection, the D11 structure including three nGaA layers having a thickness of, for example, about 2 [μm] or more can be obtained.

一定した冷却速度で連続的に成長さ−Ｕることが極めて
容易となる。It is extremely easy to grow continuously at a constant cooling rate.

（ｆｌ　　発明の実施例 以下本発明を実施例により図面を参照して具体的に説明
する。(fl Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings.

第１図は本発明の液相エピタキシャル成長方法によって
形成された半導体基体の断面図であり。FIG. 1 is a cross-sectional view of a semiconductor substrate formed by the liquid phase epitaxial growth method of the present invention.

１は（１１１）　Ａ面を主面とするＩｎＰ基板、２は第
１の１　ｎ　Ｐ、Ｆｆ、　　３はＩ　ｎ　Ｏ，５３Ｇ　
ａ　Ｏ，４７Ａ　ｓ　Ｎ。1 is an InP substrate with (111) A plane as the main surface, 2 is the first 1 n P, Ff, 3 is In O, 53G
a O, 47 A s N.

４は第２のＩｎＰ層を示す。また、第２図は本実施例の
温度プログラムを示し、１′はＩｎＰ基板１の表面層の
メルトハソク工程、２乃至４ば第１図に同一符号で示し
た層の成長工程である。4 indicates the second InP layer. Further, FIG. 2 shows the temperature program of this embodiment, in which 1' is the melting process for the surface layer of the InP substrate 1, and 2 to 4 are the growth steps for the layers indicated by the same reference numerals in FIG.

本実施例においては、　ｌ＆に示す組成比の溶液原料及
びＩｎＰ基板１をスライドボートに収容し。In this example, a solution raw material having a composition ratio shown in l& and an InP substrate 1 were placed in a slide boat.

温度約６３０（’Ｃ）に約１時間保持した後に第２図に
示す温度プログラムによって、一定の冷却速度α−２，
５（’Ｃ／　ｍｉｎ　）で冷却する間に、ｌｎＰ基板Ｉ
のメルトバック並びに第１のＩｎ２層２゜Ｉ　ｎ　Ｇ　
ａΔ５Ｗｉ３及び第２のＩｎＰＩｉｉ４の成長を順次連
続して実施している。ただし各工程の詳細は下記の通り
である。After maintaining the temperature at about 630 ('C) for about 1 hour, a constant cooling rate α-2,
During cooling at 5 ('C/min), the lnP substrate I
meltback and first In2 layer 2゜I n G
The growth of aΔ5Wi3 and the second InPIii4 is performed successively. However, the details of each step are as follows.

ＩｎＰ基ｉ反Ｉのメルトバック メルトハソクン容ン夜　　：Ｉｎ メルトバック開始温度：　５９　Ｂ、５　（°Ｃ）メル
トバック終了塩度：５９８　　じＣ〕第１のＴｎＰ屓２
の成長 成長／８液の組成比： ＋ｎ：　　１ｎＰ＝１　　　（ｇ）　　　：５．５　　
　（＋ｎｇ）成長溶液の飽和温度：６１０（’Ｃ） 成長開始７Ｍ！ｒ度：５９８［’Ｃ） 過冷却度＝１２〔“Ｃ〕 成し終了温度：５８５（”Ｃ） 成長層の厚さ：約３Ｃμｍ〕 ＩｎＧａＡｓＪＷ３の成長 成長溶液の組成比： Ｉｎ　：　ＩｎＡｓ　：ＧａＡｓ層１　（ｇ）：２２．
０６９　Ｃ■）　　：　２６．２４４　Ｃ■〕成長溶液
の飽和塩度：５Ｂ８（’Ｃ） 成長開始温度：５８５（’Ｃ） 過冷却度１（’ｃ） 成長終了温度：５８０（”Ｃ） 成長層の厚さ：約２　〔μｍ〕 第２のＩｎＰｌｉｉ４の成長 成長溶液の組成比： Ｉｎ：　１ｎＰ＝１　　（ｇ）：４．８　（ｗ）成長溶
液の飽和温度：６０２（’Ｃ） 成長開始温度：５８０（”Ｃ） 過冷却度＝２２〔°Ｃ〕 成長終了温度：５７９（”Ｃ） 成長層の厚さ：約１　〔μｍ〕 以上説明した方法によって形成された本実施例の半導体
基体において、ＩｎＧａＡｓ１ｉｔ３とＩｎ２層２及び
４との室温における格子不整合△ａ／ａは−０，０３Ｇ
％〕であって許容範囲内にあった。Meltback temperature of InP group I: In Meltback start temperature: 59 B, 5 (°C) Meltback end salinity: 598 °C] First TnP layer 2
Growth/composition ratio of 8 liquids: +n: 1nP=1 (g): 5.5
(+ng) Saturation temperature of growth solution: 610 ('C) Start of growth 7M! Degree of r: 598 ['C] Degree of supercooling = 12 ["C] Completion temperature: 585 ("C) Thickness of growth layer: approximately 3Cμm] Growth of InGaAsJW3 Composition ratio of growth solution: In: InAs:GaAs Layer 1 (g): 22.
069 C■): 26.244 C■] Saturated salinity of growth solution: 5B8 ('C) Growth start temperature: 585 ('C) Supercooling degree 1 ('C) Growth end temperature: 580 (''C) Growth Layer thickness: approximately 2 [μm] Growth of second InPlii4 Composition ratio of growth solution: In: 1nP=1 (g): 4.8 (w) Saturation temperature of growth solution: 602 ('C) Start of growth Temperature: 580 ("C) Supercooling degree = 22 [°C] Growth end temperature: 579 ("C) Growth layer thickness: Approximately 1 [μm] Semiconductor substrate of this example formed by the method explained above In, the lattice mismatch Δa/a between InGaAs1it3 and In2 layers 2 and 4 at room temperature is -0.03G
%] and was within the allowable range.

また、この半導体を襞間して襞間断面を観察した結果、
ヘテロ接合界面は平坦であり、１ｎＧａＡＳ層３のメル
トハックも発生していないことが確認された。更に、こ
の半導体を用いて、アバランシェフォトダイオードを形
成して、波長λ−１，６５ｃμｍ〕において励子効率７
０［％〕程度、暗電流が動作電圧の２においてｌＸｌ０
　　（八／　ｃｎｌ〕程度となる良好な結果を得た。In addition, as a result of folding this semiconductor and observing the cross section between the folds,
It was confirmed that the heterojunction interface was flat and no melt hacking of the 1nGaAS layer 3 occurred. Furthermore, using this semiconductor, an avalanche photodiode was formed, and the excitonic efficiency was 7 at wavelength λ-1, 65 cm.
When the dark current is around 0 [%] and the operating voltage is 2, lXl0
A good result of approximately (8/cnl) was obtained.

従来ｌ　ｎ　ＧａＡ３層の液相エピタキシャル成長に際
しては、Ｘ長温度が前記実施例より大幅に高い６５０（
’Ｃ）程度とされている場合が多く、成長温度を低下さ
せるならば成長可能な厚さが制限されるとされていた。Conventionally, in the liquid phase epitaxial growth of l n GaA three layers, the X-length temperature was 650 (
In many cases, it was considered to be about 'C), and it was thought that if the growth temperature was lowered, the thickness that could be grown would be limited.

しかしながら前記実施例のＩｎＧａＡｓ層成長／８液に
ついて第３図に例示する如＜、］ｎＧａΔＳ層の成長厚
さは該溶液の飽和温度と成長終了温度との差すなわち温
度降下幅によって定まり１例えば０．８〔μｍ〕乃至４
．０〔ｐｍ）程度の範囲内の所要の値に温度降下幅の選
択によって制御することができる。However, as illustrated in FIG. 3 for the InGaAs layer growth/8 solution of the above embodiment, the growth thickness of the nGaΔS layer is determined by the difference between the saturation temperature of the solution and the growth end temperature, that is, the temperature drop width. .8 [μm] to 4
．． It can be controlled to a desired value within a range of about 0 [pm] by selecting the temperature drop width.

従って本発明を実施するに当っては、５８０　（’ｃ）
以下に選択された［ｎＧａ八ｓへの成長終了１ＭＬ度に
、所要のＩｎＧａＡｓ層成長厚さが得られる温度降下幅
を加えた温度をその飽和温度とする組成のＩｎＧａＡｓ
層成長溶液を使用する。Therefore, in carrying out the present invention, 580 ('c)
[InGaAs with a composition whose saturation temperature is the temperature obtained by adding the temperature drop width to obtain the required InGaAs layer growth thickness to 1 ML degree of completion of growth to nGa8S selected below.
Use a layer growth solution.

なお、成長温度５８０℃付近の低温におけるＩｎ　ｃ　
ａ　Ａ　Ｓ　Ｍの成長に際して、従来成長温度６５ｏ　
’ｃ付近で行われている例えば０．５　（”Ｃ／　ｍｉ
ｎ　）程度の低い冷却速度とすることなく、　　２　（
’Ｃ／ｍ１ｎ）以上の冷却速度としても良好なるＩｎＧ
ａＡｓＮを得ることができ、これによって］　ｎ　Ｐ　
／　１ｎＧａＡｓ／ＩｎＰ　　ＤＨ構造等を、一定した
冷却速度で連続的に成長させることが極めて容易となる
。Incidentally, Inc. at a low temperature around 580° C.
When growing ASM, the conventional growth temperature was 65o.
For example, 0.5 ("C/ mi
2 (
'C/m1n) or higher cooling rate
aAsN can be obtained, thereby] n P
/1nGaAs/InP It becomes extremely easy to continuously grow a DH structure or the like at a constant cooling rate.

＋ｇｌ　　発明の詳細 な説明した如く本発明によってＩ　ｎ　０．５３Ｇ　ａ
ｏ、４７Ａ　ｓ層を成長させ、続けてこのＩｎＧａＡＳ
層に接するＩｎＰ層を前記先頭願発明によって成長させ
るならば１例えばＩｎＰ／ＩｎＧａＡｓ／ＩｎＰのＤＨ
構造などを連続して容易に形成することができ、かつ従
来問題とされたＩ　ｎＧａＡ３層のメルトバンク並びに
この層と＋ｎＰ層とのへテロ接合界面の劣化が防止され
、また最終のＩｎ２層の表面モフオロジーも良好で、ヒ
ルロック等も生じない。+gl According to the present invention, as described in the detailed description of the invention, I n 0.53G a
o, 47A s layer is grown, followed by this InGaAS layer.
If the InP layer in contact with the layer is grown according to the invention of the first application, 1, for example, a DH of InP/InGaAs/InP.
Structures etc. can be easily formed continuously, and deterioration of the InGaA three-layer melt bank and the heterojunction interface between this layer and the +nP layer, which had been a problem in the past, can be prevented, and the final In2 layer can be easily formed. The surface morphology is also good and no hillocks occur.

従って本発明によって製造された半導体基体を用いて１
例えば発振波長λ−１，６８（μｍ〕程度の発光素子或
いは前記波長をカバーする受光素子等を優れた品質をも
って提供することが可能となる。Therefore, using a semiconductor body produced according to the invention, 1
For example, it is possible to provide a light emitting element with an oscillation wavelength of about λ-1.68 (μm) or a light receiving element covering the above wavelength with excellent quality.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例としたＤ　Ｈ構造の断面図、第
２図は実施例の温度プログラムを示す図表。 第３図は温度降下幅とＩｎＧａＡｓ層の成長厚さとの相
関を示す図表である。 図において、１はＩｎＰ基板、２はＩｎＰ層。 ３はＩ　ｎ　Ｏ，５３Ｇ　ａ　０．４ＴＡ　ｓ層、４は
ＩｎＰ層を示す。 ィ　ｊ　図 一７２図 日１　　　　　間　　　　　　　　〔つＴ」ｆ　５　図FIG. 1 is a sectional view of a D H structure according to an embodiment of the present invention, and FIG. 2 is a chart showing a temperature program of the embodiment. FIG. 3 is a chart showing the correlation between the temperature drop width and the growth thickness of the InGaAs layer. In the figure, 1 is an InP substrate and 2 is an InP layer. 3 indicates an InO, 53G a 0.4TAs layer, and 4 indicates an InP layer. Figure 1 72 Figure Day 1 [T''f 5 Figure

Claims (1)

【特許請求の範囲】 ＋１１（１１１）入面を主面とするインジウム・燐（Ｊ
ｎＰ）基板上に、インジウム・ガリウム・砒素（ＩｎＧ
ａＡｓ）層を成長終了温度を５８０（’Ｃ〕以下として
成長し、続いてインジウム・燐（ＩｎＰ）ｌｉｔを前記
インジウム・ガリウム・砒素（ＩｎＧａＡｓ）層に接し
て成長する工程を含んでなることを特徴とする液相エピ
タキシャル成長方法。 （２）前記液相エピタキシャル成長系の冷却速度が２〔
“Ｃ／ｍ１ｎ）以上であることを特徴とする特許請求の
範囲第１項記載の液相エピタキシャル成長方法。[Claims] Indium phosphorus (J
Indium gallium arsenide (InG
aAs) layer at a growth end temperature of 580 ('C) or lower, and then growing indium phosphorus (InP) lit in contact with the indium gallium arsenic (InGaAs) layer. A liquid phase epitaxial growth method characterized by: (2) The cooling rate of the liquid phase epitaxial growth system is 2 [
2. The liquid phase epitaxial growth method according to claim 1, wherein the liquid phase epitaxial growth method is not less than "C/m1n).
JP57171223A 1982-09-30 1982-09-30 Method for liquid-phase epitaxial growth Pending JPS5961125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57171223A JPS5961125A (en) 1982-09-30 1982-09-30 Method for liquid-phase epitaxial growth

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57171223A JPS5961125A (en) 1982-09-30 1982-09-30 Method for liquid-phase epitaxial growth

Publications (1)

Publication Number Publication Date
JPS5961125A true JPS5961125A (en) 1984-04-07

Family

ID=15919323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57171223A Pending JPS5961125A (en) 1982-09-30 1982-09-30 Method for liquid-phase epitaxial growth

Country Status (1)

Country Link
JP (1) JPS5961125A (en)

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