JPS5960891A - Zero cross detector for dimming discharge lamp - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a zero-cross detection device for dimming a discharge lamp.

In the control system for lighting using discharge lamps,
The phase angle or firing angle of the thyristor is varied to adjust the instantaneous amount of power and thereby the illumination. That is,
Dimming control is performed by determining the firing angle using the zero-crossing point as a reference during the half-cycle period of the sine waveform from the power supply, but the detection of the zero-crossing point may be due to the collapse of the sine waveform from the power supply or the presence of noise components. If this is not done accurately due to contamination, the reference point for determining the ignition angle will float and the flash firing power will fluctuate, causing flickering in the illumination of the discharge lamp.

An object of the present invention is to eliminate inaccurate detection of zero-crossing points due to distortion of the sinusoidal waveform from the power source or noise contamination, and ultimately to eliminate flickering in the illumination of a discharge lamp.

That is, in the present invention, the sine waveform from the power supply is converted into a p-wave, the noise component is removed from the sine wave, and this is shaped, and then the phase delay caused by the p-wave is compensated for to zero/zero the sine waveform from the power supply.
The above objective is achieved by determining a point in time that exactly coincides with the cross point.

The present invention will be described in detail below with reference to the accompanying drawings.

In FIG. 1, a transformer 4 is connected to an input terminal 2-2 to convert a sine wave input signal from a power source to an appropriate voltage. A CRP wave circuit is connected to the secondary side of this transformer. 6 is a variable resistor for phase adjustment, 8 is a fixed resistor, and 10 is a capacitor. The noise component of the sine wave input signal is removed by this CRF wave circuit, but at the same time a predetermined phase lag determined by the size of the fixed resistor 8 and the capacitance of the capacitor 10 occurs. In order to set this phase delay to a predetermined and accurate value, fine adjustment is made using the variable resistor 6.

A full-wave rectifier circuit 12 is connected to the output of the furnace liquid vessel, and an amplifier 14 is connected to the output of this rectifier circuit. A 7 flip-flop circuit 16 is connected to the output of this amplifier 14, and the output of the flip-flop circuit 16 is connected to an AND circuit 18.
Connect to one input terminal of Clock pulse generator 2
0 is connected to the other input terminal of the AND circuit 18. The output terminal of the AND circuit 1B is connected to the counter 22.

This counter 22 is nπ (n is an integer, Tl =
When the clock pulses corresponding to the difference between (case 2) and the phase delay caused by the filter circuit are counted, a carry signal is output and reset is performed. The output terminal of the counter 22 is connected on the one hand to the reset input of the flip-flop circuit 16 and on the other hand to the JK flip-flop. 26
indicates an output terminal.

The operation of the tenth zero-cross detection device will be explained with reference to FIG.

A sine wave input signal from the power supply (Fig. 2g) is input to input terminal 2-.
Added to 2. This input signal has noise components removed by the CRp wave circuit, and at the same time its phase is delayed by θ (second
b), and is rectified by the full-wave rectifier circuit 12 (FIG. 2C). This rectified waveform is applied to the Flip 70 tube 16, and when the rectified voltage exceeds the 7 Lip 70 tube threshold, the Flip 70 tube outputs an output signal (see Figure 2d).
) is added to the AND circuit 18. Clock pulses are applied to this AND circuit 18 from a high-speed pulse generation circuit 20, and these high-speed pulses (Fig. 2e) are applied to the AND circuit 18.
) is counted by the counter 22. In this example, 2
When the clock pulse corresponding to the difference 2π-θ between π and the phase delay θ caused by the filter circuit is counted, a carry signal (FIG. 2f) is output and the counter 22 is reset. This carry signal is applied to the reset terminal of the flip-flop, and the flip-flop is reset at the negative-to-positive zero crossing of the sinusoidal signal from the power supply in preparation for the next cycle's zero-crossing detection.

The carry signal is a detection pulse that precisely coincides with the zero crossing point of the sinusoidal input signal from the power supply, and the firing angle can be adjusted based on this.

In the embodiment of FIG. 1, this detection pulse is applied to the JK flip-flop 24 and its output (FIG. 2g) is used.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of a zero-cross detection device for dimming a discharge lamp according to the present invention. Figure 2 shows the signal waveforms appearing at the input/output terminals of the configuration circuit of the embodiment shown in Figure 1. The output signal of the P-wave circuit, 2nd F] (c) is the output waveform of the full-wave rectifier circuit, Fig. 2 (
d) is the output waveform of the flip-flop; FIG. 2(e) is the clock pulse from the clock pulse generator;
Figure (f) is the carry signal of the counter, Figure 2 (g) is the J
The output waveforms of the K flip-flops are shown respectively. 2...Input terminal, 4...Transformer, 6...Variable resistor, 8...Fixed resistor, 10...Capacitor, 12...
・Full-wave rectifier circuit, 14... Amplifier, 16... Flip-flop, 18... AND circuit, 20... Ria
Twisting/pulsing occurs! , 2/2-... counter, 24-
...JK flip-flop, 26...output terminal. Patent Applicant Toshiba Electric Materials Corporation Agent Patent Attorney Tatsuo Ito Agent Patent Attorney Tetsuya Ito

Claims (1)

[Claims] The furnace liquid circuit connected to the input terminal, the rectifier circuit connected to the output of this furnace liquid circuit, the slip/70 tube circuit connected to the output of this rectifier circuit, the output of this flip-flop and the clock An AND circuit connected to the output of the Hals generator, connected to the output of this AND circuit,
Equipped with a counter that resets by outputting a carry signal when counting clock pulses corresponding to the difference between nπ (n is an integer) and the phase delay caused by the reactor fluid circuit, and the output terminal of this counter is connected to a flip-flop reset terminal. Connect the terminals and reset the flip/70 knob when the nπ phase is delayed from the zero crossing of the input signal. Generate a carry signal, that is, a detection pulse, at the output terminal of the heel counter that matches the zero crossing of the input signal. A zero-cross detection device for discharge lamp dimming characterized by: