JPS595779A - Run-length decoding device - Google Patents

Abstract

PURPOSE:To speed up decoding processing and to simplify operation control by controlling a conversion part which converts a run-length value into a fixed- length binary code and a conversion part which converts the output of a buffer memory into data equal to said value in parallel. CONSTITUTION:An unfixed-length code word (a) inputted from a transmission line is converted by the fixed-length conversion part 12 and the code conversion part 13 into a binary code (c) indicating a run-length (RL) value successively. The binary code (c) outputted on bit-parallel basis is inputted to the parallel code buffer 21. An RL reverse counting part 14 reads binary code c' out of the parallel code buffer 21 successively to count the RL value reversely and restores the outputs a data string (d). The parts on both sides of the parallel code buffer 21 are controlled to operate in parallel independently of each other.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the configuration of a decoding device in a run-length (hereinafter abbreviated as RL) encoding system used in image data compression.

Generally, in an RL encoding device, a part (this is called a run) where the same data values are continuous in a string of input data.
The number of data, ie, RL, is counted, and the KL values are sequentially converted into corresponding code words and outputted to a transmission line, storage device, etc. (hereinafter simply referred to as a transmission line).

On the other hand, the RL decoding device sequentially inversely converts the sequence of code words inputted from the transmission path into KL values, and then
The data string is restored and output by reproducing the data run of only that number while inversely counting.

Here, the RL is naturally not a constant value, and the codeword length is also usually set to a length in order to improve the data compression effect, so the operation timing inside the RL decoding device as described above is complicated, and the input/output speed of codes and data before and after the ILL decoding device is not constant. However, data output devices such as transmission lines and image recording devices that come before and after the decoding device cannot follow such unsteady speed changes, so a buffer memory for timing adjustment is required in between. It is. Here such a buffer is also R
It is assumed that it is included in the L decoding device.

In the following, unless otherwise specified, a case of an ILL decoding apparatus for black and white binary facsimile data will be described as a specific example.

FIG. 1 is a block diagram showing the conventional configuration of the above-mentioned RL decoding device. ,
05) is an output data buffer.

The code and information from the transmission path are input to the code buffer U in the form of one non-fixed length code word (a) connected in series.
After being temporarily stored, they are read out in the order of input.

Each read non-fixed length code word -) is converted into a binary code (C
) is converted to A typical process of this conversion is that a non-fixed-length code m (1) is processed in a bit-serial manner in a fixed-length conversion unit (■), and is first converted into an intermediate fixed-length binary code (b).
Furthermore, the intermediate code (b) is subjected to bit-serial or bit-parallel code conversion in a code converter 03 and is converted into a binary code (C) representing the RL value. Here, bit-parallel code conversion means that the values of each phase of the intermediate binary code (b) are simultaneously processed and converted into a binary code (C) representing the RL value. (Read-only memory) conversion corresponds to this. In this bit-parallel code conversion, the conversion is usually completed in one operation step. Furthermore, bit-serial code conversion refers to intermediate binary code (b)
Code conversion in the decoding of Wy le codes and B2 codes is usually performed in a bit-serial manner by sequentially processing one or more phase values of . This bit-serial code conversion normally requires multiple operation steps, but in many cases it can be performed simultaneously with the previous stage of constant length conversion, in which case the constant length conversion unit (17J and code conversion unit a3) It is not necessary to consider them separately.Next, the binary code (C) that is the output of the code converter u3 is inversely counted by the RL inverse counterer circle, and is
Data (d') having the same data value, ie, runs, are reproduced and output at a rate of one data per count. It is clear from the principle of RL encoding that the data value (-') changes by 19 every time the binary code (C) is input to the RL inverse counter (141), and this output data (d') is sequentially output. The data is input to the data buffer ti51, and after being temporarily stored, it is output to the output device according to the order of input.Here, the data output (d) from the data buffer (151 to the output device) is based on the information reception speed of the output device and the information reception unit. In the example of facsimile data, a white pixel has a data value of '0〃 and a black pixel has a data value of '1#. In between, the received image is intermittently read from the output data buffer 05) and sequentially recorded by the image recording device, thereby outputting the received image.

By the way, in the conventional RL postcoding device having the configuration as shown in FIG.
The process of converting the binary code representing the RL value into a run of data by inverse counting is performed in a time-division manner, and after the code word of one run is encoded and the reproduction of the corresponding data is completed, the code word of the next run is Operational control is performed such that the decoding of the codeword of the run begins. Therefore, for decoding one run, the number of operation steps is the sum of the number of operation steps for constant length conversion and code conversion and the number of operation steps for RL inverse counting. However, this number of operation steps is not constant and varies depending on the run. In addition, the number of operation steps for inversely counting RL is equal to the number of pixels in one scan line and is constant when considering the entire run within one scan line, but the number of operation steps for length conversion and code conversion is constant. is not constant even within one scanning line, and the number of operation steps for the sum of both is also not constant, so the RL decoding device cannot perform decoding processing synchronously on a run-by-run basis or on a scanning-line basis. Internal operation control is complex.

This causes a large number of operation steps required for decoding processing per run due to time-divisional operation, and also poses a big problem when increasing the speed of the RL decoding device.

Furthermore, in the conventional RL decoding device having the configuration as shown in FIG. 1, buffer memory is present at both the input end and the output end, making buffer control complicated. First, in the input code buffer circle, code bits are continuously input according to the information speed of the transmission path, so non-fixed length code words are must be output to the foot length conversion unit (12).On the other hand, the output data buffer 09 requires restored data according to the information speed of the output device, so there is a shortage of restored data to be output (this is called underflora). ] In order to avoid this, the data buffer 05 is
Data must be entered into 1.

To deal with these problems, it is desirable to be able to execute the decoding process as quickly as possible. If the decoding process is too slow, not only will the output device not be able to obtain the correct output, but there is also a risk of overflow occurring in the input code buffer uD. To avoid this, the capacity of the code buffer αD must be made very large. I have to do it.

Furthermore, if there is no balance between the information speed of the transmission path and the information speed of the output device, it is not sufficient to have high-speed decoding processing. However, in data compression using C%RL encoding, it is difficult in principle to maintain this balance regardless of fluctuations in statistics of data such as images, so this is also a big problem in practice.

If the transmission path is too fast, the high-speed decoding process will accumulate more and more restored data in the output data buffer 09, leading to the risk of overflow. To avoid this, the output data buffer 05) must have a very large capacity. No. Considering the capacity to store most of the restored data in preparation for the worst case scenario, the restored data will be huge because it is no longer compressed, unlike code. ), there is also a problem in terms of equipment price. Therefore, a method is often adopted in which the capacity of the data buffer 09 is kept small and the decoding process is executed intermittently so that the restored data does not overflow. It will come. On the other hand, if the output device side is too fast, both the code buffer (111) and the data buffer (151) will become underflow and correct output will not be obtained. Sometimes a method is adopted in which the output device is operated.However, this method requires a mechanism that allows intermittent operation of the output device, but a mechanism that can perform intermittent operation at high speed and accurately requires advanced technology. This poses a practical problem because the cost of the equipment is also high.

In any case, it is not easy to control the operation so that neither overflow nor underflow occurs in both the input code buffer αV and the output data buffer Q51, and an expensive device is required to solve this problem.

As mentioned above, with the configuration of the conventional KL decoding device, the operation control is complicated, and there are also problems when speeding up the decoding process, and solving these problems requires expensive equipment. There were drawbacks.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above. a first conversion unit that converts into parallel binary codes; a buffer memory that sequentially stores the binary codes in parallel bits; and a buffer memory that sequentially extracts the binary codes from the buffer memory and performs inverse counting to determine the length of the binary codes as described above. and a second conversion unit that converts data into a run equal to the RL value, and by controlling the two conversion units to operate in parallel, it is easy to speed up the decoding process. It is an object of the present invention to provide an RL decoding device whose operation can be easily controlled.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an example of an RL decoding device according to an embodiment of the present invention. In the first conversion unit that converts the run-length code (C) into a base code (C), (12 is a constant length conversion unit, αJ is a code conversion unit, and 1211 is a parallel code that sequentially stores the run-length code (C) in bit parallel. The buffer αΦ is a second buffer which sequentially extracts the constant length binary codes from the parallel code buffer (21), performs inverse counting, and converts the codes into runs of the same data whose number is equal to the run length value. This is an RL inverse counting section as a converting section.

(The basic functions of each block from 121 to 041 are
Although it is similar to the case shown in the figure, the input code buffer 011 and output data buffer (I51 in FIG.
It is placed between the inverse counting section α. Although not shown in the drawings, this apparatus is provided with a control section that controls the length conversion section, code conversion section (13i, and RL inverse counting section G4) to operate in parallel.

In FIG. 2, the non-leg length codeword (a) that is input one after another from the transmission path is sequentially inputted into the redundancy converter (12+) and the code converter (marked by u) to sequentially represent the RL value 2 as in the case of FIG. It is converted into a binary code (C).However, here, the code-converted binary code (C) is always output bit-parallel and immediately input to the parallel code buffer c!11.In the parallel code buffer) The binary code (C) representing the RL value is stored bit-parallel, and is output bit-parallel according to the input order. In the RL inverse counting unit 041, a parallel code buffer c
The binary code (C') is sequentially read out from 2υ, the RL value is inversely counted, the data string (d) is restored, and this is output to the output device.

Here, the parts on both sides of the parallel code buffer (211) can be operated independently and in parallel. That is, for a certain run, the non-length code word (a) is converted into a binary code (C ) and the process of converting the binary code (C) representing the -i:RL value for the previous run into a run (d) of data as many as the RL value are executed in parallel in a pipeline manner. This can be done in 1.
This means that the number of operation steps required for decoding processing per run is practically reduced, and the decoding processing speed can be increased accordingly.

Further, the number of operation steps required for KL inverse counting and data reproduction, which are the processes after parallel code buffer L2υ, becomes constant and equal to the number of data in l scanning lines, if the sum is taken for l scanning lines. This has great significance in simplifying the operation control of the RL decoding device and enabling high-speed operation.

If the last operation step of RL inverse counting and data reproduction and the operation step of reading out the binary code representing the next RL value from the parallel buffer Q11 can be performed in the same operation step, one scanning line worth of restored data can be executed. It is possible to continuously output one operation step per data, and the process of converting the binary code representing the RL value into restored data for one scanning line can always be completed within the same amount of time. .

FIG. 3 is a timing chart showing an example of the operation timing of continuous conversion as described above. In the figure, A indicates a clock pulse, which is a continuous pulse at a rate of one clock per one operation step, and is used to perform inverse counting of KL. B shows the output value of the counter at each step and knob, and in particular, the steps where the count value is 0 are shaded.Here, as shown in parentheses in the figure, the count value at the beginning and end of one line When the count value is 0, the binary code representing the RL value is read out from the parallel code buffer Gll at the next clock and set in the counter. When the count value is not 0, the clock pulse (to a clock pulse) is separated by a logic circuit so that the next clock counts down the counter.

The buffer read pulse obtained in this way is C),
The RL countermeasure pulse is (D), which results in the same figure (B
) is guaranteed. Further, since the buffer read pulse (9) is provided once in each run, when a 70 pulse, etc. is operated with this, a data value of 7 as shown in FIG. 4 is obtained. This data value (E) must also be set to a predetermined value at the beginning of one scanning line. Continuous restored data p) is obtained by sampling and outputting the data value (El) with a clock pulse (sampling pulse ( ) having the same frequency ridge and different phase as ~). If this restored data 0 is facsimile data, each small rectangle corresponds to a pixel, and in particular, the diagonally shaded pixels represent black pixels.

The process of RL inverse counting and data reproduction is as follows.

It can be executed continuously with one operation step per data, but on the other hand, the number of operation steps for constant length conversion and code conversion is smaller than the number of steps for RL inverse counting on average. . The reason for this is that converting a non-fixed length codeword into a fixed-length binary code essentially requires an operation step equal to the word length of the non-fixed codeword, and data compression allows this to be encoded. This has been reduced from a fraction of the number of unused data to a fraction of the number of data.

Depending on the specific method of length conversion or code conversion, the operation speed may vary.
・Although it is possible that the number of tubes is larger than the codeword length,
It is normally impossible for the number to be larger than the number of data. Therefore, even if the process of converting a non-fixed length code word into a binary code representing an RL value is performed in an operation step slower than RL inverse counting, the overall processing speed of the decoding apparatus will not be reduced. Furthermore, the processing of leg lengthening conversion and code conversion is usually a little more complicated than the processing of ILL inverse counting and data reproduction, and executing this at a slower speed is important for ensuring the reliability of the operation of the RL decoding device. It brings about sexual improvement. Conversely, if this □ processing can be executed at high speed, processing such as KL inverse counting can be executed at higher speed, and the overall processing speed of the RL decoding device can be further increased.

Another feature of the configuration of the RL decoding device as shown in FIG. 2 is that buffer control is simple. Since the only buffer memory is a parallel code buffer υ that stores fixed-length binary codes representing R and L values, over 7
There is no need to take into account the risks of 0 bits and underflora, and it is only necessary to monitor the amount of stored codes in the buffer (211).

If the information speed of the transmission path on the input side and the information speed of the output device on the output side are balanced, the processing of leg lengthening conversion and code conversion, and the processing of RL inverse counting and data reproduction are sufficient. Buffer control is easy as long as it is fast. In addition, if the transmission line side is too fast, parallel binary codes will be stored in the parallel code buffer Q.To avoid overflow, it is necessary to increase the storage capacity of the 2D Compared to storing restored data in the conventional way, the storage capacity is much smaller and it is that much more economical.On the other hand, if the output device side is too fast, the parallel code buffer will underflow and the correct output will not be possible. Buffer I2 will no longer be available.
1) The output device must be controlled to operate intermittently while confirming that there is a sufficient amount of binary codes, but this situation is no different from the conventional RL decoding device. However, if the storage capacity of the buffer (211) is increased to a certain extent and controlled so that the binary code representing RL is always stored with a margin, fluctuations in the input information speed caused by data compression can be absorbed, and the output device It is also possible to eliminate the need for a mechanism that enables intermittent operation.In particular, if the buffer (21) has a capacity to store a binary code representing the RL value for one image, the output device By performing image recording scanning continuously and performing RL inverse counting and data reproducing processing at high speed in synchronization with this, data reproducing operation can be sped up to the upper limit speed of the image recording device. This means that the entire RL decoding device can achieve extremely high-speed processing.

By the way, in FIG. 2, the non-leg length code word inputted from the transmission line is converted into a binary code (b) with an intermediate leg length in the constant length conversion unit σ2, that is, 2 which directly represents the RL value. Although it is not a binary code, it is converted into a code that has a one-to-l correspondence with this code, and this intermediate code 0 is already bit-parallel, and the code converter a3 converts it into a binary code representing the RL value by bit-parallel conversion. (b) can be obtained, even if the intermediate code (b) is sequentially stored in the parallel code buffer (21) and code conversion is performed immediately after reading out from the parallel code buffer (21), The circumstances described so far remain almost unchanged, and it is possible to simplify the operation control of the ILL decoding device and speed up the processing.

FIG. 4 is a block diagram showing an example of configuring the RL decoding device according to the present invention as described above. In this embodiment, the leg lengthening conversion section @ is connected to the first conversion section, and the code conversion section a3 and R
The L inverse counting section a corresponds to the second converting section t4G.

A parallel code buffer Qυ is placed between the constant length converter and the code converter (13).

In this case, instead of the binary code representing the RL value, an intermediate code (b) equivalent to it is stored, but in this case the number ζ also requires a buffer compared to storing the restored data. 121) will still be smaller. Further, bit-parallel code conversion in the code conversion unit α3 is performed in one operation step, and if this operation step is executed within the same operation step as reading the intermediate code (C) from the parallel code buffer (21), Similarly to the timing chart in FIG. 3, restored data can be output continuously.

As described above, the configuration of the RL5 encoding device according to the present invention has simpler operation control and is suitable for speeding up decoding processing compared to the conventional configuration, and is also advantageous in terms of device cost. ing.

Hereinafter, a specific example of 2.3 of the RL decoding device according to the present invention will be explained with reference to the drawings.

FIG. 5 is a circuit diagram showing an embodiment of a fixed length conversion section a and a code conversion section. It can be applied to codes with properties such as (abbreviated).

In the figure, (511 is a shift register, ■ is a counter, and the link is a ROM.

The non-leg length codeword in the MH code has the property that when the codeword length is greater than 8, all upper bits other than the lower 8 bits are 10'. The circuit in Figure 5 uses this property to lengthen the length of the code, and converts the main part of the code into the lower 8 bits (if the codeword length is less than 8, 10# is added to the upper part to make it 8 bits). is converted into a 12-bit parallel intermediate code 1G using a binary code IC representing the code word length, and a binary code 1C2 of the upper 4 bits representing the code word length, and this is further code converted to obtain a binary code RL representing the RL value. It's something you get.

Prior to inputting the non-fixed length code word SC, a reset pulse t is first applied.
The shift register 611 and counter ω are reset by tp, and their respective outputs all become 10#. Thereafter, clock pulses CP are applied to the clock input terminals GK of the shift register (511 and counter 521) one after another, and in synchronization with this, each bit of the non-length code word SC is sequentially applied to the shift register (511) and the counter (521) from the upper to the lower. 511. As a result, the code word appears at the output terminals Q to q7 of the shift register 6υ in a manner that gradually rises, and this is input to the input terminals 14 to II of the ROM [share].
+. Further, the counter KASUMI is counted up once for each input of the sign bit SC, and the count output to false becomes after the inputs Io to ■ of the ROJ53. If the code word length of the non-fixed length code word is greater than 8 bits, the first code bit input to the shift register 6 will be shifted and lost, but the value of that bit will be '0#'. Because there is, it does not affect the main part of the code, the IC. A code conversion table for 12-bit address inputs I0 to ■II is stored in ROM (-, 31), and when the input is correct, that is, a possible combination of code main part IC and code word length IC1, Only when the code conversion is completed, the output terminal 0° becomes ]" and the code conversion end signal EC is output. In other cases, the output terminal 0° becomes sQ. Also, when the code conversion is completed, the output terminal 0.
A binary code RL representing the RL value is output from O to O, and is written to the parallel code buffer +211.

In this embodiment, the outputs c, , and Ict of the shift register (51) and counter are bit parallel, so by using the combination as an intermediate code IC, it is possible to configure an RL decoding device as shown in Figure %4. be.

In that case, the output of ROM (to) is 1 of output terminal O0.
Only bits are required, and the intermediate code is written to the parallel code buffer. However, immediately after the parallel code buffer ■υ,
A ROM is required as a code converter that inputs the read 12-bit intermediate code and outputs an 8-bit binary code representing the RL value.

FIG. 6 is a circuit diagram showing another embodiment of the leg lengthening conversion unit uz and code conversion unit (13), in which aill is a shift register and (G is a ROM).

In the general non-constant length encoding method, if you simply add 10# code bits to the upper part of each non-length codeword to make it constant length, the original non-length codewords will have the same length. There is a risk that the unique decodability of the code will be lost. However, if a code bit '1# is added immediately above the most significant digit of each non-fixed-length code word, and a code bit of %QI is added appropriately to the upper part to make the length longer, the code becomes unique. Decodability is preserved. The circuit shown in Fig. 6 utilizes this property to perform leg-lengthening conversion to obtain a long-legged and parallel intermediate code IC, which is then subjected to bit-parallel code conversion to create a binary representation of the KL value. It is designated by the symbol KL.

Prior to inputting the non-fixed length code word SC, a specific binary code is set in the shift register (611) by a set pulse SP. Only the highest bit of this binary code is 1 and all other bits are OR. Yes, this is the shift register ttil
) also appears at Q1g.

After this, clock pulse CP or shift register fi one after another
il), and in synchronization with this, the code bits of the non-fixed length code word SC are sequentially input from high order to low order ζ, and are applied to the serial input terminal SI of shift register ff1ll. This allows the shift register (61
), the code word appears in the output terminal Qo-Q+- in a manner that gradually rises, but a specific binary code that is set to 1 is added to the upper part (and the highest 10 #
It shifts from the I pupil to the I pupil and disappears. In this way, up to 13 code@length code words are converted into a 14-bit fixed length code iIC.

The output terminals of the shift register Sen are also connected to the 7° dress input terminals 1o to "ta" of the ROM Kasumi, and when the output 14 bits are correct, that is, a possible leg length code word, El , OM Kasumi's output terminal O0 or l'
This indicates the end of the code conversion, and the binary code KL representing the RL value is output from the output terminals Ol to O. Otherwise, the output terminal O8 is '0#'. When the code conversion is completed, the binary code representing the RL value is written to the parallel code buffer (2) and transferred to the shift register (61).
The specific binary code is set again to prepare for the input of the next non-fixed length code.

In this embodiment as well, the output 14 of the shift register (61)
It is possible to configure the ILL decoding apparatus as shown in FIG. 4 by using the bit binary code as the intermediate code IC and using the same method as explained in FIG. 5.

By the way, in all the embodiments described so far, the code conversion unit αJ is a circuit using a ROM. ROM is a parallel intermediate code which is an input to be converted and RL which is a converted output.
This is extremely convenient because it allows a simple relationship between binary codes representing values in a tabular format. However, if a simple transformation logical relationship exists between the input to be transformed and the transformation output, then RO
It is also possible to configure a code conversion circuit by combining ordinary logic elements other than M. Further, depending on the encoding method, code conversion can be easily performed at the same time as constant length conversion, so there may be no need for a part that performs bit-parallel code conversion processing at all. In that case, since there is no parallel intermediate code, the configuration of the RL decoding apparatus according to the present invention cannot be as shown in FIG. 4, but is limited to the configuration as shown in FIG. 2.

FIG. 7 is a diagram showing an example of the above-mentioned encoding method.

This is a method for generating non-fixed-length codes in the same format as Wy 1 e codes and B2 codes, but it is simpler because the lower significant digits of the binary code representing the RL value appear as they are in the code word. This is a conversion logic. For example, in a binary code representing a run length of 22, only the lower five digits are valid, and the higher digits are all 'θ1L, which merely indicates the scale.

Therefore, the code word is a 6-digit binary code (010
110), a code (110) indicating the number of effective digits is added in front of the symbol (110). The code indicating the number of effective digits is also in the form of 1v, which is one less than 1/2 of the number of effective digits (6), followed by one 10#. It goes without saying that the length conversion and code conversion methods explained in the previous examples can also be applied in this case, but
Based on the information contained in the non-length code word itself, that is, the number of significant digits and the value of each significant digit, it is possible to easily perform length conversion and code conversion at the same time using a circuit such as the one described below, and it is easier for the device to do so. It is also excellent in terms of price.

FIG. 8 shows a circuit for converting a non-fixed-length code word by the encoding method explained in FIG. 7 into a binary code representing an RL value by simultaneously performing fixed-length conversion and code conversion. This is a circuit diagram showing an embodiment. In the figure, (1111 is a shift register, 1111 is a counter capable of up/down counting, 1111 is an R8 type flip-flop, and 1111 is a T type flip-flop. (c) is a NAND circuit, (
A) to (2) are AND circuits.

In FIG. 8, a set pulse SP is first inputted to the shift register (81
All bits of 1 are reset, counter @ and flip-flop (circle) are reset, and flip-flop,
Tsubutoshi is set. This is followed by clock pulse C
Code bits SC are input one after another in synchronization with P. The flip-flop (
Since the output Q of the day is 1171 and the output Q is ``0'',
The clock pulse CP passes only through the AND circuit (861) and is applied to the input terminal CU of the counter (861).
Count up 21. This count up is R
This continues until the last 10# of code bits indicating the number of significant digits of the L value is input, and the count value increases up to the number of code bits in that part. Immediately after inputting the sign bit 10, the output of the NAND circuit connected to the input terminal R of the flip-flop becomes %lj, and the 7 flip-flop is reset.
Thereafter, until the set pulse 5p is input, the reset state is maintained in a self-maintaining manner, so that the count-up is stopped. On the other hand, the output q of the flip 70 knob becomes '''l#, and AN
The clock pulse CP that has passed through the D circuit is applied to the clock input terminal CK of the shift register υ and the trigger input terminal T of the flip 70 (8Φ). The sign bit starts to be input from , and the binary code RL indicating the RL value gradually rises and appears at the output terminal or Qu.On the other hand, the clock pulse CP that has reached the circle of the flip-flop The frequency is divided by 2 and applied to the input terminal CD of the counter Z, and the counter @ is counted down once every two clocks.Then, the count value of the counter ■ is counted down to 0, and the zero output Z becomes %1#. By the time this signal passes through the AND circuit 2 and is output as the ζ signal and the conversion end signal EC, twice the number of clock pulses as the count value counted up at the beginning has been passed through the shift register 18I.
), and at the end of the conversion, the RL value is 2.
The base code RL is the output terminals 1 to q of the shift register υ.
, it appears in . This binary code is then written into the parallel code buffer D.

In the conversion circuit of this example as well, a non-fixed length code word is converted into a fixed length R
The number of operational steps required to convert into a binary code representing the L value is essentially the same as the number of truncated lengths of the non-finite length code word.

Although the configuration of the KL decoding device according to the present invention has been explained above using several specific examples, leg lengthening conversion and code conversion are not limited to these examples. The configuration of the RL decoding device according to the present invention can be applied to any RL encoding method in which a fixed-length binary code representing an RL value is obtained in parallel bits, and fixed-length encoding suitable for each encoding method can be applied. It is possible to find methods for conversion and transcoding.

In the explanation so far, the case of RL encoding of black and white binary facsimile data has been used as a specific example, but data to which RL encoding can be applied, such as image data such as halftone images and color images, Of course, the configuration of the disguise decoding device according to the present invention can be applied to ILL encoded portions of voice data, numerical data, etc. However, like binary facsimile data, R
Since it is not possible to identify the data value of each run only from the sequence of L codewords, it is not possible to identify the data value of each run only from the sequence of L codewords, so it is necessary to perform continuous Consideration must be given to whether data can be regenerated and whether parallel code buffers can be used efficiently. Only when this is possible, the method of configuring the RL decoding device according to the present invention has great significance.

As described above, according to the present invention, the RL decoding device converts each input non-fixed length code word into a constant length bit-parallel binary code that converts each input non-fixed length code word into the value it represents. 1 conversion unit, a buffer memory for sequentially storing the binary codes in bit parallel, and sequentially extracting the binary codes from the buffer memory, inversely counting them, and converting them into a run of data whose number is equal to the RL value. Since the above two converters are operated in parallel, it is suitable for speeding up the decoding process, operation control is simple, and the device is economical in terms of price. It is possible to realize a practically useful RL decoding device that has the possibility of

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional RL decoding device, FIG. 2 is a block diagram showing the configuration of an embodiment of the RL decoding device according to the present invention, and FIG. 3 is a block diagram showing the configuration of an RL decoding device according to the present invention.
FIG. 4 is a timing chart diagram showing an example of the operation timing of continuous inverse counting and data reproduction processing of the L decoding device; FIG. 4 is a block diagram showing the configuration of another embodiment of the RL decoding device according to the present invention; FIG. FIGS. 8 to 8 are diagrams showing specific examples of the constant length converting section and the code converting section of the RL decoding device according to the present invention, FIG. 5 is a circuit diagram showing one embodiment, and FIG. 6 is a circuit diagram showing another embodiment. A circuit diagram showing an embodiment, FIG. 7 is an explanatory diagram of an example of an encoding system with simple code conversion logic, and FIG. 8 is an example of a circuit for leg lengthening and code conversion for the encoding system. It is a circuit diagram. Ta...first conversion section, α2...leg lengthening conversion section, o3
...Sign conversion unit, +41...Second conversion unit, αQ・
...RL inverse counter, (21)...Parallel code buffer. Note that the same reference numerals in the figures indicate the same or similar parts. Agent Shin Kuzuno-T, Figure 1, Figure 2, Figure 4, Figure 5, Figure 6

Claims (1)

[Claims] α) A run-length decoding device I that sequentially decodes an input non-fixed length code string to restore and output a series of data having the same data value of the run length, which is a numerical value represented by each code word. an i-th conversion unit that converts a non-fixed-length code word into a fixed-length binary code corresponding to a run-length value represented by the non-fixed-length code word; a buffer memory that sequentially stores the fixed-length binary code in bit parallel; and the buffer memory a second converting unit that sequentially extracts the constant length binary codes from the first . A run-length decoding device comprising: a control unit that operates a second conversion unit in parallel.