JPS595675A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS595675A JPS595675A JP11511282A JP11511282A JPS595675A JP S595675 A JPS595675 A JP S595675A JP 11511282 A JP11511282 A JP 11511282A JP 11511282 A JP11511282 A JP 11511282A JP S595675 A JPS595675 A JP S595675A
- Authority
- JP
- Japan
- Prior art keywords
- inp
- layer
- type
- indium phosphide
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title description 20
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 9
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010931 gold Substances 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 7
- 239000010936 titanium Substances 0.000 abstract description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 2
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract 1
- NOESYZHRGYRDHS-UHFFFAOYSA-N insulin Chemical class N1C(=O)C(NC(=O)C(CCC(N)=O)NC(=O)C(CCC(O)=O)NC(=O)C(C(C)C)NC(=O)C(NC(=O)CN)C(C)CC)CSSCC(C(NC(CO)C(=O)NC(CC(C)C)C(=O)NC(CC=2C=CC(O)=CC=2)C(=O)NC(CCC(N)=O)C(=O)NC(CC(C)C)C(=O)NC(CCC(O)=O)C(=O)NC(CC(N)=O)C(=O)NC(CC=2C=CC(O)=CC=2)C(=O)NC(CSSCC(NC(=O)C(C(C)C)NC(=O)C(CC(C)C)NC(=O)C(CC=2C=CC(O)=CC=2)NC(=O)C(CC(C)C)NC(=O)C(C)NC(=O)C(CCC(O)=O)NC(=O)C(C(C)C)NC(=O)C(CC(C)C)NC(=O)C(CC=2NC=NC=2)NC(=O)C(CO)NC(=O)CNC2=O)C(=O)NCC(=O)NC(CCC(O)=O)C(=O)NC(CCCNC(N)=N)C(=O)NCC(=O)NC(CC=3C=CC=CC=3)C(=O)NC(CC=3C=CC=CC=3)C(=O)NC(CC=3C=CC(O)=CC=3)C(=O)NC(C(C)O)C(=O)N3C(CCC3)C(=O)NC(CCCCN)C(=O)NC(C)C(O)=O)C(=O)NC(CC(N)=O)C(O)=O)=O)NC(=O)C(C(C)CC)NC(=O)C(CO)NC(=O)C(C(C)O)NC(=O)C1CSSCC2NC(=O)C(CC(C)C)NC(=O)C(NC(=O)C(CCC(N)=O)NC(=O)C(CC(N)=O)NC(=O)C(NC(=O)C(N)CC=1C=CC=CC=1)C(C)C)CC1=CN=CN1 NOESYZHRGYRDHS-UHFFFAOYSA-N 0.000 description 22
- 102000004877 Insulin Human genes 0.000 description 10
- 108090001061 Insulin Proteins 0.000 description 10
- 229940125396 insulin Drugs 0.000 description 10
- 230000005533 two-dimensional electron gas Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical group [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910001392 phosphorus oxide Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- VSAISIQCTGDGPU-UHFFFAOYSA-N tetraphosphorus hexaoxide Chemical compound O1P(O2)OP3OP1OP2O3 VSAISIQCTGDGPU-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本兜明は半導体装置に関する。特に、常温において高い
スイッチングスピードをもって動作し、しかも、安定な
特性を有する半導体装置のゲート構造の改良に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a semiconductor device. In particular, the present invention relates to improvements in the gate structure of semiconductor devices that operate at high switching speeds at room temperature and have stable characteristics.
（２）技術の背景
本発明に関する半導体装置とは電子親和力の相異なる２
種の半導体を接合することにより形成される一つのへテ
ロ接合面の近傍に発生する電子蓄積群（二次元電子ガス
）の電子面濃度を制御電極に印加される電圧によって制
御して、この制御電極を挟んで設けられた一対の出力電
極間に上記の蓄積電子群（二次元電子ガス）をもって形
成される導電路のインピーダンスを制御する能動的半導
体装置をいう。(2) Technical background The semiconductor device related to the present invention has a different electron affinity.
This control is performed by controlling the electron surface concentration of an electron accumulation group (two-dimensional electron gas) generated in the vicinity of one heterojunction surface formed by joining different semiconductors by a voltage applied to a control electrode. It refers to an active semiconductor device that controls the impedance of a conductive path formed by the above-mentioned group of accumulated electrons (two-dimensional electron gas) between a pair of output electrodes provided with an electrode in between.
かかる半導体装置を構成しうる半導体の組み合わせに対
する条件は、（イ）互に格子定数が同一であるか近似し
ていること、（ロ）電子親和力の差が大きいこと、（ハ
）バンドギャップの差が大きいこと等であり、多数の組
み合わせが存在する。更に、その構造において、特定の
要件を充足すればノーマリオン型も、ノーマリオフ型も
夫々製造することが可能である。The conditions for the combination of semiconductors that can constitute such a semiconductor device are (a) their lattice constants are the same or similar, (b) there is a large difference in electron affinity, and (c) there is a difference in band gap. is large, and there are many combinations. Furthermore, in terms of the structure, it is possible to manufacture either a normally-on type or a normally-off type, if specific requirements are met.
この半導体装置の大きな特徴は、上記の蓄積電子群（二
次元電子ガス）の電子移動度が特に低温において非常に
大きくなることであるが、インジュウムリン（ＩｎＰ）
とインジュウムガリュウムヒ９４ （ＩｎＧａＡｑ）と
の組み合わせよりなる半導体装置は室温における電子移
動度が他の組み合わせに比し゛て非常に大きいという特
徴を有する。本発明はこのインシュラムリン（Ｉｎｋ）
とインジュウムガリュウムヒ素（Ｉ ｎ （ｊａ Ａｓ
）とをもって形成される半導体装置の改良である。A major feature of this semiconductor device is that the electron mobility of the above-mentioned accumulated electron group (two-dimensional electron gas) becomes extremely large, especially at low temperatures.
A semiconductor device made of a combination of InGaAq and InGaAq is characterized by a much higher electron mobility at room temperature than other combinations. The present invention utilizes this insulin (Ink).
and indium gallium arsenic (I n (ja As
) is an improvement of a semiconductor device formed by
（３）従来技術と問題点
このような半導体装置のゲート部分の構造は通常ショッ
トキ接合型とされているが、上記のインシュラムリン（
ＩｎＰ）とインジュウムガリュウムヒ素（ＩｎＧａＡｓ
）との組み合わせよりなる半導体装置においては、ショ
ットキバリヤの降服電圧が小さいため、入力信号電圧を
太き（できないという欠点があり、また逆方向リーク電
流も看做しがたい。そこで、ゲート電極と電子供給層と
の間に絶縁物を介在させて、いわゆる絶縁ゲート型構造
となす方法が提案されているが、この絶縁ゲート型構造
においては、電子供給層をなすインシュラムリン（Ｉｎ
Ｐ）の表面に陽極酸化法等を使用して酸化インジュウム
及び酸化リンとの混合組成よりなる酸化膜を形成するが
、この酸化膜とインシュラムリン（ＩｎＰ）との界面に
表面準位が先生し、この表面準位における充放纜により
、電子供給層とチャンネル層との間の界面電位が変化し
、動作の不安定性を招（原因となる。(3) Prior art and problems The structure of the gate part of such a semiconductor device is usually a Schottky junction type, but the above-mentioned insulin (
InP) and indium gallium arsenide (InGaAs
), the breakdown voltage of the Schottky barrier is small, so the input signal voltage cannot be increased (increasing the input signal voltage), and reverse leakage current is also difficult to consider. A method has been proposed in which an insulator is interposed between the electron supply layer and the so-called insulated gate structure.
An oxide film consisting of a mixed composition of indium oxide and phosphorus oxide is formed on the surface of P) using an anodic oxidation method or the like, but surface states are generated at the interface between this oxide film and insulin (InP). Due to this charging and discharging in the surface states, the interfacial potential between the electron supply layer and the channel layer changes, causing instability in operation.
（４）９Ｑ明の目的
本発明の目的はこの欠点を改良することにあり、室温に
おいて高い電子移動度を有するインシュラムリン（Ｉｎ
Ｐ）／インジュウムガリュウムヒ素（Ｉ ｎ ＧａＡｓ
）よりなる半導体装置において、逆方向リーク電流や動
作の不安定性を伴わないゲート構造を有する半導体装置
を提供することにある。(4) Purpose of 9Q Light The purpose of the present invention is to improve this drawback.
P)/Indium gallium arsenide (In GaAs
) It is an object of the present invention to provide a semiconductor device having a gate structure that is free from reverse leakage current and operational instability.
（５）発明の構成
本発明の特徴的構成は、基板上に形成されたインジュウ
ムガリュウムヒ素（Ｉ ｎ Ｇａ Ａｓ）よりなるチャ
ンネル層とｎ型のインシュラムリン（Ｉｎｋ）よりなる
電子供給層とから構成される二重層と、該二重層上に形
成されたｐ型のインシュラムリン（ＩｎＰ）よりなる層
と、該ｐ型のインシュラムリン（ＩｎＰ）よりなるｊ−
に設けられた制御電極とを含んでなる。(5) Structure of the Invention The characteristic structure of the present invention is that a channel layer made of indium gallium arsenide (In Ga As) and an electron supply layer made of n-type insulin (Ink) are formed on a substrate. a bilayer made of p-type insulin (InP), a layer made of p-type insulin (InP) formed on the bilayer, and a layer made of p-type insulin (InP).
and a control electrode provided at the.
本発明の発明者は、インシュラムリン（ＩｎＰ）／イン
ジュウムガリュウムヒ素（ＩｎＧａＡｓ）よりなる半導
体装置において、そのゲート構造をショットキバリヤ型
としても、絶縁ゲート型としても上記のような不利益を
生じるという点に鑑み、ゲート構造を接合型とすれば、
上記の欠点が解消されるとの着想を得て、ｎ型インジュ
ウムリン（口ＩｎＰ）よりなる電子供給層上にｐ型イン
ジュウムリン（ｐ ＩｎＰ ）よりなる層を設け、その
上にゲート電極を形成する構造となす、上記の如き欠点
がなく、動作が安定な半導体装置が製造可能であること
を確認して本発明を完成した。The inventor of the present invention has discovered that, in a semiconductor device made of insulumrin (InP)/indium gallium arsenide (InGaAs), the disadvantages described above occur regardless of whether the gate structure is a Schottky barrier type or an insulated gate type. Considering this, if the gate structure is a junction type,
With the idea that the above drawbacks could be solved, a layer made of p-type indium phosphorus (pInP) was provided on the electron supply layer made of n-type indium phosphorus (InP), and a gate electrode was formed on top of the electron supply layer made of n-type indium phosphorus (InP). The present invention was completed after confirming that it is possible to manufacture a semiconductor device which does not have the above-mentioned drawbacks and has a stable operation.
（６）発明の実施例
以下図面を参照しつつ、本発明の一実施例に係る半導体
装置について説明し、本発明の構成と特有の効果とを明
らかにする。(6) Embodiment of the Invention A semiconductor device according to an embodiment of the invention will be described below with reference to the drawings, and the structure and unique effects of the invention will be clarified.
第１図参照
鉄（Ｆｅ ）を不純物として含有させ半絶縁性とされた
半絶縁性インシュラムリン（１ｎＰ）よりなる基板１上
に、化学気相成長法（（、’ＶＪ））法を使用して、厚
さが１ 〔μｍ〕程度のノンドープインジュウム力すュ
ウムヒ素（Ｉｎ ｏ、ｓａ （３ａｏ４７Ａｓ）よりな
るチャンネル層２と厚さが６５０ＣＸ〕程度であり、ｎ
型不純物として硫黄（Ｓ）を１０１８／ ｃａｎ ”
程度含有するｎ＋型インジュウムリン（ｎ＋ＩｎＰ）
よりなる電子供給層３と、さらに、厚さが１０Ｏｆ：Ａ
）程度でｎ型不純物として亜鉛（Ｚｎ）を１０〜１０
／ｃａｎ程度含有スるｐ＋型インジュウムリン（ｐ＋Ｉ
ｎＰ）層４とを順次形成する。このとき、チャンネル層
２は低濃度であればｐ型の不純物を含有してもｎ型の不
純物を含有してもさしつかえない。この結晶プロファイ
ルにおいては、チャンネル層２と電子供給層３とのへテ
ロ界面近傍に二次元電子ガスよりなる電子蓄積層５が先
生する。Refer to Figure 1. Chemical vapor deposition ((,'VJ)) was used on a substrate 1 made of semi-insulating insulin (1nP) containing iron (Fe) as an impurity to make it semi-insulating. The channel layer 2 is made of non-doped indium arsenide (Ino, sa (3ao47As)) with a thickness of about 1 [μm] and the thickness is about 650CX].
1018/can” with sulfur (S) as type impurity
Containing n+ type indium phosphorus (n+InP)
The electron supply layer 3 further has a thickness of 10Of:A.
) with zinc (Zn) as an n-type impurity of 10 to 10
p+ type indium phosphorus (p+I
nP) layer 4 are sequentially formed. At this time, the channel layer 2 may contain p-type impurities or n-type impurities as long as the concentration is low. In this crystal profile, an electron storage layer 5 made of a two-dimensional electron gas forms near the hetero interface between the channel layer 2 and the electron supply layer 3.
第２図参照
チタン、白金、金（′Ｔｉ／Ｐｔ／Ａｕ）の三重層より
なる制御電極６をゲート電極形成領域に選択的に形成す
る。この工程は、制御電極形成領域以外の領域を二酸化
シリコン（Ｓ ｉＵ２ ）等のマスクで覆ったのち、ス
パッタ成長法等を使用して上記の三重層６を形成するこ
とにより実行可能である。Referring to FIG. 2, a control electrode 6 made of a triple layer of titanium, platinum, and gold ('Ti/Pt/Au) is selectively formed in the gate electrode formation region. This step can be carried out by covering the region other than the control electrode forming region with a mask such as silicon dioxide (S iU2 ), and then forming the above triple layer 6 using a sputter growth method or the like.
第３図参照
入・出力電極形成領域にシリコン（８１）等ｎ型不純物
をイオン注入法を用いてチャンネル層２に達する深さに
導入し、これに４５０［’Ｃ）程度の温度をもってなす
熱処理を施こして、人ｅ出力電也との電極接続領域７を
形成する。Refer to Figure 3. An n-type impurity such as silicon (81) is introduced into the input/output electrode formation region by ion implantation to a depth that reaches the channel layer 2, and then heat-treated at a temperature of about 450 ['C]. The electrode connection area 7 with the human output power cable is formed by performing the following steps.
続いて、真空蒸着法を使用して、金ゲルマニュウム（Ａ
ｕ（３ｅ） ／金（Ａｕ）の二重層よりなる出力型＆８
を選択的に形成する。また、この出力電極８の形成に先
立ち、ｐ＋型インジュウムリン（ｐ”１ｎＰ）層４を制
御電極形成領域以外の領域から除去し、しかるのちに、
上記と同様の工程をもって出力電極８を電子供給層４と
直接接触させて形成すると更に有利である。ｐ型不純物
を補償する必要がないからである。このとき、ｐ 型イ
ンシュラムリン（ｐＩｎｌ、’）層４のエツチングはゲ
ート電極６をマスクとして選択的に実行される
このようなゲート構造を有する半導体装置においては、
リーク電流の尭生を伴なわず、また、絶縁物を介在しな
いため表面準位も発生することなく、電子供給層とチャ
ンネル層との界面電位を安定に制御することができる。Subsequently, gold germanium (A
Output type &8 made of double layer of u(3e)/gold (Au)
selectively formed. In addition, prior to forming the output electrode 8, the p+ type indium phosphorus (p"1nP) layer 4 is removed from the region other than the control electrode formation region, and then,
It is further advantageous to form the output electrode 8 in direct contact with the electron supply layer 4 using a process similar to that described above. This is because there is no need to compensate for p-type impurities. At this time, the p-type insulin (pInl,') layer 4 is selectively etched using the gate electrode 6 as a mask. In a semiconductor device having such a gate structure,
The interfacial potential between the electron supply layer and the channel layer can be stably controlled without causing a leakage current and without generating surface states since no insulator is involved.
（７）発明の詳細
な説明せるとおり、本発明によれば、室温で高い電子移
動度を有するインシュラムリン（ＩｎＰ）／インジュウ
ムガリュウムヒ素（Ｉ ｎ Ｇａ Ａｓ）よりなる半導
体装置において、逆方向リーク電流や動作の不安定性を
伴なわないゲート構造を有する半導体装置を堤供するこ
とができる。(7) As described in detail, according to the present invention, in a semiconductor device made of insulin (InP)/indium gallium arsenide (In Ga As), which has high electron mobility at room temperature, A semiconductor device having a gate structure without leakage current or operational instability can be provided.
第１図乃至第３図は本発明の一実施例に係る半導体装置
の主要製造工程完了後の基板断面図である。
１・・・・・・半絶縁性基板（ＩｎＰ） 、２・・・・
・・チャンネル層（ノンドープ Ｉｎｏ、５ａＱａｏ、
ｎＡｓ） 、３ ・・・・・・電子供給層（ｎ”ＩｎＰ
層）、４・・・・・・戸車インジュウムリン（ＩｎＰ）
層、５・・・・・・電子蓄積層（二次元電子ガス）、６
・・・・・・制御電極（Ｔｉ ／Ｐｔ ／Ａｕ三重層）
、７・・・・・・出力電橋接続領域、８・・・・・・出
力電極（Ａｕ−（Ｊｅ／ Ａｌ！三重層）。1 to 3 are cross-sectional views of a substrate after completion of the main manufacturing steps of a semiconductor device according to an embodiment of the present invention. 1... Semi-insulating substrate (InP), 2...
...Channel layer (non-doped Ino, 5aQao,
nAs), 3...Electron supply layer (n"InP
layer), 4...Doguruma indium phosphorus (InP)
Layer, 5... Electron storage layer (two-dimensional electron gas), 6
・・・・・・Control electrode (Ti/Pt/Au triple layer)
, 7... Output bridge connection area, 8... Output electrode (Au-(Je/Al! triple layer).
Claims (1)
るチャンネル層とｎ型のインジュウムリンよりなる電子
供給層とから構成される二重層と、該二重層上に形成さ
れたｐ型のインジュウムリンよりなる層と、該ｐ型のイ
ンジュウムリンよりなる層上に設けられた制御電極とを
含んでなることを特徴とする半導体装置。A double layer consisting of a channel layer made of indium gallium arsenide formed on a substrate and an electron supply layer made of n-type indium phosphorus, and a p-type indium phosphorus formed on the double layer. and a control electrode provided on the layer made of p-type indium phosphorus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11511282A JPS595675A (en) | 1982-07-01 | 1982-07-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11511282A JPS595675A (en) | 1982-07-01 | 1982-07-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS595675A true JPS595675A (en) | 1984-01-12 |
Family
ID=14654530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11511282A Pending JPS595675A (en) | 1982-07-01 | 1982-07-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS595675A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814836A (en) * | 1985-03-21 | 1989-03-21 | Itt Gallium Arsenide Technology Center A Division Of Itt Corporation | FET photoconductor with a heterojunction in the channel |
| JPH0270082A (en) * | 1987-06-15 | 1990-03-08 | Pacific Fuarukon:Kk | Device for electrically regulating electrode in electrolytic cell and method for electrically regulating inside of the cell |
| US4962409A (en) * | 1987-01-20 | 1990-10-09 | International Business Machines Corporation | Staggered bandgap gate field effect transistor |
| US4996570A (en) * | 1987-12-23 | 1991-02-26 | U.S. Philips Corp. | Semiconductor structure having a conductive channel |
| JPH03267389A (en) * | 1990-03-16 | 1991-11-28 | O D S:Kk | Electrolytic ozonizer |
| JPH0617277A (en) * | 1990-09-03 | 1994-01-25 | Xueming Zhang | Device for electrolysis of water |
-
1982
- 1982-07-01 JP JP11511282A patent/JPS595675A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814836A (en) * | 1985-03-21 | 1989-03-21 | Itt Gallium Arsenide Technology Center A Division Of Itt Corporation | FET photoconductor with a heterojunction in the channel |
| US4962409A (en) * | 1987-01-20 | 1990-10-09 | International Business Machines Corporation | Staggered bandgap gate field effect transistor |
| JPH0270082A (en) * | 1987-06-15 | 1990-03-08 | Pacific Fuarukon:Kk | Device for electrically regulating electrode in electrolytic cell and method for electrically regulating inside of the cell |
| US4996570A (en) * | 1987-12-23 | 1991-02-26 | U.S. Philips Corp. | Semiconductor structure having a conductive channel |
| JPH03267389A (en) * | 1990-03-16 | 1991-11-28 | O D S:Kk | Electrolytic ozonizer |
| JPH0617277A (en) * | 1990-09-03 | 1994-01-25 | Xueming Zhang | Device for electrolysis of water |
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