JPS5952551B2 - Gate turn-off thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate turn-off thyristor (hereinafter referred to as GTO) having a multi-emitter structure.

Generally, a GTO with a large current capacity must have a multi-mitter structure, and therefore a plurality of GTOs are connected in parallel to form one GTO.

The current capacity of an individual GTO (referred to as a GTO element) is usually about 100A, but even if a plurality of such GTO elements (for example, 100) are connected in parallel, the current capacity is about 400A at most. This indicates that current concentration occurs in a specific GTO element when the GTO is turned off, and that at most three elements bear the entire current in the final stage of turn-off. So GT
O requires base diffusion control and control of base lifetime.

However, with the current technology, it is almost impossible to uniformly apply these to a 40-fold circumferential φ wafer, and a certain degree of non-uniformity is an unavoidable condition. For example, it is common sense to connect GTO elements whose resistances differ by about 0.1Ω in parallel. Here, there are two GTOs with resistances of 1.4Ω and 1.5Ω.
Consider the case where elements A and B are connected in parallel. If the forward voltage drop is 1.5V, the current borne by each is A
is 1.07A, and B is IA. When a common gate current is applied to these to turn them off, B escapes from the saturation state earlier than A and shifts to a high impedance state. During this time, a constant bias is applied between the anode and cathode, so A will bear the entire current at a certain time. FIG. 1 shows an explanatory diagram of this phenomenon. In other words, the GTO current concentration phenomenon is a positive feedback,
Conventional methods cannot prevent this. Although the above explanation is based on the case of two GTO elements, there is no essential change even if there are a large number of GTO elements, and this is an important problem in increasing the current of the GTO.

This invention was made in response to the above-mentioned problems.
A gate turn-off thyristor having a multi-emitter structure capable of increasing current capacity is provided.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a schematic structure of an embodiment of the present invention, and FIG. 3 shows an impurity concentration profile in the depth direction of FIG. 2.

Therefore, the first emitter region 21 has an n'''-n--nf structure, but the n''' layer 2la on the front side is the cathode electrode 25.
This is due to ohmic contact. The manufacturing method is n゛21
- A polycrystalline semiconductor layer 21b is formed by CVD on the surface of the nf layer 21C of the wafer 28 diffused into the P22-n-23-P24 structure, and the n'' layer 21a is further placed on top of it to enable ohmic contact. In FIG. 2, 26 is an anode electrode, and 27 is a gate electrode.
Normally, the relationship between the impurity concentration C (Cm-3) of a silicon semiconductor and the sheet resistance ρ (Ω·Cm) is approximately inversely proportional in a region where the impurity concentration is low, and can be written as the following equation.

ρC+5×1015 That is, C and ρ. The value of is as follows.

The single crystal high resistance layer is formed with a high impurity concentration n+ (usually 1020c
m-3 or more), impurities seep from the n+ layer to the high resistance layer, so the impurity concentration in the high resistance layer is at most 1015c.
It cannot be lowered to m-3 by seven.

In other words, the sheet resistance value of the high resistance layer is at most 5Ω-C.
It is m. When the first emitter region λ structure has an r-n-1n+ structure as shown in FIG. 2, the thickness of the high-resistance layer is at most 10
On the order of μm, the area through which the current flows is 2501 tm x 4 mm
Therefore, the resistance R, (Ω) of this layer is as follows.

In other words, for single crystals, R should be 0.5Ω or more? It is very difficult to do so. Therefore, if the n-layer 21b, which is the high-resistance layer of the first emitter region 21, is made of a single crystal, the resistance of the n-layer 2]b is only about 0.5Ω as described above, so each GTO element The average 5 equalization of the anode current is 2
The improvement is about 0 to 30%.

On the other hand, if the n-layer 21b is made of polycrystal as in the present invention, the resistance of the n-layer 21b becomes 50 [Ω] or more at the impurity concentration of polycrystalline Si ~1015/Cm2, so each GTO element The averaging of the anode current is improved by more than 90%, and one GTO element no longer bears the entire current, making it possible to significantly increase the current capacity. As described above, by providing a polycrystalline semiconductor layer (resistance layer) in the first emitter region, when multiple GTO elements are operated in parallel, the anode current of each element can be significantly averaged, increasing the current capacity of the GTO. can do.

Also, current concentration at turn-off is a positive feedback, but when current concentration occurs due to the presence of a resistance in the emitter region, it has the effect of dispersing the current, so a negative feedback mechanism has been introduced. Therefore, the polycrystalline semiconductor layer in the emitter region allows the current capacity to be increased without impairing other GTO functions.

[Brief explanation of drawings]

Fig. 1 is a diagram showing waveforms representing the unbalance of the anode currents of two GTO elements, Fig. 2 is a diagram schematically showing the structure of an embodiment of this invention, and Fig. 3 is a diagram showing the depth of Fig. 2. FIG. 2 is a diagram showing an impurity concentration profile in the horizontal direction. In FIG. 2, 21 is a first emitter region, 21a is a gear layer for forming an ohmic electrode, 21b is a polycrystalline semiconductor layer which is the key point of this invention, 21C is a breakdown layer, 22 is a first base region, 23 is the second base region, and 24 is the second base region.
This is the emitter area.

Claims (1)

[Claims] 1 In a gate turn-off thyristor with a multi-emitter structure, the emitter region is n^+-n^--n^
A gate turn-off thyristor characterized in that it has a + structure and its n^- layer is made of a polycrystalline semiconductor.