JPS5952493A - Information processor - Google Patents

Abstract

PURPOSE:To prevent the operating efficiency of a processor from being decreased, by applying a clock signal with changed phase at each processor and switching a system bus of each processor with the clock signal so as to access respectively a common memory. CONSTITUTION:An MPU clock signal generating circuit 3 applies the clock signal directly to an MPU2 and to an MPU1 via a phase inverting circuit 4. Thus, since an address switching circuit 5 and a data switching circuit 9 switch address buses 11, 21 and data buses 12, 22 in the MPU1 and MPU2 and apply the signal to the common memory 8, the MPU1 can access the common memory 8 at a half period of the clock signal and the MPU2 can access the memory at the remaining half period. Thus, when one MPU accesses the common memory 8, the other MPU is at an idle time and both the MPUs can access the common memory 8 independently.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor type information processing device having a plurality of microprocessors, and is suitable for refreshing dynamic memory without using it as a common memory. ! Regarding equipment.

Generally, in a multiprocessor system having a plurality of microprocessors, a common memory m- which is not accessible from each processor ν° is used for exchanging data between the processors ν°. This: Since it is not possible to access the common memory from each of the IIE Tsumemory companies at the same time, it is possible to increase the agility of the processor and allow the high-priority processor to access the common memory from other processors. Processor is stopped. However, this method requires frequent data transfer between processors.

The disadvantage is that as the number of memory accesses increases, the operating efficiency of Prosets decreases.

Furthermore, if a cost-effective dynamic memory is used to increase the storage capacity of a common memory, it is necessary to read the address of the memory at regular intervals or perform a fresh operation. In this case, the common memory requires the supply of a fresh address in order to refresh the memory in addition to access from each network memory, and in this case, the refresh and wb operations are performed in order to save the contents of the memory. Since υ is a process that should be prioritized over access requests from the processor, the operating efficiency of the processor further decreases.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned conventional drawbacks, and in a multiprocessor system using dynamic memory as a common memory, even if one of the processors accesses the common memory, the other processors do not stop. Another object of the present invention is to provide an information processing device that does not reduce the operating efficiency of a processor due to the common memory's fresh operation.

In order to achieve the above object, the present invention provides all
In order to synchronize the clocks of the memory cells, the same clock signal generating means supplies a clock signal (17) with a different phase for each access, and a signal of Sysdeno, disconnecting the bus with a clock signal JfJ8 ?
Furthermore, by detecting a period when none of the processors is accessing the common memory and supplying a refresh address to the common memory during that period,
17 so as not to reduce the operating efficiency of the processor.

The present invention will be explained in detail below using FIGS. 1 and 2. FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention. In Fig. 1, 1 and 2 are microprocessors (abbreviated as MJ), 3 is an MPU clock signal generation circuit, 4 is a phase inversion circuit, 5 and , common memory, 9 is a data switching circuit, ], 00
1M1UlOJ, 2Kari1': This is a common memory selection detection circuit that detects whether or not the common memory 8 has been selected.

′! F, 11 and 12t'', AfpUl (7) 7 Dresshas Oyohi Data Bus, 2], and 22 i:
These are the address bus and data bus of M11U2.

The operation 1d of the information processing device of the multi-processor system shown in FIG. 1 is as follows. In Figure 3, Af
PU clock (N number generation circuit 3 is connected to MPU1 and MI
Generates a signal to be supplied to Yla, l2, MpH
2 is directly supplied to MPUIIICIt and via a phase inversion circuit 4, respectively. Therefore, the address signals and data appearing on the address bus 11 and data bus 12 of MIUf; address and data appearing on the address buses 21 and 22 of MIUf are shifted from each other by half a period of the clock signal on the bus. Output □ Output. The address switching circuit 5 and the data switching circuit 9 are connected to the address bus 11 of All"U1 by the r-check signal.
The common memory 8
Therefore, in half the period of the clock signal, MI'
It A (rYJB can access the common memory 8 in half the period of ye b. Therefore,
During the period when one AirU accesses the common memory 8, the other AirU is in a dormant period, so MI'
There is no longer a need to stop U, and both 1M) can freely access the common memory 8 independently of each other.

Next, the riff 1/switching circuit of the common memory 8 (this will be explained) is switched by the address switching circuit 5, Afl'Uli or Air.
The address ξ from U2 and the refresh address from the linkage device attnos generation circuit 6 are switched according to the detection output of the common memory selection detection circuit 10. The detection circuit 10 determines whether the address signals of AT1/subas, 'L, and 1.21 Jl designate an address that has been stored in the common memory 8 or not.

Therefore, as shown in the timing diagram of M2 diagram, A, fl
'U1. And when Afl'U2 accesses the common memory 8 (in the case of the address shown in Figure 2, ■, 0), the address of Mr'U1 or 2 is supplied to the common memory 8, and the common memory 8 is - If neither Ml'r11 nor MI'U2 accesses the common memory 8, a refresh command is sent from the address generation circuit 6.

The address is provided to the common memory 8 so that the common memory can be refreshed. Refresh 5. Address generation circuit 6
If the refresh at1/s generated in 1/2 is made to output the same address for a period longer than the period of the clock signal (for example, 4 times to 16 times), All'U1 and MP
Even if t12 continues to access the common memory, the refresher address can always be transferred to the common memory 8, so refreshes and misses will not occur. (Usually, out of the total number of machine cycles that a processor requires for instructions to read and write common memory, 1 machine cycle is used to access common memory.) As explained above, According to this embodiment, since the two MI'Us are configured to be able to access the common memory every "1" period of the clock signal, @111.171. 1 (The common memory can be accessed, and the common memory can also be refreshed using two A
, fl'U's free time is effectively utilized 12, so that the operating QH efficiency of each AfplJ is not reduced.

In this example, two A4PUs are used.
Even if the number 4 in All'lJ increases, there is no problem v, 1.

As mentioned above, there is an information processing device for a multiprocessor system according to the present invention! In other words, since various processors can be operated according to six phase differences in clock signals, each processor can freely access the memory independently, and the access gap caused by processors can be reduced. The common memory can be refreshed using time, and the operating efficiency of the processor will not be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device of a multiprocessor system showing an embodiment of the present invention. ], 2... AfrlJ 3... 1-turn signal generation circuit 4... Phase inversion circuit edge... Address switching circuit 6... Refresh, address switching circuit 8...・Common memory 9...Data switching circuit 10...Common memory selection detection circuit Attorney Susuki 1) Interest, +9 Figure 1

Claims (1)

[Claims] Information comprising a plurality of arithmetic processing units and an address generation unit that generates a address for refreshing a common memory commonly used by each of the arithmetic processing units. In the processing device, a clock signal generating means for generating a clock signal for operating all of the plurality of arithmetic processing devices in synchronization, and a phase changer for changing the phase of the clock signal and supplying it to each performance processing device*. a shift means, a path switching means that switches according to the phase of each system path rough signal of the arithmetic processing unit and supplies it to the common memory, and a common memory that detects whether the common memory is being accessed by the arithmetic processing unit. a selection detection means; when the common memory is accessed, the address from the arithmetic processing unit selecting the common memory is supplied to the common memory; when the common memory is not accessed, the above refresh code is sent from the address generator; 1. A stone information processing device comprising: a stone address switching means for switching an address signal so as to supply an address to a common memory.