JP2004102808A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To promptly perform DMA (direct memory access) transfer in recovering from an energy saving mode in a memory controller which controls read/write of a DDR (double data rate) SDRAM (synchronous dynamic random access memory). <P>SOLUTION: The memory controller 1 which controls the read/write of data of a memory unit 10 consisting of a plurality of memory cells is provided with first and second DMA controllers 4, 5 which perform the DMA transfer of read data, first and second DMA controllers 6, 7 which perform the DMA transfer of written data, a self-refreshment control part 8 which outputs a request signal for setting and releasing self-refreshment and a memory arbiter 3 which performs arbitration to each request and the next address is inputted in the memory arbiter 3 from the first and second reading DMA controllers 4, 5. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a DDR SDRAM memory control device capable of quickly performing a DMA (Direct Memory Access) transfer when returning from an energy saving mode.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a DRAM (Dynamic RAM (Random Access Memory)) has been used more widely than an SRAM (Static RAM) because it has a lower cost per storage capacity and has a simpler internal circuit than an SRAM (Static RAM), and is used as a main memory of a personal computer. Have been. Among DRAMs, an SDRAM (Synchronous DRAM) receives a clock signal directly to the DRAM, an external bus interface reads and writes data in synchronization with the clock signal, and enables high-speed data transfer. It has become mainstream.
DRAMs use capacitors to store and hold data. Since the charge of the capacitor decreases with the passage of time, the DRAM must periodically perform recharging called refresh in order to correctly store data. The DRAM performs refresh by a circuit built therein, which is called self-refresh. In this self-refresh, energy is saved because data is retained only by supplying power to the DRAM.
On the other hand, with respect to the control device of the SDRAM, conventionally, a means for setting the self-refresh mode and a means for releasing the self-refresh mode after the setting are provided, and a CPU (Central Processing Unit: center) is used when setting and releasing the self-refresh mode. In some cases, DMA transfer of data can be performed quickly without the intervention of a processing device (see, for example, Patent Document 1).
[0003]
[Patent Document 1]
JP-A-2001-202777 (pages 1-3)
[0004]
[Problems to be solved by the invention]
However, in a DDR (Double Data Rate) SDRAM, read access is not possible for 200 clocks after self-refresh is released, so that neither a read request nor a write request can be immediately responded after self-refresh is released. Therefore, the speed of the DMA transfer when returning from the energy saving mode may be reduced.
[0005]
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to quickly perform a DMA transfer when returning from an energy saving mode in a memory control device that controls reading and writing of a DDR SDRAM.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a memory control device for controlling data read / write of a storage device composed of a plurality of memory cells, comprising one or more read DMA controllers for performing DMA transfer of read data; One or more write DMA controllers for DMA transfer of write data, a self-refresh control unit for outputting a request signal for setting and releasing self-refresh, and the read DMA controller, write DMA controller, and self-refresh control unit And a memory arbiter for performing arbitration for a request from the memory controller, wherein a next address to be accessed next time is output from the read DMA controller and input to the memory arbiter.
Further, the present invention is a memory control device for controlling data read / write of a storage device including a plurality of memory cells, and one or more read DMA controllers for DMA transfer of read data, and DMA transfer of write data. One or more write DMA controllers, a self-refresh control unit that outputs a request signal for setting and releasing self-refresh, and an arbitration for requests from the read DMA controller, the write DMA controller, and the self-refresh control unit. A memory control device for outputting a start address from the read DMA controller, inputting the start address to the memory arbiter, and calculating a next address to be accessed next by the memory arbiter.
In any of the above memory control devices, the memory arbiter may switch the memory cells to be subjected to the self-refresh according to the next address.
Also, the memory arbiter does not execute the self-refresh for the one or more memory cells indicated by the next address, but executes the self-refresh for the memory cells other than the memory cells. It is good to output a signal.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing an internal configuration of a memory control device 1 and a memory unit 10 according to the present invention.
The memory control device 1 includes a memory control unit 2, a memory arbiter 3, first and second read DMA controllers (Read DMAC) 4, 5, first and second write DMA controllers (Write DMAC) 6, 7 and a self-refresh control unit 8.
The memory control unit 2 is a circuit that receives a request from the memory arbiter 3, exchanges data to be read / written with the memory unit 10, and executes a self-refresh according to a self-refresh execution request described later. The memory arbiter 3 receives request signals REQ from the first and second read DMA controllers 4 and 5, the first and second write DMA controllers 6 and 7, and the self-refresh control unit 8, respectively. Arbitration is performed for the request, and when the request is accepted, a response signal (ACK) is output to the circuit that has output the corresponding request signal. Here, arbitration means that when there are a plurality of request signals REQ, they are arbitrated to satisfy each request. Further, the memory arbiter 3 switches the memory cells to be subjected to the self-refresh according to the next address described later.
[0008]
The first and second read DMA controllers 4 and 5 are activated upon receiving a data read request from a circuit (not shown), output a read request signal REQ to the memory arbiter 3, receive the read data, and receive the read data. This is a circuit that performs a DMA transfer to a circuit that does not. In addition, the first and second read DMA controllers 4 and 5 each input an address at which the next read access is to be performed during startup (hereinafter, this address is referred to as “next address (NextADDR)”) to the memory arbiter 3. The first and second write DMA controllers 6 and 7 receive a data write request from a circuit (not shown) and output a write request signal REQ to the memory arbiter 3, and receive data to be written and send DMA (Direct) to a circuit (not shown). Memory Access).
The self-refresh control unit 8 outputs a request signal REQ for setting and canceling the self-refresh to the memory arbiter 3, and receives a response signal (ACK) and inputs a status signal for setting and canceling the self-refresh.
[0009]
The memory unit 10 is constituted by a DDR SDRAM, and has a plurality of memory cells (CS0, CS1, CS2, CS3, CS4) arranged therein. In the memory unit 10, self-refresh is performed for each memory cell in accordance with the control of the memory arbiter 3.
Next, the operation of the memory control device 1 and the memory unit 10 configured as described above will be described with reference to the flowchart of FIG. In FIG. 3 and FIG. 4 described later, the step is abbreviated as S.
The memory control device 1 operates in response to an instruction from a circuit (not shown), proceeds to step 1, and inputs a request signal REQ for setting or canceling self-refresh from the self-refresh control unit 8 to the memory arbiter 3. I do. The memory arbiter 3 performs arbitration for this request, and outputs a response signal (ACK) to the self-refresh control unit 8 when accepting the request. Upon receiving the response signal (ACK), the self-refresh control unit 8 inputs a status signal for setting or canceling the self-refresh to the memory arbiter 3. In parallel with the operation of the self-refresh control unit 8, the next address (Next ADDR) is input to the memory arbiter 3 while the first or second read DMA controller 4, 5 is being activated.
[0010]
In step 2, the next address (Next ADDR) of the active first and second read DMA controllers 4 and 5 to which the memory arbiter 3 has been input is read. In the following step 3, the memory arbiter 3 stores the memory cell to be read (target memory cell) represented by the next address (Next ADDR) read in step 2 and the other memory cells (non-target memory cells). Determine. For example, if the target memory cell is CS0, CS1 to CS4 are determined to be non-target memory cells. In the following step 4, the memory arbiter 3 sends a self-refresh execution request signal to the memory control unit so that the self-refresh is executed only for the non-target memory cells determined in step 3 (CS1 to CS4 in the above case). Output to 2. Then, in the subsequent step 5, the memory control unit 2 executes the self-refresh only for the non-target memory cells (CS1 to CS4) which have received the self-refresh execution request in the step 4 in the memory unit 10.
[0011]
The memory unit 10 constituted by the DDR SDRAM cannot perform read access for 200 clocks after the self-refresh is released. However, the memory control device 1 sets the energy saving mode so that the memory arbiter 3 issues a self-refresh execution request. The self-refresh is not executed for the target memory cell (for example, CS0) indicated by the next address of the first and second read DMA controllers 4 and 5 held by the memory arbiter 3, and other than that. , Self-refresh is executed only for non-target memory cells (for example, CS1 to CS4). In this case, since the self-refresh is performed only for the non-target memory cells that are not scheduled to be accessed next time, it is possible to provide a memory cell that can immediately respond to both the read request and the write request even after the self-refresh is released. DMA transfer when returning from the energy saving mode can be performed quickly.
[0012]
FIG. 2 is a block diagram showing the internal configuration of the memory control device 11 and the memory unit 10 according to the present invention. The memory control device 11 is different from the memory control device 1 in that the memory arbiter 3 and the first and second read DMA controllers 4 and 5 respectively include a memory arbiter 13, a first and second read DMA controller 14. , 15 and the others have the same configuration.
The memory arbiter 13 incorporates therein a reception counter 13a and a next address calculation circuit 13b corresponding to the first and second read DMA controllers 14 and 15, respectively. The next time you know the address. The reception counter 13a measures a count value for calculating a next address (Next ADDR). The next address calculation circuit 13b calculates the next address (Next ADDR) based on the count value measured by the reception counter 13a and the start addresses input from the first and second read DMA controllers 14 and 15.
The first and second read DMA controllers 14 and 15 differ in that a start address (Start ADDR) is input to the memory arbiter 13 instead of the next address (Next ADDR), and the other configurations have the same configuration.
[0013]
Next, the operation of the memory control device 11 and the memory unit 10 configured as described above will be described with reference to the flowchart of FIG.
After starting the operation, the memory control device 11 proceeds to step 11 and inputs a request signal REQ for setting or canceling the self-refresh from the self-refresh control unit 8 to the memory arbiter 13, and the memory arbiter 13 accepts the request. In this case, a response signal (ACK) is output to the self-refresh control unit 8. Upon receiving the response signal (ACK), the self-refresh control unit 8 inputs a status signal for setting or canceling the self-refresh to the memory arbiter 13. In parallel with the operation of the self-refresh control unit 8, the first or second read DMA controller 14, 15 inputs a start address (Start ADDR) to the memory arbiter 13 during startup.
[0014]
Then, when the process proceeds to step 12, the memory arbiter 13 reads the start addresses (Start ADDR) of the active first and second read DMA controllers 14 and 15 to which the data has been input. In the following step 13, the next address calculation circuit 13b calculates the next address (Next ADDR) from the count value measured by the reception counter 13a and the read start address (Start ADDR). Then, the process proceeds to a step 14, wherein the memory arbiter 13 determines whether the memory cell to be read (target memory cell) represented by the next address (Next ADDR) calculated in the step 13 and the other memory cells (non-target memory) Is determined. For example, if the target memory cells are CS1 and CS2, CS0, CS3, and CS4 are determined as non-target memory cells. In the following step 15, the memory arbiter 13 sends a self-refresh execution request signal to the memory cells so that the self-refresh is executed only for the non-target memory cells (CS0, CS3, CS4 in the above case) determined in step 14. Output to the control unit 2. Then, in the subsequent step 16, the memory control unit 2 executes the self-refresh only for the non-target memory cells (CS0, CS3, CS4) that have received the self-refresh execution request in step 15 in the memory unit 10.
[0015]
As described above, when the memory arbiter 13 issues a self-refresh execution request similarly to the memory controller 1, the memory control device 11 sets the target memory cell (CS1, CS2) represented by the next address calculated by the memory arbiter 13. ) Is not executed, and the self-refresh is executed only for the other non-target memory cells (CS0, CS3, CS4). In this case, since the self-refresh is performed only for the non-target memory cells that are not scheduled to be accessed next time, it is possible to provide a memory cell that can immediately respond to both the read request and the write request even after the self-refresh is released. It is possible to quickly perform the DMA transfer when returning from the energy saving mode.
[0016]
【The invention's effect】
As described above, according to the present invention, the DDR SDRAM memory control device can quickly perform the DMA transfer when returning from the energy saving mode.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an internal configuration of a memory control device and a memory unit according to the present invention.
FIG. 2 is a block diagram showing another memory control device according to the present invention and an internal configuration of a memory unit.
FIG. 3 is a flowchart illustrating a self-refresh control procedure performed by the memory control device illustrated in FIG. 1;
FIG. 4 is a flowchart showing a control procedure of a self-refresh by the memory control device shown in FIG. 2;
[Explanation of symbols]
1, 11: memory controller 2: memory controller 3, 13: memory arbiter 4, 5: first and second read DMA controllers 6, 7: first and second write DMA controllers 8: self refresh controller 10: memory units 14, 15: first and second read DMA controllers

Claims (4)

A memory control device for controlling data read / write of a storage device including a plurality of memory cells,
One or more read DMA controllers for DMA transferring read data,
One or more write DMA controllers for DMA transfer of write data;
A self-refresh control unit that outputs a request signal for setting and canceling the self-refresh,
A memory arbiter that performs arbitration for requests from the read DMA controller, the write DMA controller and the self-refresh control unit,
A memory control device, wherein a next address to be accessed next is output from the read DMA controller and input to the memory arbiter. A memory control device for controlling data read / write of a storage device including a plurality of memory cells,
One or more read DMA controllers for DMA transferring read data,
One or more write DMA controllers for DMA transfer of write data;
A self-refresh control unit that outputs a request signal for setting and canceling the self-refresh,
A memory arbiter that performs arbitration for requests from the read DMA controller, the write DMA controller and the self-refresh control unit,
A memory control device, wherein a start address is output from the read DMA controller and input to the memory arbiter, and the next address to be accessed next time is calculated by the memory arbiter. The memory control device according to claim 1 or 2,
A memory control device, wherein the memory arbiter switches the memory cells to be subjected to self-refresh according to the next address. The memory control device according to any one of claims 1 to 3,
A self-refresh execution request signal for performing a self-refresh on memory cells other than the one or more memory cells indicated by the next address without performing a self-refresh on the one or more memory cells indicated by the next address Output from the memory control device.

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