JP2009266286A - Semiconductor memory and memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To always perform memory access with optimum timing by matching an operation state of a semiconductor memory with an operation state of a memory controller. <P>SOLUTION: The semiconductor memory transmits a first read-out strobe signal used for taking-in of first read-out data to the memory controller based on read-out request from the memory controller. The semiconductor memory outputs a second read-out strobe signal used for taking-in of second read-out data to the memory controller based on a read-out strobe signal output from the memory controller based on the first read-out strobe signal. The read-out data can be output from the memory to the memory controller always with optimum timing by transferring the strobe signal for each output of read-out data between the semiconductor memory and the memory controller. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory and a memory controller that accesses the semiconductor memory.

  In general, semiconductor memories are classified into a clock asynchronous type such as EDO-DRAM and a clock synchronous type such as SDRAM. Since the clock asynchronous type memory operates the data input / output circuit in accordance with the worst operation timing of the internal circuit, the access time is slow and the data transfer rate is low. A clock synchronous type memory has a high data transfer rate but a large charge / discharge current of a circuit operating in synchronization with a clock signal. In particular, power consumption increases when a semiconductor memory operates at a high frequency. Further, the clock synchronous type semiconductor memory generates electromagnetic radiation noise (EMI). When the access operation time of the internal circuit is longer than a predetermined clock cycle time, the semiconductor memory needs to be removed as a defective product.

On the other hand, there has been proposed a handshake type semiconductor memory that transmits the end of memory access to a controller as a ready signal (see, for example, Patent Document 1).
JP-T-2002-526848

  However, in the above-described handshake type semiconductor memory, the memory access operation is executed in synchronization with the clock signal. For this reason, power consumption increases and electromagnetic radiation noise is also generated.

  An object of the present invention is to always execute memory access at an optimal timing in accordance with the operation state of the semiconductor memory and the operation state of the memory controller that accesses the semiconductor memory. In particular, the memory access is always executed at the optimum timing without increasing the power consumption of the semiconductor memory.

  The semiconductor memory reads or writes data based on an access request from the memory controller. The semiconductor memory transmits a first read strobe signal used for taking in the first read data to the memory controller based on a read request from the memory controller. The semiconductor memory outputs a second read strobe signal used for taking in the second read data to the memory controller based on the read strobe signal output from the memory controller based on the first read strobe signal. The first and second read strobe signals are output to the memory controller according to the operating state of the semiconductor memory. The read strobe signal is output to the memory according to the operation state of the memory controller.

  By transmitting and receiving a strobe signal between the semiconductor memory and the memory controller every time read data is output, the read data can be always output from the memory to the memory controller at an optimal timing. That is, the memory access can always be executed at the optimum timing according to the operation states of the memory and the memory controller. Since the strobe signal generated corresponding to the read data is used without using the clock signal, the memory access can always be executed at the optimum timing without increasing the power consumption of the semiconductor memory.

  Hereinafter, embodiments will be described with reference to the drawings. In the figure, a plurality of signal lines indicated by bold lines are shown. Some of the blocks to which the thick lines are connected are a plurality of circuits. The same reference numerals as the signal names are used for signal lines through which signals are transmitted. A signal with “Z” at the end indicates positive logic. A signal preceded by “/” indicates negative logic. Double square marks in the figure indicate external terminals. The external terminal is, for example, a pad on a semiconductor chip or a lead of a package in which the semiconductor chip is stored. For the signal supplied via the external terminal, the same symbol as the terminal name is used.

  FIG. 1 shows an example of a system SYS in one embodiment. For example, the system SYS is a portable device (such as a portable game device or a cellular phone). The system SYS includes a semiconductor memory MEM, a memory controller MCNT that accesses the semiconductor memory MEM, and a microcontroller MPU that controls the memory controller MCNT. The memory controller MCNT is connected to the microcontroller MPU via the system bus SBUS. The microcontroller MPU and the memory controller MCNT are formed on one semiconductor substrate as a system-on-chip SOC, for example. Note that the function of the memory controller MCNT may be realized by an MPU.

  Some circuits of the memory controller MCNT (interface circuit of the memory MEM) operate with the power supply voltage VDD. The remaining circuits of the memory controller MCNT and the microcontroller MPU operate with the power supply voltage VDDE. For example, the voltage VDD is higher than the voltage VDDE.

  The memory MEM is, for example, a pseudo SRAM type FCRAM (Fast Cycle RAM). The pseudo SRAM has a DRAM memory cell (dynamic memory cell) and an SRAM interface. The memory MEM reads or writes data based on an access request from the memory controller MCNT. The memory MEM may be designed as a semiconductor memory device enclosed in a package, or may be designed as a memory macro (IP) mounted on a system LSI or the like. The memory MEM is connected to the memory controller MCNT via the memory bus MBUS. Details of each signal of the memory bus MBUS will be described with reference to FIG.

  FIG. 2 shows an example of the memory MEM shown in FIG. The memory MEM includes an address latch 10, a command decoder 12, a state machine 14, a bus controller 16, and a memory core 18. A triangular mark in the drawing indicates the buffer circuit BUF. Although not specifically shown, the memory MEM periodically performs a refresh operation, a refresh timer that periodically generates an internal refresh request, and a refresh address counter that generates a refresh address signal indicating a memory cell to be refreshed Etc.

  The address latch 10 latches the address signal ADD in synchronization with the latch signal LTZ and outputs it as a latch address signal LADD. Address signal ADD includes a row address signal supplied to row decoder RDEC and a column address signal supplied to column decoder CDEC. The row address signal and the column address signal are simultaneously supplied to different address terminals ADD. That is, the memory MEM is an address non-multiplex type.

  The command decoder 12 latches and decodes the command signal CMD in synchronization with the latch signal LTZ, and activates the read control signal RDZ or the write control signal WRZ according to the decoding result. For example, the command signal CMD includes a write enable signal / WE and an output enable signal / OE. The read control signal RDZ or the write control signal WRZ is deactivated in synchronization with the precharge signal PREZ.

  The state machine 14 controls the access operation (read access operation or write access operation) of the memory core 18 in response to the access request signal REQ (read command or write command). Specifically, when the access operation is possible, the state machine 14 activates the permission signal ACK to low level in response to activation of the access request signal REQ to low level. The falling edge of the access request signal REQ indicates an access request. The falling edge of the permission signal ACK indicates permission of the access operation.

  When the access operation is possible, the state machine 14 outputs a control signal CNT for accessing the memory core 18 in response to the deactivation of the access request signal REQ to a high level. The rising edge of the access request signal REQ indicates an access start notification from the memory controller MCNT to the memory MEM. The state machine 14 outputs a precharge signal PREZ in synchronization with the last burst clock signal LBCLKZ. As will be described later, the last burst clock signal LBCLKZ is output in synchronization with the final burst clock signal BCLKZ to indicate the end of the access operation. The state machine 14 deactivates the permission signal ACK to a high level in response to the precharge signal PREZ. The rising edge of the permission signal ACK indicates an access end notification from the memory MEM to the memory controller MCNT. Further, the low level period of the permission signal ACK indicates the access operation period of the memory MEM.

  In response to the access request signal REQ, the memory MEM can start an access operation after receiving an access start notification after receiving an access request from the memory controller MCNT. As a result, the memory MEM can secure a margin time from the access request to the start of the access operation, and can reliably receive the address signal ADD and the like. On the other hand, the permission signal ACK allows the memory MEM to delay the start of the access operation after receiving the access request signal REQ. For example, the access operation cycle can be prevented from colliding by delaying the output of the permission signal ACK when the access request signal REQ is received during the end processing of the immediately preceding access operation cycle (such as precharge operation). The memory controller MCNT can also delay the rising edge timing of the access request signal REQ according to the operation state of the internal circuit. As described above, the memory controller MCNT can access the memory MEM according to its own operation state and the operation state of the memory MEM by the access request signal REQ and the permission signal ACK, and the memory MEM corresponds to the operation state of the internal circuit. The access operation can be started.

  The control signal CNT includes a bit reset signal BRSZ, a bit control signal BTZ, a word control signal WLZ, a sense amplifier control signal LEZ, a column control signal CLZ, a precharge control signal PREZ, a read amplifier control signal RAEZ, and a write amplifier control signal WAEZ. . The bit reset signal BRSZ is a timing signal indicating a period during which the bit lines BL and / BL are precharged. The bit control signal BTZ is a timing signal for controlling the connection switch BT. The word control signal WLZ is a timing signal for activating the word line WL. The sense amplifier control signal LEZ is a timing signal for activating the sense amplifier SA. The column control signal CLZ is a timing signal for turning on the column switch CSW. The precharge control signal PREZ is a timing signal for starting the precharge of the bit lines BL and / BL and is a signal indicating the end of the access operation. The read amplifier control signal RAEZ is a timing signal for activating the read amplifier RA. The write amplifier control signal WAEZ is a timing signal for activating the write amplifier WA.

  The bus controller 16 outputs the read data output from the memory core 18 via the data bus DB to the data terminal DQ during the read access operation, and the write data supplied to the data terminal DQ during the write access operation. The data is output to the memory core 18 via the data bus DB. The output timing of the read data changes according to the read data transfer request signal RDATA, the read data transfer enable signal WDATA, the read strobe transfer request signal RDQS, and the read strobe transfer enable signal WDQS. The write data latch timing changes according to the write data transfer permission signal RDATA, the write data transfer request signal WDATA, the write strobe transfer permission signal RDQS, and the write strobe transfer request signal WDQS. As described above, the signals RDATA, WDATA, RDQS, and WDQS have a meaning of a request signal or a permission signal depending on the read access operation and the write access operation. Details of the state machine 14 and the bus controller 16 are shown in FIG.

  The memory core 18 is arranged between a plurality of memory blocks RBLK (RBLK0-1), a row decoder RDEC corresponding to each memory block RBLK, a sense amplifier area SAA arranged between the memory blocks RBLK, and a row decoder RDEC. A sense amplifier control unit SCNT, a column decoder CDEC, a read amplifier RA, and a write amplifier WA are provided. Note that the number of memory blocks RBLK may be four, eight, sixteen or the like (2 to the power of n; n is an integer of 2 or more) or one. When there is one memory block RBLK, the bit switch BT is not necessary.

  Each memory block RBLK0-1 is arranged in a plurality of dynamic memory cells MC arranged in a matrix, a plurality of word lines WL connected to a column of memory cells MC arranged in the horizontal direction in the figure, and arranged in the vertical direction in the figure. It has a plurality of bit lines BL, / BL connected to the column of memory cells MC. Memory cell MC includes a capacitor for holding data as electric charge and a transfer transistor for connecting one end of the capacitor to bit line BL (or / BL). The other end of the capacitor is connected to a reference voltage line. The reference voltage supplied to the reference voltage line is, for example, the same as the precharge voltage VPR (FIG. 7) and is generated by an internal voltage generation circuit (not shown).

  The sense amplifier area SAA includes a precharge circuit PRE and a connection switch BT corresponding to each memory block RBLK0-1, and a sense amplifier SA and a column switch CSW shared by the memory blocks RBLK0-1. The sense amplifier control unit SCNT generates a core control signal for controlling operations of the precharge circuit PRE, the connection switch BT, the sense amplifier SA, and the column switch CSW in response to the control signal CNT.

  The row decoder RDEC decodes an address signal LADD (row address signal) in order to select one of the word lines WL. The column decoder CDEC decodes an address signal LADD (column address signal) in order to select a bit line pair BL, / BL corresponding to the number of bits of the data terminal DQ or an integer multiple of the number. The read amplifier RA amplifies complementary read data output via the column switch CSW during a read operation. The write amplifier WA amplifies complementary write data supplied via the data bus DB during a write operation, and supplies the amplified write data to the bit line pair BL, / BL.

  FIG. 3 shows an example of the state machine 14 and the bus controller 16 shown in FIG. The operations of the state machine 14 and the bus controller 16 are shown in FIGS. The state machine 14 includes an edge detection circuit EGDET and signal generation circuits ACKGEN, BRSGEN, WLGEN, LEGEN, CLGEN, RAGEN, WAGEN, and PREGEN.

  The edge detection circuit EGDET generates the latch signal LTZ in synchronization with the rising edge of the request signal REQ. The signal generation circuit ACKGEN sets the permission signal ACK to a low level in response to the falling edge of the request signal REQ, and sets the permission signal ACK to a high level in response to the rising edge of the bit reset signal BRSZ.

  The signal generation circuit BRSGEN generates the bit reset signal BRSZ and the bit control signal BTZ in synchronization with the rising edge of the request signal REQ. The signal generation circuit WLGEN activates the word line control signal WLZ in synchronization with the bit reset signal BRSZ, and deactivates the word line control signal WLZ in synchronization with the precharge control signal PREZ. The signal generation circuit LEGEN generates a sense amplifier control signal LEZ in response to the word line control signal WLZ. The signal generation circuit CLGEN generates a column control signal CLZ in response to the sense amplifier control signal LEZ.

  The signal generation circuit RAGEN generates the read amplifier control signal RAEZ in response to the sense amplifier control signal LEZ during the read access operation (RDZ = high level). The signal generation circuit WAGEN generates the write amplifier control signal WAEZ in response to the sense amplifier control signal LEZ during the write access operation (WRZ = high level). The signal generation circuit PREGEN generates a precharge signal PREZ in synchronization with the last burst clock signal LBCLKZ.

  The bus controller 16 includes signal generation circuits RDATAGEN, RDSGEN, BCLKGEN, a data output control circuit DOUTCNT, and a data input control circuit DINCNT.

  During the read access operation, the signal generation circuit RDATAGEN inverts the logical level of the read data transfer request signal RDATA in response to activation of the column control signal CLZ, and then reads in response to the read strobe transfer enable signal WDQS. The logic level of data transfer request signal RDATA is inverted. The read strobe transfer permission signal WDQS indicates the completion of reception of read data by the memory controller MCNT and also indicates the transfer permission of the next read data. The read data transfer request signal RDATA indicates the output start timing of the read data output from the memory MEM.

  The signal generation circuit RDATAGEN inverts the logic level of the write data transfer permission signal RDATA in response to the write data transfer request signal WDATA during the write access operation. The write data transfer request signal WDATA indicates the output start timing of write data from the memory controller MCNT. The write data transfer permission signal RDATA indicates that write data can be accepted.

  The signal generation circuit RDSGEN inverts the logic level of the read strobe transfer request signal RDQS (read strobe signal) in response to the read data transfer permission signal WDATA during the read access operation. The read data transfer permission signal WDATA indicates that data can be received by the memory controller MCNT. The read strobe transfer request signal RDQS indicates the read data fetch timing to the memory controller MCNT.

  The signal generation circuit RDSGEN inverts the logic level of the write strobe transfer permission signal RDQS in response to the write strobe transfer request signal WDQS during the write access operation. The write strobe transfer request signal WDQS indicates the timing for accepting write data to the memory MEM and also indicates the next write data transfer request. The write strobe transfer permission signal RDQS indicates completion of acceptance of write data and permission for transfer of the next write data.

  The signal generation circuit BCLKGEN activates the first burst clock signal BCLKZ (any one of BCLK0Z-BCLK3Z) in response to the column control signal CLZ during the read access operation. The signal generation circuit BCLKGEN activates the burst clock signal BCLKZ (any one of the remaining BCLK0Z to BCLK3Z) in response to the read strobe transfer permission signal WDQS during the read access operation. The signal generation circuit BCLKGEN inactivates the burst clock signal BCLKZ in response to the read strobe transfer request signal RDQS.

  The signal generation circuit BCLKGEN activates the burst clock signal BCLKZ in response to the write strobe transfer request signal WDQS during the write access operation. The signal generation circuit BCLKGEN inactivates the burst clock signal BCLKZ in response to the write data transfer permission signal RDATA during the write access operation. However, the deactivation of the last burst clock signal BCLKZ in the burst access operation is performed a predetermined time after the activation of the burst clock signal BCLKZ. In the burst access operation, a plurality of data signals are continuously input or output in response to one access request REQ.

  In this embodiment, the maximum value of the burst length is “4”, and the signal generation circuit BCLKGEN generates a maximum of four burst clock signals BCLK0Z-BCLK3Z. The burst length is the number of times of output of a data signal output from the data terminal DQ in response to one read command and the number of input of a data signal received at the data terminal DQ in response to one write command. The burst length is set by a mode register (not shown) or a configuration register (not shown) in the memory MEM. When changing the burst length, the memory controller MCNT supplies a mode register setting command to the memory MEM and rewrites the value of the mode register. Burst clock signals BCLK0-3Z are output in the order corresponding to the column address signal. For example, when the burst length is set to “2”, two burst clock signals BCLKZ are sequentially output according to the column address signal. When the maximum burst length is “8”, a maximum of eight burst clock signals BCLK0Z-BCLK7Z are generated. Also in the embodiments described later, the maximum burst length may be “8” instead of “4”.

  During the read access operation, the data output control circuit DOUTCNT selects any of the parallel read data groups (sub data buses) on the data bus DB in synchronization with the burst clock signals BCLK0Z-3Z, and the selected read data The group is transferred to the output data line DOUT. The data input control circuit DINCNT has a latch circuit (not shown) corresponding to the parallel data group on the data bus DB. During the write access operation, the data input control circuit DINCNT latches the write data on the input data line DIN in the corresponding latch circuit in synchronization with the burst clock signals BCLK0Z-3Z, and the latched write data is transferred to the data bus DB. To the corresponding sub data bus. In this embodiment, the number of bits of data transmitted to the data bus DB is four times the number of bits of the data terminal DQ.

  FIG. 4 shows an example of the memory controller MCNT shown in FIG. The memory controller MCNT includes signal generation circuits ADDGEN, CMDGEN, REQGEN, WDATAGEN, WDQSGEN, a data control circuit DTCNT, and an access control circuit ACCNT.

  The signal generation circuits ADDGEN and CMDGEN generate an address signal ADD and a command signal CMD in response to an access request AREQ from a memory master such as an MPU. The signal generation circuit REQGEN changes the access request signal REQ to a low level in response to the access request AREQ, and changes the access request signal REQ to a high level in response to the permission signal ACK from the memory MEM. For example, the access request AREQ includes read access operation / write access operation identification information, address information, data transfer number information, write data information, and the like.

  The signal generation circuit WDATAGEN generates the read data transfer permission signal WDATA in response to the read data transfer request signal RDATA during the read access operation. During the write access operation, the signal generation circuit WDATAGEN generates the first write data transfer request signal WDATA in response to the write control signal WRCNT, and the next write data transfer request signal WDATA in response to the write strobe transfer enable signal RDQS. Is generated.

  The signal generation circuit WDQSGEN generates the read strobe transfer permission signal WDQS in response to the read strobe transfer request signal RDQS during the read access operation. The signal generation circuit WDQSGEN generates the write strobe transfer request signal WDQS in response to the write data transfer permission signal RDATA during the write access operation.

  During the read access operation, the data control circuit DTCNT latches the read data DQ read from the memory MEM in synchronization with the read strobe transfer request signal RDQS and outputs it as read data RDT. During the write access operation, the data control circuit DTCNT outputs the write data WDT supplied from the memory master such as MPU to the data terminal DQ of the memory MEM in synchronization with the write data transfer request signal WDATA.

  The access control circuit ACCNT outputs the read control signal RDCNT or the write control signal WRCNT in response to the permission signal ACK from the memory MEM. The read control signal RDCNT is generated to execute a read access operation of the memory MEM. The write control signal WRCNT is generated to execute a write access operation of the memory MEM. The signal generation circuit WDATAGEN, the signal generation circuit WDQSGEN, and the data control circuit DTCNT recognize the read access operation and the write access operation according to the read control signal RDCNT and the write control signal WRCNT.

  FIG. 5 shows a state transition of the memory MEM shown in FIG. The solid line in the figure indicates that the state changes based on the trigger of the signal. A broken line in the figure indicates that the state automatically changes. A downward arrow attached to the signal indicates a falling edge. An upward arrow attached to the signal indicates a rising edge.

  The memory MEM holds the standby state until it receives the access request signal REQ (FIG. 5A). The memory MEM transitions from the standby state to the access permission state in response to the falling edge of the access request signal REQ, and changes the permission signal ACK to a low level (FIG. 5B). In the access permission state, when the memory MEM detects the rising edge of the access request signal REQ, the memory MEM shifts to the access start state, latches the address signal ADD, and decodes the command signal CMD (FIG. 5C).

  When the command signal CMD indicates the read command RD, the memory MEM transitions to the read data transfer request state and inverts the logic level of the read data transfer request signal RDATA (FIG. 5 (d)). In the read data transfer request state, when the memory MEM detects the transition edge of the read data transfer permission signal WDATA, the memory MEM shifts to the read strobe transfer request state and inverts the logic level of the read strobe transfer request signal RDQS (FIG. 5 (e)). )). In the read strobe transfer supply state, when the memory MEM detects the transition edge of the read strobe transfer permission signal WDQS, the memory MEM again shifts to the read data transfer request state. However, when the memory MEM detects a transition edge of the final read strobe transfer permission signal WDQS, the memory MEM shifts to a reset state and resets the read data transfer request signal RDATA and the read strobe transfer request signal RDQS to a high level (FIG. 5). (F)). Thereafter, the memory MEM transitions to the access end notification state (FIG. 5 (g)), changes the permission signal ACK to high level, and then returns to the standby state.

  On the other hand, when the command signal CMD indicates the write command WR, when the memory MEM detects the transition edge of the write data transfer request signal WDATA, the memory MEM transitions from the access start state to the write data transfer enable state, and the write data transfer enable signal RDATA The logic level is inverted (FIG. 5 (h)). In the write data transfer permission state, when the memory MEM detects the transition edge of the write strobe transfer request signal WDQS, the memory MEM shifts to the write data latch state and latches the write data from the memory controller MCNT (FIG. 5 (i)). . Thereafter, the memory MEM transitions to the write strobe transfer enable state, and inverts the logic level of the write strobe transfer enable signal RDQS (FIG. 5 (j)). In the write strobe transfer enabled state, when the memory MEM detects the transition edge of the next write data transfer request signal WDATA, the memory MEM again shifts to the write data transfer enabled state. However, when the logic level of the final write strobe transfer enable signal RDQS is inverted, the memory MEM transitions to a reset state and resets the write data transfer enable signal RDATA and the write strobe transfer enable signal RDQS to a high level (FIG. 5). (K)). Thereafter, the memory MEM transitions to the access end notification state (FIG. 5 (l)), changes the permission signal ACK to a high level, and then returns to the standby state. In addition, you may return to a standby state, without providing a reset state (FIG. 5 (f, k)).

  FIG. 6 shows a state transition of the memory controller MCNT shown in FIG. Notations such as solid lines and broken lines are the same as those in FIG. The memory controller MCNT holds the standby state until it receives the access request AREQ from the memory master (FIG. 6 (a)). In response to the access request AREQ, the memory controller MCNT transitions from the standby state to the access request state, and changes the access request signal REQ to a low level (FIG. 6B). In the access request state, when the memory controller MCNT detects the falling edge of the permission signal ACK, the memory controller MCNT transitions to the access start request state and changes the access request signal REQ to a high level (FIG. 6C).

  When the access request AREQ indicates the read access request RD, when the memory controller MCNT detects the transition edge of the read data transfer request signal RDATA, the memory controller MCNT shifts to the read data transfer enable state and inverts the logic level of the read data transfer enable signal WDATA. (FIG. 6D). In the read data transfer enabled state, when the memory controller MCNT detects the transition edge of the read strobe transfer request signal RDQS, the memory controller MCNT shifts to the read data latch state and latches the read data from the memory MEM (FIG. 6 (e)). Thereafter, the memory controller MCNT transits to the read strobe transfer enable state, and inverts the logic level of the read strobe transfer enable signal WDQS (FIG. 6 (f)). When the memory controller MCNT detects the transition edge of the next read data transfer request signal RDATA in the read strobe transfer enabled state, the memory controller MCNT transitions again to the read data transfer enabled state. However, when the logic level of the final read strobe transfer enable signal WDQS is inverted, the memory controller MCNT transitions to a reset state and resets the read data transfer enable signal WDATA and the read strobe transfer enable signal WDQS to a high level (FIG. 6 (g)). Thereafter, the memory controller MCNT returns to the standby state.

  On the other hand, when the access request AREQ indicates the write access request WR, the memory controller MCNT transitions from the access start request state to the write data transfer request state, inverts the logic level of the write data transfer request signal WDATA, and stores the write data in the memory It outputs to MEM (FIG.6 (h)). In the write data transfer request state, when the memory controller MCNT detects the transition edge of the write data transfer permission signal RDATA, the memory controller MCNT shifts to the write strobe transfer request state and inverts the logic level of the write strobe transfer request signal WDQS (FIG. 6 ( i)). In the write strobe transfer request state, when the memory controller MCNT detects the transition edge of the write strobe transfer permission signal RDQS, the memory controller MCNT transitions again to the write data transfer request state. However, when the memory controller MCNT detects the transition edge of the final write strobe transfer enable signal RDQS, the memory controller MCNT shifts to the reset state and resets the write data transfer request signal WDATA and the write strobe transfer request signal WDQS to a high level (FIG. 6 (j)). Thereafter, the memory controller MCNT returns to the standby state. As shown in FIGS. 5 and 6, the memory MEM and the memory controller MCNT perform handshake control using signals RDATA, WDATA, RDQS, and WDQS, and execute a read access operation and a write access operation.

  FIG. 7 shows details of the sense amplifier area SAA shown in FIG. The figure shows, for example, a part of the sense amplifier area SAA corresponding to one data terminal DQ. When the memory MEM has a 16-bit data terminal DQ, the sense amplifier area SAA in FIG. 7 is formed for each data terminal DQ. The sense amplifier area SAA includes a precharge circuit PRE and a connection switch BT corresponding to each memory block RBLK0-1, and a sense amplifier SA and a column switch CSW shared by the memory blocks RBLK0-1.

  The precharge control signal BRS (BRS0-1) for controlling the precharge circuit PRE is changed to a low level in synchronization with the deactivation of the bit reset signal BRSZ, and is set to a high level in synchronization with the activation of the bit reset signal BRSZ. To change. In the memory block RBLK that is not accessed, the high-level precharge control signal BRS is supplied to the precharge circuit PRE.

  The connection switch BT selectively connects the bit line pair BL, / BL of each memory block RBLK0-1 to the bit line SBL, / SBL of the sense amplifier SA. The connection switch BT corresponding to the memory block RLBK to be accessed receives the bit control signal BT (BT0-1) that changes to a high level during the high level period of the bit control signal BTZ.

  Each column switch CSW is turned on when the column selection signal CL (CL0-2) is at a high level, and connects the sense amplifier SA and the bit line pair BL, / BL to the local data lines LDQ, / LDQ. Column selection signals CL0-2 are generated during a high level period of the column control signal CLZ. The sense amplifier activation signals PSA and NSA for controlling the sense amplifier SA change to a high level and a low level, respectively, during the high level period of the sense amplifier control signal LEZ.

  In each memory block RBLK0-1, the memory cell MC is connected to the word line WL and the bit line BL or / BL. The word line WL selected by the row address signal changes to a high level during the high level period of the word control signal WLZ. The sense amplifier area SAA has the same configuration as a general DRAM.

  FIG. 8 shows an example of the read access operation of the memory MEM shown in FIG. Detailed descriptions of the operations described in FIGS. 3 to 6 are omitted. In this example, the burst length BL1 is set to “4”. “IN” and “OUT” attached to the signals RDATA, WDATA, RDQS, and WDQS indicate an input signal to the memory MEM and an output signal from the memory MEM, respectively.

  First, the memory controller MCNT outputs the address signal ADD and the command signal CMD (read command RD) in synchronization with the falling edge of the access request signal REQ (FIG. 8A). The read command RD is recognized by a high level (H) write enable signal / WE and a low level (L) output enable signal / OE.

  The memory MEM changes the permission signal ACK to a low level in response to the falling edge of the request signal REQ (FIG. 8B). The falling edge of the permission signal ACK can be delayed according to the operation state of the memory MEM. The memory MEM generates the latch signal LTZ in synchronization with the rising edge of the request signal REQ. The rising edge of the request signal REQ can be delayed according to the operation status of the memory controller MCNT. The memory controller MCNT holds the address signal ADD and the command signal CMD for a predetermined time from the rising edge of the request signal REQ.

  The memory MEM latches the address signal ADD and the command signal CMD in synchronization with the latch signal LTZ, activates the read control signal RDZ, and starts a read access operation (FIG. 8 (c)). Address signal ADD and command signal CMD are latched in synchronization with request signal REQ. For this reason, the low level period of the request signal REQ can be used as the setup time of the signals ADD and CMD, and the signals ADD and CMD can be reliably latched.

  Thereafter, a bit reset signal BRSZ, a bit control signal BTZ, and a word control signal WLZ are sequentially generated, and data is read from the memory cell MC to the bit line BL (or / BL) (FIG. 8 (d)). Note that the output timing of the read data D0 to D3 is variable according to the signals RDATA, WDATA, RDQS, and WDQS. For this reason, the time from the rising edge of the request signal REQ to the start of the read access operation can be extended according to the operation state of the memory MEM.

  The sense amplifier control signal LEZ is activated and the voltage difference between the bit lines BL and / BL is amplified (FIG. 8 (e)). The column control signal CLZ and the read amplifier control signal RAEZ are activated in response to the sense amplifier control signal LEZ, and the read data read to the bit lines BL and / BL is output from the read amplifier RA to the data bus DB. (FIG. 8F). The column selection signal CL (column control signal CLZ) may be deactivated after the read data is latched by the read amplifier RA. Further, the column selection signal CL (column control signal CLZ) may be activated for each read data, similarly to the burst clock signal BCLKZ.

  Next, the first burst clock signal BCLKZ (any one of BCLK0 to 3Z) is activated in synchronization with the column control signal CLZ (FIG. 8 (g)), and the first read data D0 is output to the data terminal DQ. (FIG. 8 (h)). Although the burst clock signals BCLK0-3Z are shown as one signal in the figure, the burst clock signals BCLK0-3Z are actually transmitted to independent signal lines. The logical level of the read data transfer request signal RDATA is inverted in synchronization with the column control signal CLZ (FIG. 8 (i)). The read data transfer request signal RDATA is a signal for requesting transfer of read data to the memory controller MCNT. The circuit in the memory MEM continuously operates without interruption from the activation of the read control signal RDZ to the change in the logic level of the read data transfer request signal RDATA.

  The memory controller MCNT changes the logic level of the read data transfer permission signal WDATA in response to the transition edge of the read data transfer request signal RDATA (FIG. 8 (j)). The read data transfer permission signal WDATA is a signal indicating that the memory controller MCNT is ready to take in the read data, and is a signal for permitting transfer of the read data from the memory MEM. The output timing of the transition edge of the read data transfer permission signal WDATA can be delayed according to the operation status of the memory controller MCNT. The memory MEM changes the logic level of the read strobe transfer request signal RDQS in response to the transition edge of the read data transfer permission signal WDATA (FIG. 8 (k)). The output timing of the transition edge of the read strobe transfer request signal RDQS can be delayed according to the operation state of the memory MEM. The memory controller MCNT takes in the read data D0 in synchronization with the transition edge of the read strobe transfer request signal RDQS. The burst clock signal BCLKZ is deactivated after a predetermined time from the transition edge of the read strobe transfer request signal RDQS (FIG. 8 (l)). The read data to the data terminal DQ is held (latched) during the read data output period (approximately equal to the activation period of the column control signal CLZ). Therefore, the read data D0 is held until the next burst clock signal BCLKZ is activated (FIG. 8 (m)).

  The memory controller MCNT changes the logical level of the read strobe transfer permission signal WDQS in response to the transition edge of the read strobe transfer request signal RDQS (FIG. 8 (n)). The output timing of the transition edge of the read strobe transfer permission signal WDQS can be delayed according to the operation status of the memory controller MCNT. Due to the change in the logical level of the read strobe transfer permission signal WDQS, the transfer of the first read data from the memory MEM to the memory controller MCNT is completed.

  Next, in response to the transition edge of the read strobe transfer enable signal WDQS, the memory MEM activates the next burst clock signal BCLKZ and changes the logic level of the next read data transfer request signal RDATA (FIG. 8 (o)). P)). The output timing of the transition edge of the read data transfer request signal RDATA can be delayed according to the operation status of the memory MEM. Thereafter, the above-described operation is repeated, and the read data D1-D3 is transferred to the memory controller MCNT. The transition edge of the second read strobe transfer request signal RDQS is generated based on the transition edge of the first read strobe transfer request signal RDQS. In this example, the transfer cycles DCYCL1 of the read data D0-D3 are equal to each other. However, the transfer cycle DCYCL1 changes according to the operation status of the memory MEM and the memory controller MCNT.

  The precharge signal PREZ is activated in synchronization with the falling edge of the last burst clock signal LBCLKZ, and as described with reference to FIG. 3, the word line control signal WLZ, the sense amplifier control signal LEZ, the column control signal CLZ, and the read amplifier control. The signal RAEZ signal, the bit reset signal BRSZ, and the bit control signal BTZ change sequentially (FIG. 8 (q)). Then, the bit lines BL and / BL are precharged, and the burst read access operation in response to the access request signal REQ is completed. The memory MEM changes the permission signal ACK to a high level in synchronization with the deactivation of the precharge control signal PREZ, and deactivates the read control signal RDZ (FIG. 8 (r)).

  FIG. 9 shows an example of the write access operation of the memory MEM shown in FIG. Detailed descriptions of the operations described in FIGS. 3 to 6 and the same operations as those in FIG. 8 are omitted. In this example, the burst length BL1 is set to “4”. The waveforms from the access request signal REQ to the sense amplifier activation signal PSA (sense amplifier control signal LEZ) are almost the same except that the command signal CMD (write command WR) is different.

  The memory MEM latches the address signal ADD and the command signal CMD in synchronization with the latch signal LTZ, activates the write control signal WRZ, and starts a write access operation (FIG. 9A). The memory controller MCNT changes the logic level of the write data transfer request signal WDATA after a predetermined time T1 from the rising edge of the request signal REQ, and outputs the write data D0 to the memory MEM (FIG. 9 (b, c)). The write data transfer request signal WDATA is a signal for requesting transfer of write data to the memory MEM.

  For example, the predetermined time T1 is set to a time from when the memory MEM starts an access operation until the data signal on the bit lines BL and / BL is amplified. However, the write data transfer request signal WDATA may be output immediately in synchronization with the request signal REQ. At this time, a normal write access operation can be executed by delaying the output of the write data transfer permission signal RDATA by the memory MEM. Therefore, the output timing of the transition edge of the write data transfer request signal WDATA can be set according to the operation status of the memory controller MCNT.

  The memory MEM changes the logic level of the write data transfer permission signal RDATA in response to the transition edge of the write data transfer request signal WDATA (FIG. 9 (d)). The output timing of the transition edge of the write data transfer permission signal RDATA can be delayed according to the operation state of the memory MEM. The write data transfer permission signal RDATA is a signal for permitting transfer of write data from the memory controller MCNT. The memory controller MCNT changes the logic level of the write strobe transfer request signal WDQS in response to the transition edge of the write data transfer permission signal RDATA (FIG. 9 (e)). The output timing of the transition edge of the write strobe transfer request signal WDQS can be delayed according to the operation status of the memory controller MCNT. The memory MEM activates the burst clock signal BCLKZ (any one of BCLK0 to 3Z) in synchronization with the transition edge of the write strobe transfer request signal WDQS (FIG. 9 (f)). Thus, the write data D0 supplied to the data terminal DQ is transferred to the data bus DB (FIG. 9 (g)). That is, the memory MEM takes in the write data D0 in synchronization with the transition edge of the write strobe transfer request signal WDQS. Since the column selection signal CL (column control signal CLZ) is activated, the write data is transmitted to the bit lines BL and / BL (FIG. 9 (h)). Note that the column selection signal CL (column control signal CLZ) may be activated every time write data is input, like the burst clock signal BCLKZ. At this time, the second and subsequent column control signals CLZ are activated in synchronization with the transition edge of the write strobe transfer request signal WDQS.

  The memory MEM changes the logic level of the write strobe transfer enable signal RDQS in response to the transition edge of the write strobe transfer request signal WDQS (FIG. 9 (i)). The output timing of the transition edge of the write strobe transfer enable signal RDQS can be delayed according to the operation state of the memory MEM. Due to the change in the logic level of the write strobe transfer permission signal RDQS, the transfer of the first write data from the memory controller MCNT to the memory MEM is completed.

  The memory controller MCNT changes the logic level of the next write data transfer request signal WDATA in response to the transition edge of the write strobe transfer enable signal RDQS (FIG. 9 (j)). The output timing of the transition edge of the write data transfer request signal WDATA can be delayed according to the operation status of the memory controller MCNT. The memory MEM changes the logic level of the write data transfer permission signal RDATA in response to the transition edge of the write data transfer request signal WDATA, and deactivates the burst clock signal BCLKZ (FIG. 9 (k, l)). Thereby, the writing of the first write data D0 to the memory cell MC is completed.

  Thereafter, the above-described operation is repeated, and write data D1-D3 is written into the memory cell MC. For example, the write data D1 is taken into the memory MEM in synchronization with the second transition edge of the write strobe transfer request signal WDQS. In this example, the transfer cycles DCYCL1 of the write data D0-D3 are equal to each other. However, the transfer cycle DCYCL1 changes according to the operation status of the memory MEM and the memory controller MCNT.

  Then, the precharge signal PREZ is activated in synchronization with the falling edge of the last burst clock signal LBCLKZ, and the precharge operation of the bit lines BL and / BL is executed (FIG. 9 (m)). The memory MEM changes the permission signal ACK to a high level in synchronization with the deactivation of the precharge control signal PREZ, and deactivates the write control signal WRZ (FIG. 9 (n)).

  FIG. 10 shows a comparison of read access operations of the memory MEM and the DDR-SDRAM of FIG. Generally, semiconductor devices have different electrical characteristics for each chip, each wafer, or each manufacturing lot. For example, in the memory MEM, the memory operation period MOP (minimum value) from when the read command RD is received until the read data is output is different for each chip (Chip-A, Chip-B, Chip-C). In this embodiment, not only the access request signal REQ and the permission signal ACK but also the signals RDATA, WDATA, RDQS, and WDQS are used, and handshake control is repeated between the memory MEM and the memory controller MCNT every time read data is output. Thereby, read data can be output in the minimum data cycle corresponding to the memory operation period MOP of each chip. As a result, all the memory chips including Chip-C having a long memory operation period MOP caused by a change in manufacturing conditions can be shipped as non-defective products. The long memory operation period MOP also occurs due to power supply noise or the like.

  On the other hand, in a general DDR-SDRAM, the number of clock cycles (read latency RL) for outputting the first read data D0 is determined based on the worst operation of the internal circuit. For this reason, Chip-D and Chip-E having a memory operation period MOP shorter than the read latency RL cause a useless waiting time WAIT. Further, Chip-F in which the output of the first read data D0 exceeds the read latency RL is treated as a defective product. As described above, in the memory MEM of this embodiment, it is possible to prevent the yield from being lowered even if the manufacturing conditions are changed.

  As described above, in this embodiment, handshake control is performed between the memory MEM and the memory controller MCNT for each output of read data or each input of write data using the signals RDATA, WDATA, RDQS, and WDQS. As a result, the memory access operation can always be executed at the shortest or optimum timing according to the operation state of the memory MEM and the operation state of the memory controller MCNT. In particular, since the memory MEM and the memory controller MCNT are mounted on different semiconductor chips, the manufacturing conditions are different from each other and the electrical characteristics are different from each other. Even in such a case, the memory access operation can always be executed at the optimum timing according to the performance of the memory MEM and the performance of the memory controller MCNT. In addition, the memory access operation can always be executed at an optimum timing even when there is at least one of a change in manufacturing conditions, a change in power supply voltages VDD and VDDE, and a change in temperature. Further, since the data transfer is controlled using the strobe signals RDQS, WDQS, etc. without using the clock signal, the memory access operation can always be executed at the optimum timing without increasing the power consumption of the memory MEM.

  FIG. 11 shows an example of the state machine 14A and the bus controller 16A of the semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory MEM is a pseudo SRAM type FCRAM as in FIG. When the memory MEM receives an access request signal REQ (interrupt request) supplied during an access operation (ACK = low level), the memory MEM interrupts the access operation being executed and executes an access operation in response to the interrupt request. It has a function. Details of the interrupt function are shown in FIGS. The configuration excluding the state machine 14A and the bus controller 16A is the same as the memory MEM in FIG. As shown in FIG. 1, the memory MEM is mounted in the system SYS together with the MPU and the memory controller MCNT.

  The signal generation circuit ACKGEN of the state machine 14A outputs a forced end signal FENDZ when it detects a falling edge of the access request signal REQ during the low level of the permission signal ACK. Further, when the permission signal ACK changes to the high level during the low level period of the access request signal REQ, the signal generation circuit ACKGEN returns the permission signal ACK that has changed to the high level again to the low level. Other functions of the signal generation circuit ACKGEN are the same as those of the signal generation circuit ACKGEN in FIG. The state machine 14A has an OR circuit OR for supplying the last burst clock signal LBCLKZ or the reset signal RSTZ to the input of the signal generation circuit PREGEN. Other functions of the state machine 14A are the same as those of the state machine 14 of FIG.

  The signal generation circuit RDSGEN of the bus controller 16A has an edge detection circuit EGDET. The edge detection circuit EGDET outputs a reset signal RSTZ in synchronization with the transition edge of the read strobe transfer request signal RDQS (or the write strobe transfer enable signal RDQS) when detecting the rising edge of the forced end signal FENDZ. The signal generation circuit RDSGEN resets the read strobe transfer request signal RDQS (or the write strobe transfer enable signal RDQS) to a high level in synchronization with the reset signal RSTZ. Other functions of the signal generation circuit RDSGEN are the same as those of the signal generation circuit RDSGEN in FIG. The signal generation circuit RDATAGEN resets the read data transfer request signal RDATA (or the write data transfer permission signal RDATA) to a high level in synchronization with the reset signal RSTZ. Other functions of the signal generation circuit RDATAGEN are the same as those of the signal generation circuit RDATAGEN in FIG.

  FIG. 12 shows an example of state transition of the memory MEM shown in FIG. 11 and the memory controller MCNT that accesses the memory MEM. Notations such as solid lines and broken lines are the same as those in FIG. When the memory MEM is executing an access operation (ACK = low level) and the memory controller MCNT causes the memory MEM to execute another access operation, the memory controller MCNT transitions to an interrupt request state and issues an interrupt request (REQ = low level). Issue (FIG. 12A).

  When receiving an interrupt request during the access operation, the memory MEM transitions from the access state (ACK = low level) to the access forced end state, and changes the permission signal ACK to high level (FIG. 12B). Here, the access state includes the states (d), (e), (h), (i), and (j) shown in FIG. The memory MEM automatically transitions from the access forced end state to the reset state, and resets the signals RDATA and RDQS to a high level (FIG. 12C). Thereafter, the memory MEM shifts to the access permission state shown in FIG.

  On the other hand, when the rising edge of the permission signal ACK is detected, the memory controller MCNT transitions to a reset state and resets the signals WDATA and WDQS to a high level (FIG. 12 (d)). Thereafter, when the memory controller MCNT detects the falling edge of the permission signal ACK, the memory controller MCNT transits to the access start request state of FIG.

  FIG. 13 shows an example of the interrupt access operation of the memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 8 are omitted. In this example, the memory controller MCNT outputs the access request signal REQ (interrupt request) while the memory MEM is outputting the third read data D2 (ACK = low level) (FIG. 13A). The memory controller MCNT outputs the address signal ADD and the command signal CMD (read command RD) together with the interrupt request REQ to the memory MEM (FIG. 13B).

  In response to the interrupt request REQ, the memory MEM outputs a forced end signal FENDZ, and outputs a reset signal RSTZ in synchronization with the read strobe transfer request signal RDQS (FIG. 13 (c, d)). The memory MEM resets the read data transfer request signal RDATA and the read strobe transfer request signal RDQS to high level in synchronization with the rising edge of the reset signal RSTZ (FIG. 13 (e, f)). That is, the read data transfer request signal RDATA and the read strobe transfer request signal RDQS are reset based on the interrupt request REQ.

  A precharge control signal PREZ is output in synchronization with the reset signal RSTZ, and the read access operation is interrupted (FIG. 13 (g)). The memory controller MCNT receives the read data in synchronization with the read strobe transfer request signal RDQS. Therefore, by interrupting the read access operation in synchronization with the read strobe transfer request signal RDQS, the memory controller MCNT can reliably receive the read data D2. Note that the memory MEM can delay interruption of the read access operation only by delaying the transition edge timing of the read strobe transfer request signal RDQS.

  The memory MEM temporarily changes the permission signal ACK to high level in response to the completion of the read access operation (FIG. 13 (h)). The memory controller MCNT resets the read data transfer permission signal WDATA and the read strobe transfer permission signal WDQS to high level in synchronization with the rising edge of the permission signal ACK (FIG. 13 (i, j)). That is, the read data transfer permission signal WDATA and the read strobe transfer permission signal WDQS are reset based on the interrupt request REQ. The memory controller MCNT changes the access request signal REQ to a high level in synchronization with the falling edge of the permission signal ACK (FIG. 13 (k)). Similarly to FIG. 8, the memory MEM starts the read access operation in synchronization with the rising edge of the access request signal REQ. That is, an access read operation corresponding to the interrupt request REQ is started.

  FIG. 14 shows another example of the interrupt access operation of the memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 8 and 13 are omitted. In this example, an interrupt request REQ (write command WR) is supplied instead of the interrupt request REQ (read command RD) of FIG. 13, and a write access operation is executed (FIGS. 14A and 14B). The write access operation is the same as in FIG. Other operations are the same as those in FIG.

  FIG. 15 shows another example of the interrupt access operation of the memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 9 and 13 are omitted. In this example, an interrupt request REQ is generated during a write access operation. Specifically, the memory controller MCNT outputs the access request signal REQ (interrupt request) while outputting the third write data D2 (ACK = low level) (FIG. 15A). Further, the memory controller MCNT outputs an address signal ADD and a read command RD together with the interrupt request REQ to the memory MEM (FIG. 15 (b)). The interruption operation of the write access operation in response to the interrupt request REQ is the same as the interruption operation of the read access operation of FIG. As in FIG. 13, the memory MEM can delay the interruption of the write access operation only by delaying the transition edge timing of the write strobe transfer permission signal RDQS.

  Also in the write access operation, the reset signal RSTZ is output in synchronization with the transition edge of the write strobe transfer enable signal RDQS (FIG. 15 (c)). Then, in synchronization with the reset signal RSTZ, the write data transfer permission signal RDATA and the write strobe transfer permission signal RDQS are reset to a high level (FIG. 15 (d, e)). The write data transfer request signal WDATA and the write strobe transfer request signal WDQS are reset to a high level in synchronization with the rising edge of the permission signal ACK (FIG. 15 (f, g)).

  The memory MEM generates a burst clock signal BCLKZ (any one of BCLK0 to 3Z) in synchronization with the write strobe transfer request signal WDQS, and writes the write data to the memory cell MC. Write strobe transfer permission signal RDQS is generated in response to write strobe transfer request signal WDQS. Therefore, by interrupting the write access operation in synchronization with the write strobe transfer permission signal RDQS, the memory MEM can reliably receive the write data D2 and can reliably write to the memory cell MC. The read access operation started in response to the interrupt request REQ is the same as in FIG.

  FIG. 16 shows another example of the access operation of the memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIGS. 9, 13, 14, and 15 are omitted. In this example, an interrupt request REQ (write command WR) is supplied instead of the interrupt request REQ (read command RD) in FIG. 15, and a write access operation is executed (FIGS. 16A and 16B). Other operations are the same as those in FIG.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, even in the memory MEM having the interrupt function of the access request REQ, the memory access operation can always be executed at the optimum timing according to the operation state of the memory MEM and the operation state of the memory controller MCNT. In particular, since handshake control is performed for each data output or each input, a memory access operation can always be executed at an optimal timing without malfunction even if an interrupt request REQ is generated at any timing.

  FIG. 17 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory MEM of this embodiment has a command decoder 12B and a bus controller 16B instead of the command decoder 12 and the bus controller 16 of FIG. The memory MEM has a mode register 20B. Other configurations are the same as those in FIG. The memory MEM is a pseudo SRAM type FCRAM as in FIG. As shown in FIG. 1, the memory MEM is mounted in the system SYS together with the MPU and the memory controller MCNT.

  The command decoder 12B activates the mode register setting signal MRSZ when receiving the mode register setting command. For example, the mode register setting command is generated in response to the low level write enable signal / WE and the low level output enable signal / OE when the access request signal REQ is at a high level. Other functions of the command decoder 12B are the same as those of the command decoder 12 of FIG. Note that the command decoder 12B may generate the mode register setting signal MRSZ when receiving a predetermined combination of a read command and a write command together with a predetermined address signal ADD.

  Mode register 20B has a plurality of registers set in accordance with the value of latch address signal LADD received in synchronization with mode register setting signal MRSZ. Specifically, the mode register 20B has a burst register for setting the burst length BL1 and a plurality of delay registers for adjusting the delay time of the variable delay circuit in the bus controller 16B. Each delay register outputs a delay control signal DLYCNT1-2 in accordance with the set value. That is, the delay control signal DLYCNT1-2 is set by the memory controller MCNT accessing the mode register based on the instruction from the MPU shown in FIG. The mode register 20B is also referred to as a configuration register. In addition to the functions described with reference to FIGS. 2 and 3, the bus controller 16B has a function of adjusting the output timing of the signals RDATA and RDQS according to the delay control signal DLYCNT1-2.

  FIG. 18 shows an example of the state machine 14 and the bus controller 16B shown in FIG. The state machine 14 is the same as in FIG. The bus controller 16B is different from FIG. 3 in signal generation circuits RDATAGEN and RDSGEN. Other configurations are the same as those in FIG.

  The signal generation circuit RDATAGEN has a variable delay circuit DLY1 whose delay time is changed according to the delay control signal DLYCNT1. The variable delay circuit DLY1 adjusts the time from when receiving the transition edge of the read strobe transfer enable signal WDQS to when changing the logic level of the read data transfer request signal RDATA during the read access operation. In addition, the variable delay circuit DLY1 adjusts the time from the transition of the write data transfer request signal WDATA to the change of the logical level of the read data transfer request signal RDATA during the write access operation.

  The signal generation circuit RDSGEN includes a variable delay circuit DLY2 whose delay time is changed according to the delay control signal DLYCNT2. The variable delay circuit DLY2 adjusts the time from when receiving the transition edge of the read data transfer permission signal WDATA to changing the logic level of the read strobe transfer request signal RDQS during the read access operation. In addition, the variable delay circuit DLY2 adjusts the time from the reception of the transition edge of the write strobe transfer request signal WDQS to the change of the logic level of the read strobe transfer request signal RDQS during the write access operation. Other functions of the signal generation circuits RDATAGEN and RDSGEN are the same as those in FIG.

  FIG. 19 shows an example of a memory controller MCNT that accesses the memory MEM shown in FIG. The memory controller MCNT is different from that shown in FIG. 4 in signal generation circuits WDATAGEN and WDQSGEN. Other configurations are the same as those in FIG.

  The signal generation circuit WDATAGEN has a variable delay circuit DLY3 whose delay time is changed according to the delay control signal DLYCNT3. The variable delay circuit DLY3 adjusts the time from the transition of the read data transfer request signal RDATA to the change of the logical level of the read data transfer permission signal WDATA during the read access operation. In addition, the variable delay circuit DLY3 adjusts the time from the transition edge of the write strobe transfer permission signal RDQS to the change of the logic level of the write data transfer request signal WDATA during the write access operation.

  The signal generation circuit WDQSGEN has a variable delay circuit DLY4 whose delay time is changed according to the delay control signal DLYCNT4. The variable delay circuit DLY4 adjusts the time from when receiving the transition edge of the read strobe transfer request signal RDQS to when changing the logic level of the read strobe transfer enable signal WDQS during the read access operation. In addition, the variable delay circuit DLY4 adjusts the time from when receiving the transition edge of the write data transfer permission signal RDATA until changing the logic level of the write strobe transfer request signal WDQS during the write access operation. The other functions of the signal generation circuits WDATAGEN and WDQSGEN are the same as those in FIG.

  The delay control signal DLYCNT3-4 is set by the memory controller MCNT based on an instruction from the MPU shown in FIG. The MPU instructs the memory controller MCNT to reduce the delay time of at least one of the variable delay circuits DLY1 to D4 when a high data transfer rate for the memory MEM is required according to the operation status of the system SYS. The MPU instructs the memory controller MCNT to increase the delay time of at least one of the variable delay circuits DLY1-4 when a low data transfer rate is sufficient. For example, a high data transfer rate is set when moving image data is input / output to / from the memory MEM. The low data transfer rate is set when waiting for key input by the user. At a low data transfer rate, the power consumption of the memory MEM can be reduced.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in this embodiment, for example, the power consumption of the memory MEM can be reduced by changing the data transfer rate for the memory MEM in accordance with the operation status of the system SYS. In particular, in this embodiment, by increasing the delay time of at least one of the variable delay circuits DLY1-4, not only can the frequency of the access request REQ be lowered, but also the access operation speed of the memory MEM can be lowered. That is, the memory access operation can always be executed at the optimum timing according to the operation state of the memory MEM and the operation state of the memory controller MCNT. Furthermore, the peak value of the current consumption of the memory MEM can be reduced, and power supply noise and the like can be reduced.

  FIG. 20 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory MEM of this embodiment has a bus controller 16B shown in FIG. 17 instead of the bus controller 16 of FIG. Further, the memory MEM has a delay control terminal DLYCNT1-2 that receives the delay control signal DLYCNT1-2. Other configurations are the same as those in FIG. The memory MEM is a pseudo SRAM type FCRAM as in FIG. As shown in FIG. 1, the memory MEM is mounted in the system SYS together with the MPU and the memory controller MCNT. The memory controller MCNT is the same as that in FIG.

  FIG. 21 shows an example of a read access operation of the memory MEM shown in FIG. Detailed descriptions of the operations described in FIGS. 3 to 6 and the same operations as those in FIG. 8 are omitted. In this example, the MPU changes the value of the delay control signals DLYCNT1-4 in order to increase the delay time of the variable delay circuits DLY1-4 while the memory MEM is outputting the first read data D0 (not shown). ) Thereby, the delay time from the change of the signal RDATA to the change of the signal WDATA, the delay time from the change of the signal WDATA to the change of the signal RDQS, the delay time from the change of the signal RDQS to the change of the signal WDQS, and the change of the signal WDQS To delay the signal RDATA change (FIG. 21 (a, b, c, d)). Since the delay time of the variable delay circuits DLY1-4 increases, the transfer cycle DCYCL2 of the read data D1-D3 becomes longer than the transfer cycle DCYCL1 of the read data.

  Thereby, the power consumption and peak current of the memory MEM can be reduced. In particular, the delay time of the variable delay circuits DLY1-2 can be directly changed via an external terminal without using a mode register or the like. Therefore, the data transfer cycle can be freely changed during the burst access operation. Since there is no need to set the mode register, the power consumption can be adjusted without interrupting the access operation. The same effect as described above can be obtained by increasing the delay time of at least one of the variable delay circuits DLY1-4. Also in the write access operation, the same operation as in FIG. 21 can be realized.

  FIG. 22 shows another example of the read access operation of the memory MEM shown in FIG. Detailed description of the same operation as in FIG. 21 is omitted. In this example, the MPU or the memory controller MCNT executes a processing AP different from the memory access operation after the memory MEM outputs the first read data D0 (FIG. 22A). During the processing AP, the memory controller MCNT cannot receive the read data D1.

  The memory controller MCNT increases the delay time of the variable delay circuit DLY3 shown in FIG. 19 based on an instruction from the MPU. Thereby, the delay time from the change of the signal RDATA to the change of the signal WDATA becomes long (FIG. 22B). During the process AP, the memory MEM continues to output the read data D1 (FIG. 22C). When the processing AP is completed, the memory controller MCNT changes the logic level of the signal WDATA and resumes the held read access operation (FIG. 22D). The transfer cycle DCYCL3 of the read data D1 is significantly longer than the transfer cycle DCYCL1 of the read data D0. Thereafter, the delay time of the variable delay circuit DLY3 is returned to the original value, and the read data D2-3 is transferred as in FIG. 8 (FIG. 23 (e, f)). When the processing AP time is longer, not only the variable delay circuit DLY3 but also the delay time of the variable delay circuit DLY2 may be increased.

  FIG. 23 shows an example of the write access operation of the memory MEM shown in FIG. Detailed descriptions of the operations described in FIGS. 3 to 6 and the same operations as those in FIG. 9 are omitted. In this example, similarly to FIG. 22, the MPU or the memory controller MCNT executes the processing AP different from the memory access operation after the memory MEM writes the first data and outputs the data D0 (FIG. 23 (a)). .

  The memory controller MCNT increases the delay time of the variable delay circuit DLY4 shown in FIG. 19 based on an instruction from the MPU. Thereby, the delay time from the change of the signal RDATA to the change of the signal WDQS becomes longer (FIG. 23B). During the processing AP, the memory controller MCNT continues to output the write data D1 (FIG. 23 (c)). When the processing AP is completed, the memory controller MCNT changes the logic level of the signal WDS and resumes the held write access operation (FIG. 23 (d)). The transfer cycle DCYCL4 of the write data D1 is significantly longer than the transfer cycle DCYCL1 of the write data D0. Thereafter, the delay time of the variable delay circuit DLY4 is returned to the original value, and the write data D2-3 is transferred as in FIG. 8 (FIG. 23 (e, f)). When the processing AP time is longer, not only the variable delay circuit DLY4 but also the delay time of the variable delay circuit DLY2 may be increased.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, the MPU or the memory controller MCNT can execute another processing AP during the burst access operation without interrupting the burst access operation. As a result, the memory access operation can always be executed at the optimum timing in accordance with the operation state of the memory MEM and the operation state of the memory controller MCNT. Furthermore, since the burst access operation does not prevent the start of the processing AP, the performance of the system SYS can be improved.

  FIG. 24 shows an example of a semiconductor memory MEM in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory MEM of this embodiment has a state machine 14C instead of the state machine 14 of FIG. Further, the memory MEM has a refresh control circuit 22C and an address selection circuit 24C. Other configurations are the same as those in FIG. The memory MEM is a pseudo SRAM type FCRAM as in FIG. As shown in FIG. 1, the memory MEM is mounted in the system SYS together with the MPU and the memory controller MCNT. The memory controller MCNT is the same as that in FIG.

  The state machine 14C has a function of prohibiting a low level change of the permission signal ACK during the activation of the refresh signal REFZ indicating the execution of the refresh operation. Other functions of the state machine 14C are the same as those of the state machine 14 of FIG.

  The refresh control circuit 22C has a timer TMR that periodically generates an internal refresh request RREQ and an arbiter ARB that determines the priority order of the internal refresh request RREQ and the external access request signal REQ. The arbiter ARB activates the refresh signal REFZ for a predetermined period when giving priority to the internal refresh request RREQ. The refresh control circuit 22C includes a refresh address generation circuit (not shown) that sequentially generates a refresh address signal RADD indicating the memory cells MC that perform the refresh operation.

  The address selection circuit 24C selects the refresh address signal RADD during the refresh operation, selects the latch row address signal LRAD other than the refresh operation, and outputs the selected signal to the row decoder RDEC.

  FIG. 25 shows an example of the state machine 14C and the bus controller 16 shown in FIG. The bus controller 16 is the same as in FIG. The state machine 14C is different from FIG. 3 in signal generation circuits ACKGEN, BRSGEN, and PREGEN. The signal generation circuit BRSGEN deactivates the bit reset signal BRSZ in synchronization with the activation of the refresh signal REFZ, activates the bit control signal BTZ, and transmits a control signal for activating the word control signal WLZ to the signal generation circuit WLGEN. Output to. Thereby, control signals WLZ, LEZ, CLZ, etc. for executing the refresh operation are sequentially generated.

  When the signal generation circuit ACKGEN detects the falling edge of the access request signal REQ while the refresh signal REFZ is activated, the signal generation circuit ACKGEN prohibits the change of the permission signal ACK to a low level until the refresh signal REFZ is deactivated. To do. Other functions of the signal generation circuit ACKGEN are the same as those in FIG. The signal generation circuit PREGEN activates the precharge control signal PREZ after a predetermined time from the activation of the refresh signal REFZ. Other functions of the signal generation circuit PREGEN are the same as those in FIG.

  FIG. 26 shows an example of the read access operation of the memory MEM shown in FIG. Detailed descriptions of the operations described in FIGS. 3 to 6 and the same operations as those in FIG. 8 are omitted. In this example, before the access request signal REQ changes to a low level, an internal refresh request RREQ is generated, the refresh signal REFZ is activated, and a refresh operation is executed (FIG. 26 (a, b, c)). . The precharge control signal PREZ is activated after a predetermined time from the activation of the refresh signal REFZ, and the refresh operation is completed (FIG. 26 (d)).

  The memory controller MCNT changes the access request signal REQ to high level in response to the permission signal ACK that changes to low level in synchronization with the inactivation of the refresh signal REFZ (FIG. 26 (e)). That is, during the refresh operation, the memory controller MCNT does not receive the falling edge of the permission signal ACK. Thereafter, the burst read access operation is executed as in FIG. As described above, when the internal refresh request RREQ is generated immediately before the access request REQ, the refresh operation is executed before the burst read access operation. Note that when the write command WR is supplied together with the access request signal REQ, the memory MEM operates in the same manner as in FIG.

  FIG. 27 shows another example of the read access operation of the memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 8 are omitted. In this example, after the access request signal REQ changes to a low level, an internal refresh request RREQ is generated (FIG. 27 (a)). Therefore, the burst read access operation is executed in the same manner as in FIG. The refresh control circuit 22C shown in FIG. 24 activates the refresh signal REFZ in synchronization with the inactivation of the read control signal RDZ (FIG. 27 (a)). Then, the refresh operation is executed as in FIG. 26 (FIG. 27C). As described above, when the internal refresh request RREQ occurs during the low level of the access request signal REQ or during execution of the read access operation, the refresh operation is executed after the read access operation. Even when the write command WR is supplied together with the access request signal REQ, the memory MEM operates in the same manner as in FIG.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in this embodiment, when the internal refresh request RREQ and the access request REQ conflict, the memory MEM can operate without malfunction. In particular, when the internal refresh request RREQ is generated, it is possible to easily prevent the internal refresh operation and the read access operation from colliding by delaying the output of the permission signal ACK. That is, the memory controller MCNT can always perform memory access at an optimal timing in accordance with the operation state of the memory MEM.

  FIG. 28 shows an example of a system SYS in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. For example, the system SYS is a portable device (such as a portable game device or a cellular phone). In FIG. 28, elements for realizing the communication function are omitted.

  The system SYS includes a battery BAT, a system controller SCNT, a power controller PWRIC, a microcontroller MPU, a dynamic memory access controller DMAC, a memory controller MCNT, FCNT, a memory MEM, a flash memory FLASH, a USB interface USBIF, a card interface CARDDIF, a liquid crystal controller LCDC, It includes a liquid crystal display device LCD, an input / output interface I / OIF, a speaker SPK, a key input device KEY, and the like. The memory MEM and the memory controller MCNT are the same as those in FIG.

  The MPU, the DMAC, and the memory controllers MCNT and FCNT are configured as a single chip as a system-on-chip SOC. In this example, the system controller SCNT, the power supply controller PWRIC, the memory MEM, the flash memory FLASH, and the liquid crystal controller LCDC are each configured by a single semiconductor chip. Note that at least one of these chips SCNT, PWRIC, MEM, FLASH, and LCDC may be mounted on the SOC. Furthermore, the function of the system controller SCNT may be realized by an MPU.

  The system controller SCNT is connected to the power supply controllers PWRIC and MPU via, for example, a PBUS (Power Management Bus). The system controller SCNT controls the power supply controllers PWRIC and MPU according to the access status of the memory MEM (the operation status of the system SYS or the memory controller MCNT) in order to optimally adjust the data transfer rate and power consumption of the memory MEM. The power supply controller PWRIC receives power from the battery BAT, receives an instruction from the system controller SCNT, supplies the power supply voltage VDDE to the SOC, and supplies the power supply voltage VDD to the memory MEM. The power supply voltages VDDE and VDD are variable. The power supply voltage VDD may be supplied to a part of the memory controller MCNT (an interface circuit of the memory MEM). The power supply controller PWRIC may receive an external power supply from outside the system SYS.

  The power supply voltage VDDE is a power supply voltage for SOC, and MPU, DMAC, MCNT, FCNT, etc. operate with the power supply voltage VDDE. Note that the power supply voltages VDDE and VDD may be supplied to other chips. The power supply controller PWRIC may supply another power supply voltage (not shown) to the liquid crystal controller LCDC, for example.

  The MPU, DMAC, MCNT, FCNT, USBIF, CARDDIF, LCDC, and I / OIF are connected to the system bus SBUS. For example, the MPU controls the overall operation of the system SYS by executing a program held in the memory MEM. For example, the DMAC transfers a program and various parameters stored in the FLASH to the memory MEM when the system SYS is powered on, and transfers various parameters held in the memory MEM to the FLASH when the system SYS is powered off. The memory controller MCNT receives an access request (a write request, a read request, a mode register setting request, etc.) of the memory MEM from the MPU or the DMAC, and accesses the memory MEM. When the memory MEM is a DRAM, the memory controller MCNT outputs a refresh request for executing a refresh operation to the DRAM at a predetermined frequency.

  The memory controller FLASHHC receives a FLASH access request (read request, program request, erase request, etc.) from the MPU or DMAC, and accesses the FLASH. When a device having a USB interface is connected, the USB interface USBIF inputs / outputs data to / from this device. When a device having a card interface is connected, the card interface CARDIF inputs / outputs data to / from this device. The liquid crystal controller LCDC outputs image data supplied via the system bus SBUS to the LCD in order to display an image on the LCD. The image data may be held in the memory MEM or may be held in an image memory (not shown). The input / output interface I / OIF converts, for example, digital audio data into analog and outputs it to the speaker SPK. The input / output interface I / OIF outputs an interrupt for key input to the MPU when it receives key input information from the key input device KEY. The key input device KEY includes, for example, an input button and a touch sensor.

  FIG. 29 shows the performance of the memory MEM mounted in the system SYS shown in FIG. “Performance” in the figure is a data transfer rate or power consumption. The performance of the memory MEM is higher as the data transfer rate is higher. Alternatively, the performance of the memory MEM is higher as the power consumption is lower. In this embodiment, the power supply controller PWRIC shown in FIG. 28 changes the power supply voltage VDD based on an instruction from the system controller SCNT. In other words, this embodiment has a DVS (Dynamic Voltage Scaling) function for changing the power supply voltage VDD in order to dynamically change the performance of the memory MEM.

  When the power supply voltage VDD is low, the operation speed of the internal circuit of the memory MEM is relatively slow. Thereby, the data transfer rate is lowered and the power consumption is reduced. On the other hand, when the power supply voltage VDD is high, the operation speed of the internal circuit of the memory MEM is relatively high. This increases the data transfer rate and increases the power consumption. The performance of the memory MEM automatically changes according to the change of the power supply voltage VDD. Therefore, as shown in the upper side of the figure, the actual performance of the memory MEM can be changed following the required performance of the system SYS indicated by shading.

  The lower side of the figure shows the change in the performance of the semiconductor memory before this embodiment is proposed. In this semiconductor memory, when the power supply voltage VDD is changed, an access request cannot be supplied to the semiconductor memory until the power supply voltage VDD is stabilized. This is to prevent malfunction due to fluctuations in the power supply voltage VDD. For this reason, the actual performance of the semiconductor memory has a time lag with respect to the required performance, as indicated by the broken line. Further, the memory operation cannot follow a fine change in the power supply voltage VDD.

  FIG. 30 shows an example of the read access operation of the memory MEM shown in FIG. Detailed descriptions of the operations described in FIGS. 3 to 6 and the same operations as those in FIG. 8 are omitted. In this example, the power supply voltage VDD gradually decreases under the control of the power supply controller PWRIC shown in FIG. 28 (FIG. 30 (a)). The memory MEM performs a burst read access operation while the power supply voltage VDD is decreasing (FIG. 30B).

  The operation speed of the transistors in the memory MEM decreases as the power supply voltage VDD decreases. Therefore, the delay time from the change of the signal WDATA to the change of the signal RDQS and the delay time from the change of the signal WDQS to the change of the signal RDATA are gradually increased (FIG. 30 (c, d)). The power supply voltage VDDE supplied to the memory controller MCNT does not change. For this reason, the delay time from the change of the signal RDATA to the change of the signal WDATA and the delay time from the change of the signal RDQS to the change of the signal WDQS do not change (FIG. 30 (e, f)). As a result, the transfer cycle DCYCL of the read data D0-3 is gradually increased, and the power consumption of the memory MEM is gradually decreased. In this embodiment, the access operation can be executed during the period ADIS in which the access operation is prohibited in the semiconductor memory shown in the lower side of FIG. Note that the memory MEM can also perform a burst write operation access operation while the power supply voltage VDD is decreasing. Further, the memory MEM can execute a read access operation or a write operation access operation while the power supply voltage VDD is increasing.

  FIG. 31 shows another example of the read access operation of the memory MEM shown in FIG. Detailed descriptions of the same operations as those in FIG. 30 are omitted. In this example, the power supply voltages VDD and VDDE gradually decrease under the control of the power supply controller PWRIC shown in FIG. 28 (FIG. 31A). For this reason, the delay time from the change of the signal RDATA to the change of the signal WDATA and the delay time from the change of the signal RDQS to the change of the signal WDQS gradually increase (FIG. 31 (b, c)). Other operations are the same as those in FIG. That is, the transfer cycle DCYCL of the read data D0-3 is further increased, and the power consumption of the memory MEM is further decreased. Note that the memory MEM can also perform a burst write operation access operation while the power supply voltages VDD and VDDE are lowered. Further, the memory MEM can execute a read access operation or a write operation access operation while the power supply voltages VDD and VDDE are increasing.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, the memory MEM can perform a burst access operation while the power supply voltage VDD is being changed in order to slow down the access operation of the memory MEM. That is, the memory controller MCNT can always perform a burst access operation at an optimal timing according to the operation state of the memory MEM. Furthermore, the burst access operation can always be executed at the optimum timing without increasing the power consumption of the memory MEM.

  FIG. 32 shows an example of a system SYS in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the memory controller MCNT outputs an access request signal REQ0-1, and the memory MEM outputs a permission signal ACK0-1. Other configurations are the same as those in FIG.

  FIG. 33 shows an example of the memory MEM shown in FIG. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory MEM of this embodiment has a state machine 14D instead of the state machine 14 of FIG. Further, the memory core of the memory MEM has two banks BK0-1. Other configurations are the same as those in FIG.

  The state machine 14D receives the access request signals REQ0-1 corresponding to the banks BK0-1 and outputs the permission signals ACK0-1. Further, the state machine 14D outputs the bank selection signals BKSEL0-1 for selecting the banks BK0-1 to the banks BK0-1. The state machine 14D has the signal generation circuits BRSGEN, WLGEN, LEGEN, CLGEN, RAGEN, WAGEN and PREGEN shown in FIG. 3 for each bank BK0-1.

  FIG. 34 shows an example of the read access operation of the memory MEM shown in FIG. Detailed descriptions of the operations described in FIGS. 3 to 6 and the same operations as those in FIG. 8 are omitted. In this example, the read access operation of the bank BK0 is started in response to the falling edge of the access request signal REQ0 (FIG. 34 (a, b)).

  When the first read data D0 is output, the access request signal REQ1, the address signal ADD, and the command signal CMD for the bank BK1 are output (FIG. 34 (c)). Similarly to FIG. 8, the memory MEM changes the permission signal ACK1 to the low level in response to the falling edge of the access request signal REQ1 (FIG. 34 (d)). The memory controller MCNT changes the access request signal REQ1 to high level in synchronization with the falling edge of the permission signal ACK1 (FIG. 34 (e)).

  The memory MEM latches the address signal ADD and the command signal CMD in synchronization with the rising edge of the access request signal REQ1, and starts the read access operation of the bank BK1 (FIG. 34 (f)). At this time, control signals BRSZ, BTZ, WLZ, LEZ (not shown) are sequentially output. Since the control signal CLZ is not activated, the data D4-D7 read to the bit lines BL, / BL of the bank BK1 are not output to the data bus DB. Further, the memory MEM changes the permission signal ACK1 to the high level again to indicate that the read data from the bank BK1 cannot be output (FIG. 34 (g)).

  When the read access operation of the bank BK0 is completed and the permission signal ACK0 changes to high level, the state machine 14D changes the permission signal ACK1 to low level (FIG. 34 (h)). The state machine 14D activates the control signal CLZ corresponding to the bank BK1 in synchronization with the falling edge of the permission signal ACK1 in order to output the read data D4-D7 to the data bus DB. Thereafter, similarly to FIG. 8, the transfer cycle DCYCL1 of the read data D4-D7 of the bank BK1 is sequentially executed (FIG. 34 (i)).

  FIG. 35 shows an example of the write access operation of the memory MEM shown in FIG. Detailed descriptions of the operations described in FIGS. 3 to 6 and the same operations as those in FIGS. 9 and 34 are omitted. Also in the write access operation, the access operation of the bank BK1 is started during the access operation of the bank BK0 (FIG. 35 (a)). The memory controller MCNT changes the signal WDATA to a low level in response to the falling edge of the permission signal ACK1 (FIG. 35 (b)). However, when the permission signal ACK1 changes to a high level after the access request REQ, the memory controller MCNT immediately changes the signal WDATA to a low level in synchronization with the falling edge of the permission signal ACK1. Similarly to FIG. 9, write data D4-D7 for the bank BK1 are sequentially output (FIG. 35 (c)).

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, even when the memory MEM has a plurality of banks BK0-1, a burst access operation can always be executed at an optimal timing.

  FIG. 36 shows an example of a system SYS in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, an address data signal line ADQ is provided instead of the address signal line ADD and the data signal line DQ in FIG. That is, in this embodiment, the address signal ADD and the data signal DQ are transmitted to the memory MEM using a common signal line. Other configurations are the same as those in FIG. The memory MEM is a pseudo SRAM type FCRAM as in FIG.

  FIG. 37 shows an example of the read access operation of the memory MEM shown in FIG. 8 is the same as FIG. 8 except that the address signal ADD is transmitted to the address data signal line ADQ.

  FIG. 38 shows an example of the write access operation of the memory MEM shown in FIG. 9 is the same as that of FIG. 9 except that the address signal ADD is transmitted to the address data signal line ADQ.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in this embodiment, even in the memory MEM in which the address signal ADD and the data signal DQ are transmitted to the common signal line ADQ, the timing is always optimal in accordance with the operation state of the memory MEM and the operation state of the memory controller MCNT. A memory access operation can be executed.

  FIG. 39 shows an example of a system SYS in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, the signal RDATA and the signal RDQS from the memory MEM are transmitted to the common signal line RDQS / RDATA. The signal WDATA and the signal WDQS from the memory controller MCNT are transmitted to the common signal line WDQS / WDATA. Other configurations are the same as those in FIG. The memory MEM is a pseudo SRAM type FCRAM as in FIG.

  FIG. 40 shows an example of the read access operation of the memory MEM shown in FIG. In this embodiment, the rising edge of the signal RDQS / RDATA indicates the transition edge of the signal RDQS. The falling edge of signal RDQS / RDATA indicates the transition edge of signal RDATA. Similarly, the rising edge of the signal WDQS / WDATA indicates the transition edge of the signal WDQS. The falling edge of the signal WDQS / WDATA indicates the transition edge of the signal WDATA. Other operations are the same as those in FIG.

  FIG. 41 shows an example of the write access operation of the memory MEM shown in FIG. The meanings of signal RDQS / RDATA and signal WDQS / WDATA are the same as those in FIG. Operations other than the signals RDQS / RDATA and WDQS / WDATA are the same as those in FIG.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, even when the signal RDQS / RDATA is transmitted to the common signal line and the signal WDQS / WDATA is transmitted to the common signal line, the burst access operation can always be executed at the optimum timing.

  FIG. 42 shows an example of a system SYS in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The memory MEM has a function of outputting an error signal ERRZ when it is determined that the read data is invalid.

  The determination of read data is executed by, for example, an error detection circuit (such as an ECC circuit) provided in the memory MEM. The error detection circuit detects that the read data and the write data have changed to values different from the expected values due to voltage fluctuations or noise. At this time, the error signal ERRZ is activated. Alternatively, the error signal ERRZ is output when the refresh request is generated during the read operation and the read data and the write data cannot be guaranteed because the read operation is interrupted. The memory controller MCNT has a function of recognizing that the read data is invalid when receiving the error signal ERRZ. Other configurations are the same as those in FIG. The memory MEM is a pseudo SRAM type FCRAM as in FIG.

  FIG. 43 shows an example of the read access operation of the memory MEM shown in FIG. Detailed descriptions of the operations described in FIGS. 3 to 6 and the same operations as those in FIG. 8 are omitted. When the memory MEM outputs the second read data D2, the memory MEM detects that the read data D2 is invalid, and activates the error signal ERRZ to a high level (FIG. 43 (a)). The memory controller MCNT treats the shaded read data D2-D3 received during the activation of the error signal ERRZ as invalid data (FIG. 43 (b, c)). Note that the memory MEM outputs the read data D0-D3 by the number corresponding to the burst length BL1, regardless of whether there is an error. Thereafter, the memory controller MCNT outputs an access request signal REQ again (not shown) in order to receive correct read data D2-D3. Note that the memory MEM also outputs the error signal ERRZ in the write access operation as in FIG.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, in this embodiment, even when the memory MEM has an error signal terminal ERRZ for notifying an error of read data and write data, the burst access operation can always be executed at an optimal timing.

  FIG. 44 shows an example of the read access operation of the memory MEM in another embodiment. Detailed descriptions of the operations described in FIGS. 3 to 6 and the same operations as those in FIG. 8 are omitted. In this embodiment, the enable signal ACK changes to a high level during the read access operation, thereby indicating that the read data D2-D3 is invalid (FIG. 44 (a)). Similarly, in the write access operation, when the permission signal ACK changes to a high level, it indicates that invalid write data has been written into the memory cell MC.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, in this embodiment, even in the memory MEM in which the logic of the error signal ERRZ is included in the permission signal ACK, the burst access operation can always be executed at the optimum timing.

  In the above-described embodiment, the example applied to the pseudo SRAM type FCRAM has been described. However, for example, the above-described embodiment may be applied to a DRAM, SRAM, ferroelectric memory, or the like. The above-described embodiment is desirably applied to a semiconductor memory having a data burst transfer function. However, even when applied to a semiconductor memory that inputs and outputs data for each access request REQ, the same effects as described above can be obtained. it can.

  In the above-described embodiment, the example applied to the memory MEM of the address non-multiplex type has been described. However, for example, the embodiment described above may be applied to an address multiplex type semiconductor memory that sequentially receives a row address signal and a column address signal at a common terminal.

  In the embodiment shown in FIG. 17 and FIG. 20, even if either the variable delay circuit DLY1-2 (MEM) or the variable delay circuit DLY3-4 (MCNT) is deleted, the same effect as those of these embodiments can be obtained. Can do.

  Control of the performance of the memory MEM shown in FIG. 29 can also be realized by using at least one of the memory MEM shown in FIG. 20 and the memory controller MCNT shown in FIG. Specifically, the memory controller MCNT may control the delay control signal DLYCNT1-2 or the delay control signal DLYCNT3-4 according to a data transfer rate or power consumption request from the system SYS. As a result, as shown in FIGS. 21 to 23, the read data transfer cycle and the write data transfer cycle can be freely and quickly changed without changing the power supply voltage VDD.

  A plurality of banks BK0-1 may be formed in the memory MEM of the embodiments of FIGS. 17, 20, 24, 28, 36, 39, and 42. Further, the number of banks BK may be two or more.

The following additional notes are further disclosed with respect to the embodiment shown in FIGS.
(Appendix 1)
In a semiconductor memory that reads or writes data based on an access request from a memory controller,
The semiconductor memory is
Based on a read request from the memory controller, a first read strobe signal used to capture first read data is sent to the memory controller,
A second read strobe signal used for fetching second read data based on the read strobe signal output from the memory controller based on the first read strobe signal; memory.
(Appendix 2)
The semiconductor memory is
The semiconductor memory according to appendix 1, wherein a permission signal for permitting access based on the access request is output to the memory controller.
(Appendix 3)
The semiconductor memory is
A signal for requesting transfer of read data to the memory controller is output based on the access request, and the first read strobe is output based on a signal for permitting transfer of read data output from the memory controller based on the signal. 3. The semiconductor memory according to appendix 1 or appendix 2, characterized by outputting a signal.
(Appendix 4)
The semiconductor memory is
The semiconductor memory according to appendix 3, wherein the first and second read strobe signals and a signal requesting transfer of the read data are output to a memory controller via a common signal line.
(Appendix 5)
The semiconductor memory is
The semiconductor memory according to appendix 1, appendix 2, appendix 3 or appendix 4, wherein the first read strobe signal or the second read strobe signal is reset based on an interrupt request from the memory controller.
(Appendix 6)
The semiconductor memory is
Supplementary note 1, supplementary note 2, supplementary note 3, supplementary note, wherein the delay time from the read strobe signal output from the memory controller to the output of the second read strobe signal is changed according to an instruction from the memory controller 4. The semiconductor memory according to 4 or appendix 5.
(Appendix 7)
It has a power supply terminal that receives the power supply voltage whose value is changed,
The semiconductor memory is
Appendix 1, appendix 2, appendix 3, wherein the first read strobe signal and the second read strobe signal are output to a memory controller during at least one of the power supply voltage falling and rising The semiconductor memory according to appendix 4, appendix 5 or appendix 6.
(Appendix 8)
In a semiconductor memory that reads or writes data based on an access request from a memory controller,
The semiconductor memory is
Sending a write strobe signal to the memory controller based on the first write strobe signal from the memory controller, and taking in the first write data based on the first write strobe signal,
A semiconductor memory, wherein second write data is fetched based on a second write strobe signal output from a memory controller based on the write strobe signal.
(Appendix 9)
The semiconductor memory is
9. The semiconductor memory according to appendix 8, wherein a permission signal for permitting access based on the access request is output to the memory controller.
(Appendix 10)
The semiconductor memory is
A signal for requesting transfer of write data generated based on the access request is input, a signal for permitting transfer of write data based on the signal is output to the memory controller, and writing and data transfer are permitted. The semiconductor memory according to appendix 8 or appendix 9, wherein the first write strobe signal generated based on the signal is input.
(Appendix 11)
The semiconductor memory is
11. The semiconductor memory according to appendix 10, wherein the first and second write strobe signals and the signal requesting transfer of the write data are received from a memory controller via a common signal line.
(Appendix 12)
The semiconductor memory is
12. The semiconductor memory according to appendix 8, appendix 9, appendix 10, or appendix 11, wherein the write strobe signal is reset based on an interrupt request from the memory controller.
(Appendix 13)
The semiconductor memory is
According to appendix 8, appendix 9, appendix 10, appendix 11 or appendix 12, wherein a delay time from the first write strobe signal to outputting the write strobe signal is changed according to an instruction from a memory controller The semiconductor memory as described.
(Appendix 14)
It has a power supply terminal that receives the power supply voltage whose value is changed,
The semiconductor memory is
The supplementary note 8, the supplementary note 9, the supplementary note 10, the supplementary note 11, the supplementary note 12 or the like, wherein the first write data and the second write data are captured while the power supply voltage is falling or rising. The semiconductor memory according to appendix 13.
(Appendix 15)
In a memory controller that outputs an access request for reading or writing data in a semiconductor memory,
The memory controller is
Taking in the first data based on the first read strobe signal output from the semiconductor memory based on the read request, generating the read strobe signal based on the first read strobe signal, and outputting to the semiconductor memory,
A memory controller, wherein the second read data is captured based on a second read strobe signal generated based on the read strobe signal and output from the semiconductor memory.
(Appendix 16)
The memory controller is
16. The memory controller according to appendix 15, wherein a delay time from the first read strobe signal to the output of the read strobe signal is changed.
(Appendix 17)
In a memory controller that outputs an access request for reading or writing data in a semiconductor memory,
The memory controller is
A first write strobe signal for the semiconductor memory to capture the first data is output to the semiconductor memory;
Based on the write strobe signal generated based on the first write strobe signal and output from the semiconductor memory, the semiconductor memory outputs a second write strobe signal for capturing the second data to the semiconductor memory. A memory controller featuring.
(Appendix 18)
The memory controller is
18. The memory controller according to appendix 17, wherein a delay time from the write strobe signal from the semiconductor memory to the output of the second write strobe signal is changed.

  From the above detailed description, features and advantages of the embodiment will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and changes, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

2 illustrates an example system in one embodiment. 2 shows an example of the memory shown in FIG. An example of the state machine and bus controller shown in FIG. 1 is shown. 2 shows an example of the memory controller shown in FIG. The state transition of the memory shown in FIG. 1 is shown. The state transition of the memory controller shown in FIG. 1 is shown. 3 shows details of the sense amplifier region S shown in FIG. An example of a read access operation of the memory shown in FIG. 1 is shown. 2 illustrates an example of a write access operation of the memory illustrated in FIG. 1. 2 shows a comparison of read access operations between the memory of FIG. 1 and a DDR-SDRAM. 3 illustrates an example of a state machine and a bus controller of a semiconductor memory in another embodiment. 12 shows an example of state transition of the memory shown in FIG. 11 and a memory controller that accesses the memory. 12 shows an example of an interrupt access operation of the memory shown in FIG. 12 shows another example of the interrupt access operation of the memory shown in FIG. 12 shows another example of the interrupt access operation of the memory shown in FIG. 12 shows another example of the interrupt access operation of the memory shown in FIG. The example of the semiconductor memory in another embodiment is shown. 18 shows an example of the state machine and bus controller shown in FIG. 18 shows an example of a memory controller that accesses the memory shown in FIG. The example of the semiconductor memory in another embodiment is shown. 21 shows an example of a read access operation of the memory shown in FIG. 21 shows another example of the read access operation of the memory shown in FIG. 21 shows an example of a write access operation of the memory shown in FIG. The example of the semiconductor memory in another embodiment is shown. An example of the state machine and bus controller shown in FIG. 24 is shown. 25 shows an example of a read access operation of the memory shown in FIG. 25 shows another example of the read access operation of the memory shown in FIG. 2 illustrates an example of a system in another embodiment. The performance of the memory mounted in the system shown in FIG. 28 is shown. 29 shows an example of a read access operation of the memory shown in FIG. 29 shows another example of the read access operation of the memory shown in FIG. 2 illustrates an example of a system in another embodiment. FIG. 33 shows an example of the memory shown in FIG. 32. FIG. 34 shows an example of a read access operation of the memory shown in FIG. 33 shows an example of a write access operation of the memory shown in FIG. 2 illustrates an example of a system in another embodiment. 37 shows an example of a read access operation of the memory shown in FIG. FIG. 37 shows an example of a write access operation of the memory shown in FIG. 36. FIG. 2 illustrates an example of a system in another embodiment. 40 shows an example of a read access operation of the memory shown in FIG. 40 shows an example of a write access operation of the memory shown in FIG. 2 illustrates an example of a system in another embodiment. 43 shows an example of a read access operation of the memory shown in FIG. 10 shows an example of a memory read access operation in another embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Address latch; 12, 12B ... Command decoder; 14, 14A, 14C, 14D ... State machine; 16, 16A, 16B ... Bus controller; 18 ... Memory core; 20B ... Mode register; Address selection circuit; ACK ... permission signal; MCNT ... memory controller; MEM ... semiconductor memory; MPU ... microcontroller; RDATA ... read data transfer request signal, write data transfer enable signal; RDQS ... read strobe transfer request signal, write strobe transfer enable REQ ... access request signal; SYS; system; WDATA ... read data transfer enable signal, write data transfer request signal; WDQS ... read strobe transfer enable signal, write strobe transfer request signal

Claims (5)

In a semiconductor memory that reads or writes data based on an access request from a memory controller,
The semiconductor memory is
Based on a read request from the memory controller, a first read strobe signal used to capture first read data is sent to the memory controller,
A second read strobe signal used for fetching second read data based on the read strobe signal output from the memory controller based on the first read strobe signal; memory. The semiconductor memory is
2. The semiconductor memory according to claim 1, wherein a permission signal for permitting access based on the access request is output to the memory controller. In a semiconductor memory that reads or writes data based on an access request from a memory controller,
The semiconductor memory is
Sending a write strobe signal to the memory controller based on the first write strobe signal from the memory controller, and taking in the first write data based on the first write strobe signal,
A semiconductor memory, wherein second write data is fetched based on a second write strobe signal output from a memory controller based on the write strobe signal. In a memory controller that outputs an access request for reading or writing data in a semiconductor memory,
The memory controller is
Taking in the first data based on the first read strobe signal output from the semiconductor memory based on the read request, generating the read strobe signal based on the first read strobe signal, and outputting to the semiconductor memory,
A memory controller, wherein the second read data is captured based on a second read strobe signal generated based on the read strobe signal and output from the semiconductor memory. In a memory controller that outputs an access request for reading or writing data in a semiconductor memory,
The memory controller is
A first write strobe signal for the semiconductor memory to capture the first data is output to the semiconductor memory;
Based on the write strobe signal generated based on the first write strobe signal and output from the semiconductor memory, the semiconductor memory outputs a second write strobe signal for capturing the second data to the semiconductor memory. A memory controller featuring.
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