JPS5952375A - Arithmetic device - Google Patents

Abstract

PURPOSE:To prevent the erroneous inversion of output data polarity during an overflow, by setting larger the bit width of a part covering an adder circuit through a working register than that of the part of a data memory. CONSTITUTION:The data read out of an RAM106 is applied to a code expanding circuit 109 and then loaded to a working register 103 via an adder circuit 101 in the form of a signal of 18-bit width. Then the desired calculation is carried out by the multiplier data, etc. stored in an ROM111, and the data Wi in an equation is stored in the register 103. This data Wi is loaded to a data memory 7 after stored temporarily in the RAM106. When the data is stored in the RAM 106, it is sent to a clamping circuit 105 which converts the data of 18 bits into the 16-bit width. In such a way, the polarity of the output data is not inverted even though the overflow is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an arithmetic device using an accumulation program control method used in fast Fourier transform and digital signal processing.

[Technical background of the invention and its problems]

Referring to FIG. 1, a case will be described in which a conventional arithmetic unit performs digital filter processing. In FIG. 1, 1.
2 indicates an adder circuit which is an arithmetic circuit, 3.4.5.6 indicates a multiplication circuit, and 7.8 indicates a data memory (delay circuit). As shown in the figure, the input data is X11, the output data is Yi, the data output from the adder circuit 1 is Y1, the data output from the data memory 7 is W1, and the data output from the data memory 8 is Wi1. -2, multiplication circuit 3,
4.5゜6 each multiplier bl + b2 * al
*If &2, this performance is 3! In a filter consisting of l-devices, the following operations are performed.

In this way, each output data w of the data memory 7.8
i-1+'wi-2 is sent to the multiplier circuits 3 and 4 as multipliers b, respectively.
1. A filter that is multiplied by b2 and each result is fed back to the input is called a recursive filter. In this recursive filter, if the result of addition by the adding circuit 1 overflows, the filter may oscillate depending on the conditions, making it impossible to obtain normal output data. For example, even though the correct operation result when an overflow occurs is negative data, the most significant bit (the bit indicating positive or negative) of the data output from the adder circuit is changed due to the overflow, and the result is negative. Suppose that the data indicates that the data is . Then, in the following process, even if correct input data x1 arrives, the bit indicating positive or negative is changed every time there is an overflow.
The filter will oscillate.

Therefore, in conventional arithmetic units, an overflow detection flag is provided, and when an overflow occurs,
An operation was performed by a program to replace the data of the maximum absolute value of the same sign (positive and negative) in the bit width of the adder circuit 1 as different output data. By doing this, it is possible to prevent oscillation of the filter, but since the processing is performed by a program, there is a drawback that the processing speed is reduced.

Furthermore, even if the above processing were to be performed by hardware, the calculation accuracy would be increased. Since the width of 21 paths rarely exceeds 10 bits, no improvement in accuracy could be expected. Moreover, depending on the need, many stages of such filters are often connected in cascade, and when many stages are connected in cascade, the overflow that occurs in the previous stage spreads to the next stage and subsequent stages, resulting in the inconvenience of amplifying the peaks. .

The above description can be applied to the adder circuit 2 in almost the same way.

[Purpose of the invention]

The present invention has been developed in view of the above-mentioned drawbacks, and its purpose is to provide an arithmetic device that can prevent filter oscillation and obtain highly accurate results without reducing processing speed. be.

[Summary of the invention]

Therefore, the present invention provides at least an arithmetic circuit that performs addition, a working register that accumulates data output from the arithmetic circuit, a data memory that accumulates data used in the arithmetic circuit, and a data memory that accumulates data output from the working register. a first for guiding data to one input terminal of the arithmetic circuit;
a second path that leads the data output from the working register to the data memory; a third path that leads the data output from the data memory to the other input end of the arithmetic circuit; a fourth path that leads data output from an arithmetic circuit to the working register, the arithmetic circuit, the working register, the first and fourth paths, and the second and third
The bit width of a part of the path is set to be larger than the bit width of the data memory, a clamp circuit that performs a bit width reduction operation is interposed in the second path, and a bit width of the third path is set to be larger than the bit width of the data memory. By interposing a sign extension circuit that performs an extension operation,
The computing device was constructed. Although the object of the present invention is thereby achieved, in order to further increase the effect of the present invention, in addition to the above configuration, an overflow of the addition result is detected in the 40th path, and the output data is sent to the above arithmetic circuit. A clamp circuit is provided to clamp the signals to the absolute value of the maximum value of the same sign in the bit width that can be output.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows a block diagram of a digital filter to which the present invention is applied. This digital filter is a biquad filter. In FIG. 2, the same components as in FIG. 1 are given the same numbers as in FIG. 1, and their explanations are omitted. In FIG. 2, reference numeral 9 denotes a clamp circuit, which performs an operation of reducing data to be input into the data memory 7 to the bit width of the data memory 7. Reference numerals 10 and 11 indicate sign extension circuits, which perform an operation of extending data provided to adder circuits 1 and 2, respectively, to the bit width of adder circuits 1 and 2. 12, 13
is a clamp circuit.

Further, in this embodiment, all the input/output paths of the adder circuit 1.2 are 18 bits, and the data memory 7.8
It is assumed that all input/output paths are 16 bits. Then, the data stored in the data memory 7.8 and output from the data memory 7.8 is shifted and clamped by the clamp circuit 9, so that the adder circuit 1.2 has a large pitch width ( (18 bits) is clamped, and in practice, data of values up to the maximum (minimum) value of 16 bits is input to one of the input terminals.

Therefore, the dynamic range of the adder circuit 1.2 will not be exceeded. Furthermore, when data is stored in the data memory 7.8, it is shifted by the clamp circuit 9,
The dynamic range of the data memory 7.8 will not be exceeded.

Next, a calculation device for such a filter will be explained with reference to FIG.

In FIG. 3, 101 is an adder circuit. This adder circuit 101 outputs 18-bit output data from a fourth path 102 to a working register 103. The output data path of the working register 103 is the adder circuit 10.
18-bit first path 104 to one input end of 1
It becomes. Furthermore, the output data of the working register 103 is transferred to a part of the second path (hereinafter referred to as the clamp circuit 105).
The signal is output to the clamp circuit 105 through an input path (referred to as an input path). Furthermore, the output data of the clamp circuit 105 is configured to be outputted to the RAM 106, which is a data memory, via a second path 107. Further, the data in the RAM 106 is transferred to a third path 108.
and the input path 11 of the adder circuit 101, which is part of the third path.
3 to the adder circuit 101.
A sign extension circuit 109 is interposed in this third path 108 .

Further, 16-bit data is applied from the RAM 106 to one input terminal of the multiplication circuit 110, and 16-bit multiplier data from the ROM 111 is applied to the other input terminal of the multiplication circuit 110.

Further, the output data of the multiplication circuit 110 is transmitted through a third path 10
8 to the sign extension circuit 109. The clamp circuit 112 in FIG. 3 corresponds to the clamp circuits 12 and 13 in FIG. 2, and will be described here assuming that it is not present.

Adder circuit 101 of the arithmetic device configured as above corresponds to adder circuit 1.2 in FIG. 2, 1 multiplier circuit 110 corresponds to multiplier circuit 3.4.5.6, and clamp circuit 105 corresponds to 9, the sign extension circuit 109 corresponds to the sign extension circuits 10 and 11, and the RAM 106 corresponds to the data memory 7.8. Although the corresponding components of the ROM 111 and the working register 103 are not shown in FIG. 2, they have the function of providing the multiplier of the multiplier circuit 3.4.5.6 of FIG. 2, and the clamping circuit of FIG. This corresponds to the function of accumulating data before the circuit 9.

Furthermore, the adder circuit 101, the working register 103, the first path 104, the fourth path 102, and the clamp circuit 1050 input path (part of the second path) are 18 bits, and the RAM 106 ( The bit width is wider than that of the data memory (data memory), which is 16 bits.

The operation of the arithmetic device configured as above will be explained. First, data is read from the RAM 106 and provided to the sign extension circuit. Here, the data has a bit width of 18 bits, is passed through an adder circuit 101, and is loaded into a working register 103. Next, RAM106
Data corresponding to the output data of the data memory 7 in FIG.
Data corresponding to 0 multiplier b1 is read out and multiplier circuit 1
10 to the other input terminal. As a result, after a certain period of time, a 16-bit multiplication result is output from the multiplication circuit 110, and this data is sent to the sign extension circuit 109 via the third path 108. In this sign extension circuit 109, the input 16-bit data is converted into 18-bit data, and this data is sent from the input path 113 of the adder circuit 101, which is part of the third path, to one input of the adder circuit 101. given to the end. At this time, the aforementioned input data has already been applied to the other input terminal of the adder circuit 101 from the working register 103 via the first path 104. Adder circuit 101 adds these data, and the resulting data is loaded into working register 103 via fourth path 102 .

Also, the data memory 8 in FIG. 2 in the RAM 106
The same operation as above is performed using the data corresponding to the data corresponding to the data and the data corresponding to the multiplier b2 of the multiplier circuit 4 in FIG. Indicated by

The stored data is stored. This data needs to be stored in the data memory 7 in FIG. 2 for the next processing, but at this stage, the data memory 7.
Since I would like to be able to destroy the stone data stored in the
06). At this time, the clamp circuit 105 extracts the lower 16 bits of the 18-bit data output from the working register 103.

At this time, if the 18-bit data is a value that cannot be expressed in a 16-bit width, the r2-amp circuit 105 converts the 18-bit data into a value that has the same sign (positive or negative) and is equal to the maximum value of the 16-bits. ), expressed in hexadecimal notation is 7FFF (
when it is a positive number), soo.

(When the number is negative 5) Clamp to one of -.

Furthermore, the output data of the data memory 7.8 in FIG. This is done in the same way as above. In this manner, oscillation can be prevented by the operation of the clamp circuit 105, and since the processing is not based on a program, the processing speed will not be reduced. Therefore, conventionally, highly accurate calculation results are guaranteed.

Next, the clamp circuits 12, 13, and the third clamp circuit in FIG.
A case where the clamp circuit 112 shown in the figure is interposed will be explained.

A beam 2 amplifier circuit 112 is interposed in the fourth path 102 in FIG. This clamp circuit 112 is a circuit that detects when an overflow occurs in the adder circuit 101 and clamps its output to 18-bit maximum value data with the same sign as the overflow data. Due to the function of this clamp circuit 112, even if the output data of the adder circuit 101 overflows beyond the 18-bit width, it will be clamped, and the portions of the adder circuit 101, fourth path 102, clamp circuit 112, and working register 103 will be , compared to the entire arithmetic unit having a width of 16 bits,
The data is processed with a wider width of 18 bits and becomes data with 18 bit precision. The same applies when there is no clamp (b) path 112, but in the adder circuit 101, fourth path 102, clamp N path 112, and working register 103, the keys (18-bit width) that are not shifted by the clamp circuit 112 are As long as the width does not exceed 9), correct operation results can be guaranteed with an 18-bit width.

〔Effect of the invention〕

As explained above, according to the present invention, the bit width of the portion from the adder circuit to the working register is set wider than the bit width of the data memory (RAM) portion, so that the arithmetic processing in this portion is is performed over a wide dynamic range. In particular, when using digital filters in cascade as in the embodiment, the input and output of each stage is only transferred through the working register, so the dynamic range of the working register is instantaneously exceeded in the above portion. However, it is guaranteed that accurate calculation results will be obtained as long as the dynamic range that has been set widely is not exceeded.

Even if the dynamic range that has been set wide is exceeded, the data is clamped by the clamp circuit and given to the addition (B) path again, so unlike the conventional operation, the filter is overlooked due to sign inversion. is never done.

Furthermore, by expanding the bit width and providing a clamp circuit in the calculation section with a wide dynamic range,
Even if Hiko filters are connected in series as in the embodiment, the polarity of the output data can always be maintained correctly, and an improvement in accuracy can be expected.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional digital filter.
FIG. 2 is a block diagram showing a digital filter to which the present invention is applied, and FIG. 3 is a block diagram of an embodiment of the present invention. 101...Addition circuit 102...Fourth path 1
03... Working register 104... First path 105, 112... Clamp circuit 106... RAM (data memory) 107... Second path 108 (113)... Third path 109...Sign extension circuit 110...Multiplication circuit 111...ROM

Claims (4)

[Claims] (1) at least an arithmetic circuit that performs addition, and a working register that accumulates data output from the arithmetic circuit;
a data memory that stores data used in the arithmetic circuit; a first path that leads data output from the working register to one input terminal of the arithmetic circuit; and a data memory that stores data output from the working register; a second path leading to the memory; and a third path leading the data output from the data memory to the other input terminal of the arithmetic circuit.
and a fourth path that leads data output from the arithmetic circuit to the working register, the arithmetic circuit, the working register, the first and fourth paths, and the second path. The bit width of a part of the third path is set to be larger than the bit width of the data memory, and a clamp circuit for reducing the bit width is interposed in the second path. 1. An arithmetic device characterized in that a sign extension circuit for performing a bit width extension operation is interposed in the processor. (2) The third path leading to the sign extension circuit is provided with output data from a multiplication circuit that multiplies the data output from the data memory and other data. 1) The arithmetic device described in section 1). (3) at least an arithmetic circuit that performs addition, and a working register that accumulates data output from the arithmetic circuit;
a data memory that stores data used in the arithmetic circuit; a first path that leads data output from the working register to one input terminal of the arithmetic circuit; and a data memory that stores data output from the working register; a second path leading to the memory; and a third path leading the data output from the data memory to the other input terminal of the arithmetic circuit.
and a fourth path that leads data output from the arithmetic circuit to the working register, the arithmetic circuit, the working register, the first and fourth paths, and the second and fourth paths. The bit width of a part of the third path is set to be larger than the bit width of the data storage, a clamp circuit for reducing the bit width is interposed in the second path, and the bit width is set in the third path. A sign extension circuit that performs an expansion operation is interposed, and a clamp circuit is interposed in the fourth path that detects an overflow of the calculation result and clamps the output data to the absolute value of the maximum value that can be output by the calculation circuit with the same sign. An arithmetic device that takes the percentage of what happened. (4) The path of wc3 to the sign extension circuit is provided with output data from a multiplication circuit that multiplies data output from the data memory and other data. ).