JPH01288921A - Rounding processing system - Google Patents

Abstract

PURPOSE:To make an arithmetic result highly accurate without hardly increasing a circuit scale by providing a rounding circuit to output one bit to be rounded with a rounding instruction out of an arithmetic means and an arithmetic result, an adder, an output means, etc. CONSTITUTION:When the rounding instruction is inputted, only the one bit value to be rounded is fetched from a rounding circuit 12 out of the arithmetic result, and it is added with the output arithmetic result of a memory means 11 by an adder 13. From this, the arithmetic result, to which the rounding processing is executed, is fetched from the adder 13, supplied to an output means 14, and here, made into the arithmetic result consisting of one bit to be practically rounded and the respective bits on a high-order side. Since the final arithmetic result obtained by an operation at full accuracy by means of an arithmetic means 10 is stored into the means 11, the rounding processing is executed not in the middle of the operation but only for the final arithmetic result. Further, by sharing the adder 13 and the means 14 as a part of the means 10, a circuit constitution is simplified and the highly accurate arithmetic result can be obtained.

Description

[Detailed Description of the Invention] [Summary] To obtain high-precision calculation results without substantially increasing the circuit scale regarding the rounding process 7J formula for obtaining calculation results with a predetermined number of digits in a digital signal processor, etc. A calculation means for obtaining an operation result based on a desired operation formula, a storage means for storing the operation result, and an output of one bit of the operation result supplied from the storage means to be rounded manually by a rounding instruction. A rounding circuit that outputs 1 pin 1 of the rounding circuit
- an adder that modulates the signal and the operation result from the storage means, and of the output signal of the modifier, only the one bit to be rounded and all bits on its upper side are substantially modified by inputting the rounding command; and an output means for outputting to.

[Industrial application field]

The present invention relates to a rounding processing method, and more particularly to a rounding processing method for obtaining operation Q results of a digital signal processor or the like with a predetermined number of digits.

The calculation results of digital signal processors, etc. must be transmitted using the preset right limit number of digits, so
Rounding is required to reduce the result to a smaller number of digits than the above finite number of digits. Since this rounding process inevitably causes an error in the calculation result, it is important to minimize the error as much as possible.

[Conventional technology]

FIG. 6 shows an example of a conventional rounding processing method.

This example multiplies the value of data A and 8, and the product and data C
In this example, as shown in FIG. 6, first, for example, 16-bit data A and B are each multiplied to obtain a multiplication result 1. This multiplication result 1 is 32 bits, but for example, the value of the 5th bit of the multiplication result 1 shown as 2 in FIG. IXI calculation is performed to obtain a 27-bit multiplication result by rounding off the lower 5 bits of multiplication result 1, as shown at 4 in the figure.

Next, 27-bit data C is added to this rounded multiplication result 4 to obtain the lower 27-bit product-sum operation result shown at 5 in FIG. Then, the product-sum operation result 5 is converted into 16 bits 9
In order to transmit on a transmission path, the lower 11 bits are discarded to obtain a rounded output of the 16-bit product-sum operation result as shown at 6 in FIG.

In this way, conventionally, the product-sum operation result of the product of each 16 bits of data A and B and the phase of 27 bits of data C is calculated as 16 bits.
It was transferred rounded into bits.

[Problem to be solved by the invention]

However, in the conventional rounding process, 4,6
t- As shown, rounding is performed every time an operation is performed, so when performing cumulative 1i1i such as C = AXB + C, the more the number of operations increases, the larger the error 1 due to rounding becomes, making it difficult to perform high-precision calculations. This method has the drawbacks of not producing good results and of reducing versatility.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a rounding processing method that can obtain highly accurate arithmetic results without substantially increasing the circuit scale.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. In the same figure, 10
is an arithmetic means, which obtains an arithmetic result based on a desired arithmetic expression.

Reference numeral 11 denotes a storage means for storing the above calculation results. 12 is a rounding circuit which outputs one bit of the above operation result to be rounded by inputting a rounding instruction.

Reference numeral 13 denotes an adder that adds the two-way power signals of the storage means 11 and the rounding circuit 12. Reference numeral 14 denotes an output means that essentially outputs only one bit to be rounded and all bits on its higher-order side by inputting a rounding command.

[Effect]

When a rounding command is input, only the 1-bit value to be rounded out of the operation result is taken out from the rounding circuit 12 and sent to the adder 13.
It is added to the output calculation result of the storage means 11 in the step. As a result, the rounded operation result is taken out from the adder 13 and supplied to the output means 14, where it is made into an operation result that essentially consists of the 1 bit to be rounded and each bit on its upper side. .

In the present invention, since the final rounding result obtained by calculating with full precision by the calculation means 10 is stored in the storage means 11, rounding processing is performed only on this final calculation result, and the calculation No intermediate rounding is performed.

Further, by sharing the adder 13 and the output means 14 as a part of the stop means 10, the circuit configuration can be further simplified.

〔Example〕

FIG. 2 shows a configuration diagram of an embodiment of the present invention. In the figure, the same components as in FIG. 1 are given the same reference numerals. Although this embodiment shows an example in which some circuits (adder 13, clip circuit 19) in the calculation means 10 are used in common with the adder 13 and the output means 14, it is of course possible to provide them separately. is also possible.

In FIG. 2, 15 is a data selector, and a rounding instruction R
When the value of NDOP is "0" (no rounding command input), data A or data (AXB) is selected and output according to the value of select signal A/AXB. Here, data (
AXB) is full-precision 32-bit data obtained by multiplying each 16-bit data A and B.

On the other hand, when the value of the rounding command RNDOP is "1" (when there is a rounding command input), the data selector 15 is all "ON" regardless of the value of the select signal RA/AXB.
Forcibly output the data.

16 is an RND circuit, and the value of the rounding instruction RNDOP is “O”
When the output 1 bit becomes O'', the rounding instruction RND
Only when the value of OP is ``1'', the lower 16 bits of the 32-bit data C from the accumulator 20 are input, and a total of 2 bits of the least significant bit and the sign bit of the upper 16 bits are input, A predetermined rounding process is performed and one bit to be rounded is output. Here, the rounding method of the RND circuit 16 is based on the 2-bit input of RNDl and RND2, and is based on the IEEE (In5titudinal
of Electrical and Hectron
ics Engineers) 17:1 of the four rounding methods of the standard is selected.

Further, 17 is a two-man OR circuit which takes the logical sum of 1 bit of the output of the data selector 15 and 1 bit of the output of the RND circuit 16. The OR circuit 17 and the RND circuit 16 constitute a rounding circuit 12.

Further, 18 is an overflow detection circuit, 19 is a clip circuit, which constitutes the output means 14, and 20 is an accumulator, which constitutes the first storage stage 11. .

Next, the operation of this embodiment will be explained.

■During normal arithmetic operation At this time, the value of the rounding instruction RNDOP is 170 N, and RND@v! 116 is always set to "0" (in this case, it is equivalent to the absence of the RND circuit 16), and the data selector 15 outputs the select signal A.
/AXB calculates and outputs data A or data (AXB). Here, when data A is output, the data selector 15
Since the most significant bit of the output 32 bits of data is a sign bit (when in two's complement format), the same value as the most significant bit is added to the upper 16 bits. The least significant bit of the upper 16 bits of the 32-bit signal output from the data selector 15 is passed through the OR circuit 17 to the remaining 31 bits.
After being added to 32 bits, the adder 13
is supplied to one input terminal of

The 32 bits output from the accumulator 20 are input to the other input terminal of the adder 13, but initially all “0”
The 32-bit data entered into one input terminal of the adder 13 is supplied to the overflow detection circuit 18 and clipping circuit 19 through the adder 13 as is. The overflow detection circuit 18 causes the clipping circuit 19 to perform the clipping operation only when the output 32-bit data of the adder 13 overflows, and sets it to the maximum positive or negative value, and stops the clipping behavior when there is no overflow.

The 32-bit data taken out from the clip circuit 19 is supplied to an accumulator 20 and stored there.

The output 32-bit data of this accumulator 2o is
Then, data C is transferred to the data bus while being supplied to the adder 13.

Thereafter, by repeating the same operation as above, the accumulator 20 has (A+C) or (AxB+C
) 32-bit operation results will be stored.

■Maru-dokoro T! ! ! The rounding process is performed when the operation result is stored in the accumulator 20 during operation, using the rounding instruction RN'D added to the operation instruction of the general-purpose digital signal processor.
The value of OP is set to 1''.

As a result, all 32 bits output from the data selector 15 are turned on, and the RND circuit 16 performs rounding processing.

t, that is, 32 bits of data C shown as 22 in FIG.
The bit, the least significant bit of the upper 16 bits, and the sign bit are supplied to the RND circuit 16, and as shown at 23 in FIG. (1 bit of the 17th lower bit) is taken out from the RND circuit 16, and the OR circuit 17
It is input to the aging device 13 through.

Here, the rounding method by the RND circuit 16 is based on IEEE
There are four rounding methods in the standard, ORN (RoundNear
est), ORp (Round Plus), ■R
M (Round Minus) ORZ (Round
Zero), but since these are well known, detailed explanation thereof will be omitted, and PJI! I'll stop at an explanation. When the data representation format is two's complement format, the fourth
The 1 bit to be rounded (lower 17th bit) of the 32-bit data shown as 26 in the figure is ■lower 16th bit,■,
Assuming that the lower 15 bits are ■ and the most significant bit (that is, the sign bit) is S, the 1-bit IUR to be rounded can be calculated using the formula shown in the table below.

In addition, in the above table and the following table, "+" indicates an OR operation between corresponding bits, and "x" indicates an AND operation between corresponding bits.

Also, when the data representation format is absolute value format, R
The rounding methods for N, RP, RM and RZ are as shown in FIG. In addition, in Figure 5, "Positive 1, [Negative, 1] indicates the polarity of 32-bit data. Also, the sticky bit is ■, the guard bit is ■, the least significant bit is O, the sign bit is S, and the 1 to be rounded is Letting the value of the bit be R, R can be found using the arithmetic expression shown in the following table.

Table 2 Returning to Figures 2 and 3 again, as described above,
The 1-bit value to be rounded (the 17th low-order bit, shown as 23 in FIG. 3), which has been rounded using one of the four rounding methods in the RND circuit 16, is 7 32-bit data C from the cumulator 20
(shown as 24 in Figure 3, which is the same as 22) is added to the 32-bit addition signal, and then the clip circuit 1
9.

The clipping circuit 19 receives the rounding instruction RNDOP with a value of 1''.
is input, the 1 bit to be rounded (lower 1
The value of the upper 16 bits consisting of the 7th bit) and all bits on its upper side (upper 15 bits) is output as is, and the value of the remaining lower 16 bits is clipped to make it all 0. Therefore, the clipping circuit From 19, 32 bits of data as shown in 25 in FIG.
This is 16-bit data that has been rounded off (final calculation result).

As described above, according to this embodiment, rounding processing is performed only on the final calculation result, so highly accurate rounding processing output data can be obtained, and the RND circuit 16 and O
It can be constructed by simply adding the R circuit 17, and further reduces the damping volume 13.
, the clip circuit 19, etc. are shared, so the circuit structure can be simplified.

Note that the present invention is not limited to the above-described embodiment, and if one clip circuit is not shared, for example, the output means 14 may be configured with a gate circuit that outputs only the upper 16 bits instead of the clip circuit 19. You can.

〔Effect of the invention〕

As described above, according to the present invention, rounding is performed only on the final calculation result, resulting in higher calculation accuracy than the conventional method in which rounding is performed every time one calculation is completed during the calculation. In addition, since it can be constructed by simply adding a few circuits to an existing circuit, the circuit size hardly increases, and furthermore, a part of the circuit constituting the calculation means can be shared by the adder and the output means. This has the advantage of being able to further prevent an increase in circuit scale.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Fig. 4 is an explanatory diagram of a rounding method in two's complement format. , FIG. 5 is an explanatory diagram of an absolute value format rounding method, and FIG. 6 is an explanatory diagram of an example of the conventional method. In the figure, 10 is an arithmetic means, 11 is a storage means, 12 is a rounding circuit, 13 is an adder, 14 is an output means, and RNDOP is a rounding instruction. Patent Applicant Fujitsu Co., Ltd. Agent Patent Attorney Tadahiko Ito 1.1.,') 0''

Claims (1)

[Claims] Calculating means (10) for obtaining calculation results based on a desired calculation formula.
a storage means (11) for storing the operation result; and a rounding circuit (12) for outputting one bit of the operation result supplied from the storage means (11) to be rounded by inputting a rounding command.
and the output 1-bit signal of the rounding circuit (12) and the storage means (
an adder (13) that adds the operation result from the adder (11); and of the output signal of the adder (13), only the one bit to be rounded and all bits on its upper side are substantially converted by inputting the rounding instruction. 1. A rounding processing method characterized by comprising: an output means (14) for outputting an output.