JPS5951552A - Manufacture of integrated circuit substrate - Google Patents
Manufacture of integrated circuit substrateInfo
- Publication number
- JPS5951552A JPS5951552A JP16187582A JP16187582A JPS5951552A JP S5951552 A JPS5951552 A JP S5951552A JP 16187582 A JP16187582 A JP 16187582A JP 16187582 A JP16187582 A JP 16187582A JP S5951552 A JPS5951552 A JP S5951552A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- pattern
- integrated circuit
- unbaked
- circuit substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
- H05K1/092—Dispersed materials, e.g. conductive pastes or inks
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は鶏’［ｊ回路用Ｍ’板の製造方法に関する。[Detailed description of the invention] The present invention relates to a method for manufacturing a M' board for a J circuit.
一般にアルミナ等を主成分としたセラミック基板は、絶
縁体とし、て集積１１１１路用の基板又はパッケージと
して多ｈ４に使用されている。このセラミック基板は、
必要に応じて基板分割用の？１．ｒやスルーホールが形
成された未焼成基板をｌＴ：′Ｉ温で焼成して形成され
るが、セラミノクツ、（也はぞ１通蓄成すると収縮する
為、その収縮率全考慮して：ｉｋ Ａｔｉの大きさ、ス
ルーホールの位置等が定められる。In general, ceramic substrates mainly composed of alumina or the like are used as insulators and are widely used as substrates or packages for integrated 1111 circuits. This ceramic substrate is
For board division if necessary? 1. It is formed by firing an unfired substrate on which r and through holes are formed at lT:'I temperature, but since ceramics shrink when they are accumulated, the shrinkage rate is taken into account: ik The size of Ati, the position of the through hole, etc. are determined.
この様に収縮率を考慮しても、焼成したセラミック基板
の寸法は１％程度の誤差を有する。従って、使用するセ
ラミック基板の寸法を統一する為には全てのセラミック
基板を測定し分類する必要があるが、一般には、セラミ
ック基板の周辺部を゛さけて回路パターンを形成するこ
とによりセラミック基板寸法のばらつきによる影響ヲ除
いている。Even when considering the shrinkage rate in this way, the dimensions of the fired ceramic substrate have an error of about 1%. Therefore, in order to standardize the dimensions of the ceramic substrates used, it is necessary to measure and classify all the ceramic substrates, but in general, by forming a circuit pattern avoiding the periphery of the ceramic substrate, the dimensions of the ceramic substrate can be determined. This excludes the effects of variations in
第１図は回路パターンが形成さｔまた従来の集積回路用
基板の断面図である。FIG. 1 is a cross-sectional view of a conventional integrated circuit substrate on which a circuit pattern is formed.
第１図において、セラミック等より成り絶縁性を有する
基教徒は、基板焼成時に形成でれた基板分割用の溝２，
２′ が設けられておシ、父、１ｉｉ−版ｌの表面には
回路パターンとして導体３及びｌＪ（抗４が形成されて
いる。In Fig. 1, the insulation material made of ceramic or the like is the groove 2 for dividing the board formed during the firing of the board,
A conductor 3 and a conductor 4 are formed as a circuit pattern on the surface of the 1ii-version 1.
この様に１私回路用の基板に基板分割Ｊ１．ｌの１１１
ｔやスルーホール等が形成されている場合、基板１の収
縮によるばらつきを考慮し、基板１）に形成される導体
３や抵抗４のパターンに設旧マージン全比較的多くとる
必要が、ある。この設合ｉマージンはそれだけｆ積回路
の集積度を高める為の障害となっている。In this way, the board is divided into 1 private circuit board J1. 111 of l
When holes, through holes, etc. are formed, it is necessary to take into account variations due to shrinkage of the substrate 1, and to provide a relatively large margin for the patterns of the conductors 3 and resistors 4 formed on the substrate 1). This i-margin is an obstacle to increasing the degree of integration of f-product circuits.
更に、使用する基板は生産工程上できる限シ同じ寸法に
区分して用いる心安があるが、その為には基板１に設け
られた分割用の溝やスルーホールの間隔を基板ごとに測
定しなければならない欠点がある。Furthermore, it is safe to use the boards to be divided into the same dimensions as much as possible in the production process, but to do so, it is necessary to measure the spacing between the dividing grooves and through holes provided on the board 1 for each board. There are certain drawbacks.
本発明の目的は上記欠点を除去し、焼成後の基板寸法を
簡単に精度良く測定できる集積回路用基板の製造方法を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an integrated circuit substrate, which eliminates the above-mentioned drawbacks and allows the dimensions of the substrate after firing to be easily and accurately measured.
本発明の集積回路、男基板の製造方法は、未焼成基板表
面の一部に一定間隔のパターンを印刷する工程と、この
未焼成基板を焼成する工程とを含んで構成される。The method for manufacturing an integrated circuit and a male substrate of the present invention includes the steps of printing a pattern at regular intervals on a part of the surface of an unfired substrate, and firing the unfired substrate.
次に本発明について実施例を用いて説明する。Next, the present invention will be explained using examples.
第２図（ａｌ 、 （ｂｌは本発明の一実施例を説明す
る為の主な製造工程における断面図である。FIG. 2 (al and bl) are cross-sectional views showing the main manufacturing steps for explaining one embodiment of the present invention.
まず、第２図（ａＪに示すように未焼成基板１１′のｙ
ｔｆｌｉ部に、例えばタングステンペーストにより一定
間隔のパターン５′ヲ印刷する。First, as shown in FIG. 2 (aJ), the unfired substrate 11' is
Patterns 5' at regular intervals are printed on the tfli portion using, for example, tungsten paste.
次に第２図（ｂ）に示すようにこの未知、成基板１１′
を焼成してタングステンのパターン５を焼結した焼成基
板１１を形成する。この焼成、基板１１は未焼成基板１
１′より収縮したものとなる。Next, as shown in FIG. 2(b), this unknown substrate 11'
A fired substrate 11 having a tungsten pattern 5 sintered thereon is formed by firing. In this firing, the substrate 11 is the unfired substrate 1
It is more contracted than 1'.
第３図は本発明の一実施例で製造した集積回路用基板の
平面図である。FIG. 3 is a plan view of an integrated circuit board manufactured according to an embodiment of the present invention.
パターン５は一定間隔の同一ラインで形成されている為
、間隔の明らかな定規をこの上にあて、パターンと比較
することにより集積回路用基板２１の寸法のばらつきを
容易に精度よく知ることができる０従って、集積回路用
基板２１は容易に寸法規格区分毎に分類できる。この為
、その寸法１ス分に適した回路パターンを印刷すること
ができるので、回路パターンの設合ｌマージンを邑らし
集積度の向上した集積回路を作ることが可能である。Since the pattern 5 is formed of the same lines at regular intervals, by placing a ruler with clear intervals on it and comparing it with the pattern, the variation in dimensions of the integrated circuit board 21 can be easily and accurately determined. Therefore, the integrated circuit substrates 21 can be easily classified into dimensional standard categories. Therefore, it is possible to print a circuit pattern suitable for the size of one square, so it is possible to make an integrated circuit with an improved degree of integration by increasing the circuit pattern layout margin.
以上詳細に説明したように、本発明によれ一１焼成後の
基板寸法を簡単に精度良く測定できる集積回路用基板の
製造方法が得られるのでその効果は大きい。As described above in detail, the present invention provides a method for manufacturing an integrated circuit board that allows the dimensions of the board after firing to be easily and accurately measured, and therefore has great effects.
第１図は回路パターンが形成された従来のケ、積回路用
の基板の断面図、第２図（ａｌ 、 ｔｂ）は本発明の
一実施例を説、明する為の主な製造工程における断面図
、第３図１は本発明の一実施例で製造した集積回路用基
板の平面図である。
１・・・・・・基板、２．２′・・・・・・溝、３・・
・・・・導体、４・・・・・・抵抗、５，５′・・・・
・・パターン、１１・・・・・・焼成基板、１１’・・
・・・・未焼成基板、２１・・・・・・集積回路用基板
。
茅１図
茅 ２ 図
病 ３ 図Fig. 1 is a cross-sectional view of a conventional integrated circuit board on which a circuit pattern is formed, and Fig. 2 (al, tb) shows the main manufacturing steps in order to explain and explain one embodiment of the present invention. 3 is a cross-sectional view. FIG. 1 is a plan view of an integrated circuit substrate manufactured according to an embodiment of the present invention. 1...Substrate, 2.2'...Groove, 3...
...Conductor, 4...Resistance, 5,5'...
...Pattern, 11...Baked substrate, 11'...
. . . Unfired substrate, 21 . . . Integrated circuit substrate. Kaya 1 figure Kaya 2 figure disease 3 figure
Claims (1)
工程と、該未焼成基板を焼成する工程とを含むことを！
１“１Ｊ徴とする犯Ａ′と回路用基板の製造方法。It includes a step of printing a pattern at regular intervals on a part of the surface of the unfired substrate, and a step of firing the unfired substrate!
1. Crime A' with 1J characteristics and method for manufacturing circuit boards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16187582A JPS5951552A (en) | 1982-09-17 | 1982-09-17 | Manufacture of integrated circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16187582A JPS5951552A (en) | 1982-09-17 | 1982-09-17 | Manufacture of integrated circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5951552A true JPS5951552A (en) | 1984-03-26 |
Family
ID=15743632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16187582A Pending JPS5951552A (en) | 1982-09-17 | 1982-09-17 | Manufacture of integrated circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5951552A (en) |
-
1982
- 1982-09-17 JP JP16187582A patent/JPS5951552A/en active Pending
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