JPS5947769A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To secure the effective channel length and largely improve MOS FET withstand voltage by sufficiently enlarging the radius of curvature of the junction of source-drain regions by a method wherein an impurity is introduced into a substrate in the state that the gate region is coated with a coat glass. CONSTITUTION:A field oxide film 22 is grown on the Si substrate 21, further a gate oxide film 23 is grown by dry oxidation, poly Si is deposited by CVD method, and then the gate 24 is formed by photoetching method after the thermal diffusion of phosphorus. Next, the coat glass is spincoated, resulting in a coat glass layer 25 whose section at the gate side part inclines, the coat glass layer 25 on the gate oxide film 23 and the gate 24 is removed by etching with fluoric acid, arsenide is implanted, and accordingly an arsenide diffused layer 26 is formed. The radius of curvature at the end part of the arsenide diffused layer 26 can be enlarged to 1mum or more, and therefore the junction withstand voltage can be largely improved to 26V.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that is particularly suitable for forming a high voltage MO8 semiconductor device.

[Prior art]

In order to improve the performance of MOSFETs (MOS field effect transistors), the gate length must be shortened.

It is well known that reducing the thickness of the gate oxide film is effective. The reason for this is that the gain constant β is the gate length Lg,
Gate width W g , field effect mobility μF to gate oxide film thickness t, oxide film relative permittivity, and vacuum permittivity ε. This is because it is expressed by the following equation.

Therefore, since the miniaturized MOS F E 'J'' has a larger gain constant, it has a great effect on speeding up the circuit.

However, on the other hand, such miniaturization has resulted in a decrease in the breakdown voltage of MOSFETs. Figure 1 shows the relationship between the gate length L+r of MO8FE'I' and the breakdown voltage BVDS using the gate oxide film thickness as a parameter.Even if the gate length is the same, the breakdown voltage decreases as the gate oxide film thickness becomes thinner. I understand. In Fig. 1, the gate oxide film thickness is C: 5Qn+n, △35nm, 25nm, ◇:
It represents 20nm. -4- However, in order to improve the performance of MO8I-ET, the gate length is shortened and the gate oxide film is made thinner. may become difficult.

In order to prevent such a drop in breakdown voltage, a method called the double drain method has been proposed. As shown in Figure 2, this method uses, for example, a p-type (100) plane 10Ω
A high concentration region 2 formed by doping arsenic and a low concentration region formed by doping arsenic in a silicon substrate 1 with a thickness of However, studies by the present inventors have revealed that such an IH structure does not necessarily improve the withstand voltage of the MOSFET.

In other words, as shown in Fig. 2, the actual physical channel length (effective channel length "Leu") is
) is shortened by the amount of the low concentration region 3, and the withstand voltage is therefore reduced by that amount. Since the degree of integration of the device is determined by the gate length Lg, if we try to secure the effective gate length I, @ff in order to suppress one voltage using such a square train method, we have to increase the gate length Lg. First, the degree of integration decreases. Needless to say, such a reduction in the degree of integration is extremely undesirable in terms of MO8IC design.

On the other hand, with the miniaturization of semiconductor devices, it has become necessary to reduce the junction depth of impurity diffusion layers forming source/drain regions. Generally, when the gate length Lg is about 5 μm, the junction depth is 0.7 μm, when it is 3 μm, it is 0.4 μm, and when it is 2 μm, it is 0.
．． A process is used that provides a junction depth of about 0.2 μm at 3 p m and 1.3 tt m. However, studies conducted by the present inventors have revealed that when the junction depth becomes shallow, the junction breakdown voltage decreases, and as a result, the breakdown voltage of MUII'ET also decreases. In other words, FIG. 3 is a diagram showing the relationship between junction depth and MO8FET breakdown voltage, but when junction depth x
It can be seen that the following equation approximately holds true between t and the breakdown voltage BvDS.

14VDs=20Aogx"+27 The reason for this is that as the junction depth becomes shallower, the radius of curvature of the junction becomes smaller, and therefore electric field concentration becomes more likely to occur. This tendency becomes even more remarkable in the operating state of M 08 II''l':, T.

[Summary of the invention]

The present invention was made to eliminate the problems of the prior art as described above, and it secures the effective channel length by introducing impurities into the substrate with coating glass applied to the gate region. At the same time, it is possible to sufficiently increase the radius of curvature of the source tray/region junction, and therefore it is possible to significantly improve the MO81;'ET breakdown voltage.

〔Example〕

Example 1 In the present invention, the coating properties of the coated glass are important.

Therefore, first, the coating characteristics will be explained. Figure 4 (a
), an oxide film 12 with a thickness of -Jlonm was grown by thermal oxidation on a p-type (100) plane 10ΩlIcIn silicon substrate 11, and a gas containing monotherane (SfH4) and ammonia (Nl-1,) as main components was grown. Chemical used
A silicon nitride (Si3N4) film 13 having a thickness of 15nrn was deposited by a paper deposition method (hereinafter abbreviated as CVIJ method), and 950t? The surface of the S'3N4 Jlg 13 was oxidized by wet oxidation for 30 minutes to grow an oxide film 14 with a thickness of 4 nm.
Polycrystalline Si 11: ¥15 was deposited with a thickness of 0.3 μm by the CVD method using thermal decomposition of
This shows a state in which an oxide film 16 with a thickness of 0.3 μm is grown on the polycrystalline Si film 15 by oxidizing C by wet e-oxidation. Next, as coated glass, the main component is silanol (S
Alcohol solution of i (OI-1)4), f? For example, when 0CD59310 (trade name, manufactured by Ni-Tokyo Ohka Co., Ltd.) is spin-coated at a rotational speed of 700 rpm, a coated glass layer 17 is formed as shown in FIG. 4(b). As is clear from FIG. 4(b), according to the present invention,
A thick coated glass layer 17 with a sloped cross section can be formed at both ends of the region to become the gate. In this example, the spinner rotation speed f during coating was set to 000 rpm, but it was found that it is sufficient to set it to 2000 rpm or more. The reason for this is that the ratio r = a / b of the thickness a of the coated glass layer 17 in the second part of the gate and the thickness of the coated glass layer 17 in the part 1 μm 1 l from the edge of the gate is as shown in FIG. When the rotation speed is 700 rpm or more, it is 1,
If it is less than 2000 rp, it will be less than 0.5. Therefore, when removing the coated glass layer on the substrate, the coated glass layer formed at both ends of the gate and having an inclined cross section will also be removed, resulting in a good result. This is because the semiconductor device is formed into an inner cone.

Example 2 As shown in FIG. 6(a), the p-type (100) surface was
The well-known 1. A field oxide film 22 with a thickness of 0.6 μm is grown by the ocos method, and then a field oxide film 22 with a thickness of 20 nm is grown. 95 sintered film 23
It was grown by dry oxidation at 0C for 20 minutes, and po'yS I was deposited to a thickness of 0.35 tt m by method C1).
After thermally diffusing phosphorus, the gate 24 is shaped by photoetching.
I did. Next, as shown in No. 6F+(b), 0CD59000 (previous product name manufactured by Nitokyo Nka) was spin-coated at a rotational speed of 500 Orpm as a coated glass, and the gate f
A coated glass layer 25 having a sloped cross section in the llQ portion was formed and annealed for 20 minutes in a nitrogen atmosphere. The upper surface of the gate oxide film 23 and the gate 24, . 1. The coated glass layer 25 of : hydrofluoric acid: ammonium fluoride = 1:20
Arsenic (As) was removed by etching with a solution of
m-2 implantation and another 1000t? After nitrogen annealing for 30 minutes, the substrate 21 is heated as shown in FIG. 6(C).
An arsenic diffusion layer 26 with a junction depth of 0.4 μm and a nine-layer resistance of 25 Ω/'' was formed within the arsenic diffusion layer 26.The radius of curvature at the end of the arsenic diffusion layer 26 formed in this way was that of a normal MO8.
If an IC process was used, the thickness would be 0.4 μm, and the junction breakdown voltage would be about 18V, but it was found that since the thickness could be 1 μm or more, the junction breakdown voltage could be significantly improved to 26V. Furthermore, by appropriately selecting the 92 cloth conditions for the coated glass and the annealing conditions for the arsenic ion implantation layer,
Arsenic diffusion layer 26! 11A+% (S is not brought into contact with the gate 24. Since it is possible to have a so-called offset structure, a skewer that further improves the withstand voltage of MOS JI''1.:T can be created. This off-sera h
This is an example of a rlh manufactured M OS I'''ET, and the lateral inner depth of the arsenic diffusion layer is 0.4 μm, but the coated glass layer 2
5 is 1 tt m pH (c i +
Since the gate 24 is formed with a 0.6 μm on-line set portion 27 on both sides of the gate 24,
．． stomach). The length of the offset portion 27 can be controlled by the coating conditions of the coated glass, the ion implantation conditions, and the annealing conditions. Therefore, it is possible to easily control the breakdown voltage of the MOSFET as required.

Example 3 Phosphorus is diffused into the offset portion formed in Example 2 to form a low concentration n-type layer, and MOS F E
The so-called double drain structure improves the withstand voltage of T.
This can be realized without shortening the effective channel length as shown in FIG. FIG. 7 shows this example, and in FIG. 6(C), the coated glass layer 25 is removed and oxidized to form a re-oxidized film 27. The re-oxidation film 27 is formed to improve the gate breakdown voltage and is not necessarily essential. In this example, ioo.

An oxide film with a thickness of 200 m was grown by dry oxidation of C. Furthermore, phosphorus ions were
x 10" cm-2 implant, annealed at 100OU for 20 minutes. As a result, a junction depth of 0.4 μm single layer resistor 2
A phosphorus diffusion layer 28 of 1M08FE is formed with a resistance of 00Ω/mouth.
The withstand voltage of T was significantly improved.

In this example, the withstand voltage at a gate voltage of 5 V was improved by 50% from 4 V to 6 .mu.m in a device with a gate length of 11 .mu.m.

Example 4 In Example 3, phosphorus ion implantation was performed to form a phosphorus diffusion layer, but instead of ion implantation,
It is also possible to carry out phosphorus diffusion from the coated glass layer.

FIG. 8(a) kl5, tP, field oxide film; 31, gate oxide film 32, on substrate 30 in the same manner as in FIG.
At 1111' when the gate 33 was formed, OCD59340 (containing 8 mole % of Nilin, manufactured by Nito Ohka Co., Ltd., trade name) was spin-coated as a coated glass at 500 rpm to form a coated glass layer 34. 95
Nitrogen annealing was performed at 0C for 20 minutes to form a low concentration diffusion layer 35 of phosphorus from the coated glass layer 34 into the substrate 31 as shown in FIG. 8(b). The resulting low concentration diffusion layer 35 had a junction depth of 0.2 μm and a layer resistance of 500Ω/hole.

Part of the coated glass layer 34 and gate oxide film 32 is removed using an etchant containing a mixture of hydrofluoric acid and ammonium fluoride at a ratio of 1:20, and then an oxide film 36 with a thickness of 20 nm is grown by wet oxidation at 900C. Then, by ion implantation, arsenic was implanted at 80 keV at I.times.10"crn" and annealed at 950 C for 20 minutes to form an arsenic diffusion layer 37 as shown in FIG. 8(C). The junction depth υ of the arsenic diffusion layer 37, 1: 0.25 μm1, and the junction depth of the low-degree diffusion layer 35 was 0.2 μm.
As is clear from the figure (cl), according to the present invention, the reduction in the effective channel length from the gate length is small, and therefore the effect of improving the breakdown voltage is large.N = IOS with a gate length of 1 μm.
When comparing FET, it was possible to achieve an increase in lateral pressure of 2 V or more compared to the case formed by the method of Yoko.

Example 5 In the example described in -1-, polySi was used as the gate, but for example, MoSi2. WS i, , ,
It is also possible to use metal silicides (hereinafter abbreviated as silicides) such as 'I'iS i2, metals such as Mo and W (hereinafter abbreviated as metals), and combinations of these materials.

In this example, polycrystalline Si (0.2μ
On top of that, Mo5t2 was deposited to a JW of 0.2 μm using a sputtering method, and 2 μm was deposited at 950C.
A gate was formed by annealing in a nitrogen atmosphere for 0 minutes. In this case as well, the same effect of improving the breakdown voltage as in the above example was obtained.

The coated glass used in the present invention is generally called spin-on glass, and various types are also known. [Effects of the Invention] The present invention has been described with reference to the above embodiments; - Also, according to the present invention, the thickness of the glass layer on the side of the gate is 1゛I? By forming a coated glass layer of Single drain or offset gate structures are easily realized.

[Brief explanation of the drawing]

Figure 1 shows the gate length and ■＼40 S F'E'I'1
Figure 2 is a diagram showing MO8FF and T formed by the conventional method. Figure 3 is a diagram showing the relationship between bonding depth and suppression. Figures 4 to 8 2A and 2B are diagrams for explaining the invention in detail, respectively. 1.11,21. ．． 30...Silicon substrate, 4,15
゜24.33...Gate, 5, 12, 14, 27゜3
2... Gate oxide film, 22.31... Field oxide film, 17, 25.34... Coated glass film, 16°2
7.36...Re-1 oxidation film, 2,26.37...High concentration 1st figure 'JfQa, Shen Yunso Moxibustion (Hyptn,) Fig.
(Tue) Mootsu Figure (b) 2/f Taku 7 Figure 21 γ 8 Mouth (Ri Figure 8 (b)

Claims (1)

[Claims] 1. A step of forming a source and a drain by introducing impurities into a semiconductor substrate through coated glass layers formed on the sides of a gate and having different thicknesses. A method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is introduced by ion implantation. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity is introduced by thermally diffusing the impurity contained in the coated glass layer.