JPS5947767A - Mis type semiconductor element - Google Patents
Mis type semiconductor elementInfo
- Publication number
- JPS5947767A JPS5947767A JP15681682A JP15681682A JPS5947767A JP S5947767 A JPS5947767 A JP S5947767A JP 15681682 A JP15681682 A JP 15681682A JP 15681682 A JP15681682 A JP 15681682A JP S5947767 A JPS5947767 A JP S5947767A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- source
- channel
- schottky
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910000838 Al alloy Inorganic materials 0.000 claims description 2
- 108091006146 Channels Proteins 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 9
- 108010075750 P-Type Calcium Channels Proteins 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 235000015067 sauces Nutrition 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 241000254158 Lampyridae Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 1
- 229910001245 Sb alloy Inorganic materials 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 239000002140 antimony alloy Substances 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- XQCUWCZUYXJXRL-UHFFFAOYSA-N copper dioxosilane Chemical compound [Si](=O)=O.[Cu] XQCUWCZUYXJXRL-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 239000011591 potassium Substances 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 230000009182 swimming Effects 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】 本発明はＩＶｆＩｌし牛尋体素子に関する。[Detailed description of the invention] The present invention relates to an IVfl body element.
ＭＩＳ形半導体素子、特にＩＶＩＯ３形半専体累千はｊ
Ｐ純な構造ケ持ち、製作が容易であることから、集積回
路に多用ちれている。従来一般に用いられているＩＶＩ
Ｏ８形半導体素子盆スケールダウン則に基ついて倣卸１
化するには、ナヤ不ル長の微細化に伴なって生じるショ
ートナヤネル効果、例えばしきい値電圧の低下等電防止
１°る心安がある。これは、基板中に形成したソースＰ
よひドレイン（以下ではソース・ドレインと略称する）
の拡散層深さを浅くすることにより実現さ７Ｌる。しか
し、ソース参トレインの拡散層を浅くするとソース・ド
レイン抵抗か増太し、ドレイン電流の低下等、素子峰性
會劣化させるという欠点がめった。MIS type semiconductor devices, especially IVIO3 type semi-dedicated
Because it has a simple structure and is easy to manufacture, it is widely used in integrated circuits. Conventionally commonly used IVI
O8 type semiconductor device tray imitation wholesale 1 based on scale down rules
In order to achieve this, there is peace of mind that the short Nayanel effect that occurs with the miniaturization of the Naya irregular length, for example, the isoelectric reduction of the threshold voltage, can be prevented by 1°. This is the source P formed in the substrate.
Yohi drain (hereinafter abbreviated as source/drain)
This is achieved by reducing the depth of the diffusion layer of 7L. However, when the diffusion layer of the source reference layer is made shallow, the source/drain resistance increases, resulting in a decrease in drain current and other drawbacks, such as deterioration of device peak characteristics.
上記問題を解決する方法として、ソース・ドレインに金
屑または金鵜シリツーイドのショットキ接触を用いた、
いわゆるショットキソース・ドレインＭＯ８形半導体素
子が提案されている。As a method to solve the above problem, a Schottky contact of gold scrap or gold silitoid is used for the source and drain.
A so-called Schottky source-drain MO8 type semiconductor device has been proposed.
この方法は、ソース・ドレインに金属または金属シリサ
イドを用いることから、ソース・ドレイン抵抗を小さく
できると共に、ソース・ドレインが基板中に形成さ゛れ
ていないため、ショートチャネル効果を抑制できる。し
かし、ショットキソース・ドレインＭＯ８形半導体素子
では第１図のｎチャネルでの等価回路に示すように、ソ
ース２とチャネル５の間にショットキ障壁４が形成され
る。このため、ゲート１にオン電圧が印加された時、電
荷担体はソース２からショットキ障壁４を乗り越えてチ
ャネル５に注入されねばならない。したがって、ショッ
トキソース・ドレインＭＯ８形半導体素子では、ソース
・ドレインに拡散層音用いチャネルに対してオーム性接
触會有するＭＯ８形半導体素子に比ベトレイン電流が小
さいという欠点がめった。なお３はドレインを示す。Since this method uses metal or metal silicide for the source and drain, it is possible to reduce the source and drain resistance, and since the source and drain are not formed in the substrate, the short channel effect can be suppressed. However, in the Schottky source/drain MO8 type semiconductor device, a Schottky barrier 4 is formed between the source 2 and the channel 5, as shown in the n-channel equivalent circuit of FIG. Therefore, when an on-voltage is applied to the gate 1, charge carriers must be injected from the source 2 over the Schottky barrier 4 into the channel 5. Therefore, the Schottky source/drain MO8 type semiconductor device often has the disadvantage that the train current is small compared to the MO8 type semiconductor device which has ohmic contact with the source/drain diffusion layer channel. Note that 3 indicates a drain.
本発明はチャネルに対してオーム性接触、基板に対して
ショットキ接触とするソース・ドレインを用いることを
特徴とし、その目的はソース舎ドレイン抵抗を増大させ
ることなくショートチャネル効果を抑制し、スケールダ
ウンされたｔＩＳ形半導体素子を提供するにある。The present invention is characterized by using a source/drain having an ohmic contact with the channel and a Schottky contact with the substrate.The purpose of this invention is to suppress the short channel effect without increasing the source/drain resistance and to reduce the scale. An object of the present invention is to provide a tIS type semiconductor device.
前記の目的を達成するため、本発明ｅまチャネルに対し
てオーム性接触、基板に対してショットキ接触とするソ
ースおよびドレインに用いることを特徴とするＭＩＳ形
半導体素子全発明の狭口とするものである。In order to achieve the above object, the present invention provides an MIS type semiconductor device characterized in that it is used for the source and drain with ohmic contact to the channel and Schottky contact to the substrate. It is.
次に本発明の実施例全添附図面についてｈ発明する。な
お実施例は一つの例示であって、本発明の精神を逸脱し
ない範囲内で、柚々の変更あるいは改良を行いうろこと
は１うまでもない。Next, embodiments of the present invention will be described with reference to all attached drawings. Note that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.
前述したように、ショットキソースドレインＭＯ８形半
導体素子は、ソース・ドレイン抵抗を小さくできると共
にショートチャネル効果が抑制できるので、スケールダ
ウンしたＭＯ８形半導体素子に適した構造である。しか
し、ソースとチャネルの間にショットキ障壁が存在する
ため、ドレイン電流が小さいという欠点がめる。As described above, the Schottky source-drain MO8 type semiconductor device is suitable for a scaled-down MO8 type semiconductor device because the source/drain resistance can be reduced and the short channel effect can be suppressed. However, since there is a Schottky barrier between the source and the channel, there is a drawback that the drain current is small.
本発明の要点は上記のショットキソース・ドレインｔｅ
ｌ ＯＳ形十４Ｉ体素子の利点を保持し、欠点でア４）
ソースとチャネルの間のショットキ障壁倭取り除くため
、ソースとチャネルヶオーム性接触としたことにるる。The main point of the present invention is the above-mentioned Schottky sauce drain.
l Maintains the advantages of the OS type 14I body element, but eliminates the disadvantages of A4)
In order to eliminate the Schottky barrier between the source and the channel, ohmic contact is made between the source and the channel.
以１、実施例により成用する。The following 1 is accomplished based on the examples.
〔実施？ｌ１１〕
第２図？−１、本発明の一実施例ケ示すものであって、
ｐチャネルのｉｖｔ ＯＳ形半導体素子の−１面を示す
。図において、１０は不純物鋲度２ ｘ ｌｏ” ／副
３のｎ形シリコン基板、ｌｌは二酸化シリコンの素子分
離、１２は多結晶シリコンのケート、１３はアルミニウ
ムのソース拳ドレイン、１４は二酸化シリコンのケート
絶縁物お・よびソース嗜ドレイン１３とケート１２の分
離である。１５はｐ形のチャ不ルヲホす。に４のアルミ
ニウムのソース・ドレインｖ；Ｊ１、ｎ形シリコン基板
１０に対してはショットキ接触となシ、１５の部分に形
りにされるｐ形のチャネルに対し１はメーム性接触とな
るため、従来のショットキソース・ドレインｙｈｏｓ形
半ｍ体銅矛に児られるドレイン電流が小δいという欠点
は見とめられず、ソース・ドレインに拡散層を用いたＭ
Ｏ８形十形半導体の特性か有られた。一方、ソース・ド
レイン■（抗はソース・ドレインにアルミニウム音用い
たことから小芒くできる。塘た、ショートテヤイ・ル効
釆も生じにくいことか判かり、本発明の方法かイ１幼ｌ
ことが確認できた。〔implementation? l11] Figure 2? -1. One embodiment of the present invention is shown,
The -1 plane of a p-channel ivt OS type semiconductor device is shown. In the figure, 10 is an n-type silicon substrate with an impurity concentration of 2 x lo" / sub-3, 11 is a silicon dioxide element isolation, 12 is a polycrystalline silicon gate, 13 is an aluminum source and drain, and 14 is a silicon dioxide silicon substrate. The gate insulator and the separation of the source/drain 13 and gate 12 are shown in FIG. However, since the p-type channel formed in the part 15 becomes a memetic contact, the drain current generated in the conventional Schottky source drain yhos half-m copper spear is small δ. No drawbacks were observed, and M using diffusion layers for the source and drain
It has the characteristics of an O8 type 10 type semiconductor. On the other hand, the source/drain resistor can be made small because aluminum is used for the source/drain.It is clear that the short-circuit effect is also less likely to occur, and the method of the present invention is
This was confirmed.
〔実施例２〕
第３図は本発明の他の実施例紫ボすものであって、ｎチ
ャネルのＭ ＯＳ形半導体素子の断四會示す６図に２い
て２０は不純物も（度２刈０” ／ ｔｔｎ”のｐ形シ
リコン基板、２１は二酸化シリコンの銅矛分離、２２は
多結晶シリコンのケート、２３はモリブデンシリサイド
のソース・トレイン、２４はヒ素のイオンナ］込魯で形
成したｎ形層、２５はアルミニウムの配線、２６は二酸
化シリコンのケート絶縁物υ」、ひソース・ドレイン２
３とゲート２２の分離である。ｎ形）５７２１はソース
・トレイン２３が零バイアス時において、完全に窒乏化
づ一°るよう、凝度寂よひ深さが決められで↓・り、ｐ
形シリコンノ、１、ｌｌｉ Ｖ（一対うるショットキ１
Ｍ１（壁全Ｊ−１／ｊ’ ） ｎ７１’−チャイ・ル
Ｖ（Ｚり・」１−るショットキ障壁全下ける。[Embodiment 2] Fig. 3 shows another embodiment of the present invention shown in purple. 0"/ttn" p-type silicon substrate, 21 is silicon dioxide copper separation, 22 is polycrystalline silicon gate, 23 is molybdenum silicide source train, 24 is n-type formed with arsenic ionizer. layer, 25 is aluminum wiring, 26 is silicon dioxide gate insulator υ', source/drain 2
3 and gate 22. n type) 5721, the concentration depth is determined so that the source train 23 is completely depleted at zero bias.
Shape Silicono, 1, lli V (pair Uru Schottky 1
M1 (all walls J-1/j') n71'-Chai Le V (Z-ri-'1-') Schottky barrier all lowered.
したかつて、Ｊシリブナンシリサイトのソース噂ドレイ
ン２二３ｅコ、ｐＪレシリコン基板２０に対してショッ
トキ接触となり、２７の部分Ｖこ形成さ扛るｎ形のナヤ
イ・ルに対しでスーム性接触となるため、従来のンヨッ
トキソース・ドレイン■１０Ｓ形半尋体系子に兄ら７’
Ｌるドレイン７（Ｌ流か小恥いといり欠点ｔｘｔ、児と
めらｒｌ、ず、ソース・ドレインに拡散胎を月１いた１
１／１０Ｓ形半導体素子の特４１が得られた。−力、ソ
ース・ドレイ７１−ＦＬ Ｊ九〇」ソース・ドレインｉ
／（１％リブアンシリサイド′忙用いグにとから小さく
でさる。寸だ、ショートチャネル効果も生じにくいこと
が刊かシ、＋、光明の力泳が自効なことかイ１ｆ（ｉ
ｍ−Ｃさた。Once, the source rumored drain 223e of J silicon silicite was in Schottky contact with the pJ resilicon substrate 20, and a smooth contact was made with the n-type Nayole forming the part V of 27. In order to become
L drain 7 (L style or a little shameful flaw txt, child and mera rl, zu, I had a spread womb in the source and drain once a month 1
A 1/10S type semiconductor device, Part 41, was obtained. -Power, Source Dray 71-FL J90” Source Drain i
/(1% Libunsilicide'It's small enough for busy people. It's obvious that the short channel effect is not likely to occur. +, Komei's force swimming is self-effective.
m-C sata.
上記の実施例１ではソース・ドレインにアルミニウムＴ
ｈ Ｊｉｌいｆｃが、アルミニ３ツムとシリコンの合金
々ｊ１、アルごニツム合金か用いつる。−刀、１）チャ
ネル（１） ｒｖｔ ＬＪ Ｓ ）ｉ；牛尋体素ゴに対
し、 −Ｃｒ：Ｊ５、アンチモンわるい＆Ｊアンナモン
と蛍の合金等のアンチモン合金か用いンる。In the above embodiment 1, aluminum T is used for the source and drain.
h Jil fc uses alloys of aluminum and silicon, and aluminum alloys. - Sword, 1) Channel (1) rvt LJ S ) i; For Ushijintai Sogo, - Cr: J5, antimony alloy such as antimony wari & Jannamon and firefly alloy is used.
」二Ｍ１．’ｉの尖７／ｉ！Ｉ抄り２ではソース・トレ
インｅ（七すブプ°ンシリザイド會用いｌこが、チタン
シリザイド、ニッケルシリーリイド等の−ｊ＆的な金稙
シリザイド、−またはそリプブン、チタン、ニッケル等
の御飯的な全組か用いうる。ｎｊしＪｆｇｉの形成にヒ
素のイオン打ち込みを用いたが、リン、アンチモンのイ
オン刊込みか用いつる。また、気相拡散等の拡散法介・
用いることも一〇きる。−ツバｐチャネルのＭ ＯＳ形
半縛Ｊ体素づ−に刈してはｎ形層のかわしにｐ形層電相
いＩ’Ｌ、 ？、Ｉよく、ホウ素。”2M1. 'i no cusp 7/i! In Section 2, the source train e (seven silicides), titanium silicide, nickel silicide, etc. Although arsenic ion implantation was used to form nj and jfgi, phosphorus and antimony ion implantation could also be used.Also, diffusion methods such as gas phase diffusion,
It can be used ten times. - The p-channel MOS type half-bound J body is cut in half, and the n-type layer is replaced by the p-type layer I'L,? , I well, boron.
カリウム等のイオン打込みか用いう／）。−りだ、気相
拡散等の仏散法が用い９る。Use ion implantation such as potassium. - Buddha-san methods such as Rida and vapor phase diffusion are used9.
本発明は、しさい仙電圧調」シー寺の／Ｃめ、チャイノ
１の形成さ扛る領域に不＊Ｉｉｉ物虻イオン打込外した
、いわゆるナヤイ・ルドーノＮｌｏ ｓ形半ｚｊｌ、体
系子にも同４求に通用ｔさ４）。The present invention is based on the so-called Nayai Rudno Nlo s-shaped half-zjl, which is the so-called Nayai Rudno Nlo s-shaped half zjl, in which the non-*III ions are implanted into the area where the chino 1 is formed. It is also valid for the same question 4).
取手簡明しｔ（ように、チャネルに幻り、、 −（：
＊−ム祉猛触、基板に対ｔ７−（ショラミ゛キ払触とな
るソース−ドレイン會ハ」いているので、従来のショッ
トキソース祷ドレインＩ’＋１ ＯＳ形半専体素子に特
有のトレイン篭ωｔか小さいという欠点會生じることか
くソース・ドレイン抵抗を小３くでさ４）と共ＶＣ１シ
ョートナヤイ・ル効朱−ｅ ＋ｐ（１制できる４・す点
かめる。ａらに、本発明のＭＵＳ形半導体系すをＣＩＶ
ＩＯ８情成で用いｇは、ソース−ドレインと基板との接
触がショットキ接触であることから、基４μに形ｈ）ｊ
、さ扛る寄生バイポーラへの少数キャリア注入か抑制さ
れる／こめラッチアップか用Ｊ匍ｊされるオリ点がある
。Toride simplification t (like, illusion in the channel,, -(:
* Since there is a t7- (source-drain meeting that causes severe contact with the board), the conventional Schottky source drain I'+1 train cage peculiar to the OS type semi-dedicated element Therefore, the source/drain resistance is reduced to a small value (4), and the effect of the VC1 short circuit is also small. MUS type semiconductor system CIV
The g used in the IO8 configuration has the form h)j in the base 4μ since the contact between the source-drain and the substrate is a Schottky contact.
, there is an origin point where minority carrier injection into the parasitic bipolar is suppressed/latch-up is suppressed.
以上の祝す」でりＩＶｌ（ＪＳ形牛尋体系予の４に一自
及したか、ＭＯＳ形にととｌらずケート絶λぺ狭として
窒化シリコン膜など會用い／こ１■Ｉｓ形半尋体素士全
触＆０わ１こ９本発明を襲用しうるξとは自明でりる。I would like to congratulate you on the above IVl (JS type gyro system design 4). It is self-evident that ξ can be applied to the present invention.
４、区間の１ハ１年な成力
第１図Ｑよソース・ドレインにショットキ接触を用い７
ＣｎチャネルのＩＶＩ Ｕ Ｓ形午導体素子の等側回路
、第２図は本元印」の−実施例である牛４俸累子のＩＩ
／ｌ−１１１１図、第３図をユ本発明の他の実施例であ
る半導体素子の）！ｊＴ ’Ｉ川用を示す。4. Section 1 is 1-year formation power Figure 1 Q Using Schottky contact for source and drain 7
Cn channel IVI U S-shaped conductor element equilateral circuit, Fig. 2 is an example of the original seal II
/l-1111 and FIG. 3 of a semiconductor device which is another embodiment of the present invention)! jT 'I River use is shown.
■・・・・・・ケート、２・・・・・・ソース、３・・
・・・・ドレイン、４・・・・・・ショットキ障壁、５
・・・・・チャネル、ＩＯ・・・・・・シリコン基板、
１１・・・・・・系子分丙１３．１２・・・・・・ケー
ト、ｌ：ｒ・・・・ソース−トレイン、１４・・・・ゲ
ートｅ 様？／Ｉνよびソース・ド１／インとケートの
分’４１’ｉ Ｘ１６・・・・・・チャネル、２０・・
・・・・ンリコン基４Ｒ１２１・・・・・・素子分離、
２２・・・・・・ケー１−１２３・・・・・・ソース・
ドレイン、２４・・・・・・ｎ ｙｌジノ【Ｉ、２５・
・・・・ｈ己かＲ１２６・・・・・・ゲート絶縁物およ
びソース・ドレインとゲートの分離、２７・・・・・・
チャネル
特ｒ「出願人 Ｈ本電１０′屯砧公社■...Kate, 2...Sauce, 3...
...Drain, 4...Schottky barrier, 5
...Channel, IO...Silicon substrate,
11... System molecule C 13. 12... Kate, l:r... Source-train, 14... Gate e? /Iν and source do 1/in and Kate's minute '41'i X16... Channel, 20...
...Nricon group 4R121...Element separation,
22・・・・・・K1-123・・・・・・Source・
Drain, 24...n yl Jino [I, 25.
....R126...Gate insulator and separation of source/drain and gate, 27...
Channel special r "Applicant H Honden 10' Tunkei Public Corporation
Claims (1)
てショットキ接触とするソースおよびドレイン全相いる
こと全特徴とするパノｉＩＳ形半導体素子。 （２ｊ ｐチャネルに対しては、アルミニウムあるい
はアルミニウム合金ｋＸ”チャネルに対しては、アンチ
モンめるいＱまアンナモン合金をソース２よびドレイン
に用い、チャネルに対し１オーム性接触、基板に対し１
シヨツトキ接触とすることを特徴とする特ｆｆ論求の範
囲第１項記載のＭＩｓ形半導体累子。 （３２ソース近傍２よひドレイン近傍にｐチャネルに対
してｆｌｐｔｋ層、ｎチャネルに対してはｎ形層を形成
し、チャネルに対してメーム性接触、基板に対してショ
ットキ政触とすることを特徴とする％ＦＦ紬求０範囲第
１項記載のＭＩＳ形十専体素子。(1) -C ohmic contact to the channel, to the substrate,
A pano-iIS type semiconductor device characterized in that all phases of the source and drain are made into Schottky contacts. (For the 2j p-channel, aluminum or aluminum alloy k
The MIs type semiconductor resistor according to item 1 of the scope of the special ff discussion, characterized in that it has a shot contact. (32) Form a flptk layer for a p-channel and an n-type layer for an n-channel near the source and 2-drain near the drain, and make memetic contact with the channel and Schottky contact with the substrate. The MIS type decadal element as described in item 1, characterized by %FF 0 range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15681682A JPS5947767A (en) | 1982-09-10 | 1982-09-10 | Mis type semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15681682A JPS5947767A (en) | 1982-09-10 | 1982-09-10 | Mis type semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5947767A true JPS5947767A (en) | 1984-03-17 |
Family
ID=15635957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15681682A Pending JPS5947767A (en) | 1982-09-10 | 1982-09-10 | Mis type semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5947767A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181669A (en) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | Mos type semiconductor device |
| JPS61129863A (en) * | 1984-11-28 | 1986-06-17 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JP2007049182A (en) * | 1999-12-16 | 2007-02-22 | Spinnaker Semiconductor Inc | System and method of mosfet device |
| US7358550B2 (en) | 2004-03-26 | 2008-04-15 | Kabushiki Kaisha Toshiba | Field effect transistor |
| US7589381B2 (en) | 2003-09-05 | 2009-09-15 | Kabushiki Kaisha Toshiba | Field effect transistor and manufacturing method thereof |
| JP2010045394A (en) * | 2003-09-05 | 2010-02-25 | Toshiba Corp | Field-effect transistor and method of manufacturing the same |
| US9140365B1 (en) | 2012-09-11 | 2015-09-22 | Engineered Seal Products, Inc. | Outer seal |
| US9423030B2 (en) | 2007-04-27 | 2016-08-23 | Deere & Company | Outer pin seal |
| US20160377180A1 (en) * | 2015-06-24 | 2016-12-29 | Engineered Seal Products, Inc. | Double sided outer seal |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5766671A (en) * | 1980-10-09 | 1982-04-22 | Fujitsu Ltd | Semiconductor device |
-
1982
- 1982-09-10 JP JP15681682A patent/JPS5947767A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5766671A (en) * | 1980-10-09 | 1982-04-22 | Fujitsu Ltd | Semiconductor device |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181669A (en) * | 1983-03-31 | 1984-10-16 | Toshiba Corp | Mos type semiconductor device |
| JPH055184B2 (en) * | 1983-03-31 | 1993-01-21 | Tokyo Shibaura Electric Co | |
| JPS61129863A (en) * | 1984-11-28 | 1986-06-17 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JP2007049182A (en) * | 1999-12-16 | 2007-02-22 | Spinnaker Semiconductor Inc | System and method of mosfet device |
| JP2010045394A (en) * | 2003-09-05 | 2010-02-25 | Toshiba Corp | Field-effect transistor and method of manufacturing the same |
| US7589381B2 (en) | 2003-09-05 | 2009-09-15 | Kabushiki Kaisha Toshiba | Field effect transistor and manufacturing method thereof |
| US7479674B2 (en) | 2004-03-26 | 2009-01-20 | Kabushiki Kaisha Toshiba | Field effect transistor |
| CN100446271C (en) * | 2004-03-26 | 2008-12-24 | 株式会社东芝 | Field effect transistor |
| US7358550B2 (en) | 2004-03-26 | 2008-04-15 | Kabushiki Kaisha Toshiba | Field effect transistor |
| US9423030B2 (en) | 2007-04-27 | 2016-08-23 | Deere & Company | Outer pin seal |
| US9140365B1 (en) | 2012-09-11 | 2015-09-22 | Engineered Seal Products, Inc. | Outer seal |
| US9879783B1 (en) | 2012-09-11 | 2018-01-30 | Engineered Seal Products, Inc. | Outer seal |
| US20160377180A1 (en) * | 2015-06-24 | 2016-12-29 | Engineered Seal Products, Inc. | Double sided outer seal |
| US10520094B2 (en) | 2015-06-24 | 2019-12-31 | Engineered Seal Products, Inc. | Double sided outer seal |
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