JPS5946869A - プリント板の診断方法 - Google Patents

プリント板の診断方法

Info

Publication number
JPS5946869A
JPS5946869A JP57157772A JP15777282A JPS5946869A JP S5946869 A JPS5946869 A JP S5946869A JP 57157772 A JP57157772 A JP 57157772A JP 15777282 A JP15777282 A JP 15777282A JP S5946869 A JPS5946869 A JP S5946869A
Authority
JP
Japan
Prior art keywords
flip
log
flops
bits
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57157772A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0233105B2 (enExample
Inventor
Hisao Hidaka
日高　久男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57157772A priority Critical patent/JPS5946869A/ja
Publication of JPS5946869A publication Critical patent/JPS5946869A/ja
Publication of JPH0233105B2 publication Critical patent/JPH0233105B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
JP57157772A 1982-09-10 1982-09-10 プリント板の診断方法 Granted JPS5946869A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57157772A JPS5946869A (ja) 1982-09-10 1982-09-10 プリント板の診断方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57157772A JPS5946869A (ja) 1982-09-10 1982-09-10 プリント板の診断方法

Publications (2)

Publication Number Publication Date
JPS5946869A true JPS5946869A (ja) 1984-03-16
JPH0233105B2 JPH0233105B2 (enExample) 1990-07-25

Family

ID=15656958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57157772A Granted JPS5946869A (ja) 1982-09-10 1982-09-10 プリント板の診断方法

Country Status (1)

Country Link
JP (1) JPS5946869A (enExample)

Also Published As

Publication number Publication date
JPH0233105B2 (enExample) 1990-07-25

Similar Documents

Publication Publication Date Title
US4583169A (en) Method for emulating a Boolean network system
US5291495A (en) Method for designing a scan path for a logic circuit and testing of the same
CN1035191A (zh) 测试和故障检查基于微处理器的电子系统的存贮器仿真方法和系统
NO317781B1 (no) System for bruk i grensesnitt-testere med adresseavhengige instruksjoner
US20070005323A1 (en) System and method of automating the addition of programmable breakpoint hardware to design models
US4847838A (en) Circuit for testing the bus structure of a printed wiring card
US4156132A (en) Automatic fault injection apparatus and method
Manning On Computer Self-Diagnosis Part I-Experimental Study of a Processor
JPS5946869A (ja) プリント板の診断方法
CA1182579A (en) Bus sourcing and shifter control of a central processing unit
US6675323B2 (en) Incremental fault dictionary
US7523367B2 (en) Method and apparatus to verify non-deterministic results in an efficient random manner
JPH0561931A (ja) シミユレーシヨン装置
CN114676064B (zh) 一种面向硬件语言代码的通用测试系统和方法
Moussouris et al. CHEOPS: A chess-oriented processing system
US12461151B2 (en) Method and system for testing blocks within device under test (DUT) using reconfigurable test logic
Szygenda et al. Fault insertion techniques and models for digital logic simulation
Al-Asaad et al. ESIM: A multimodel design error and fault simulator for logic circuits
JP2964746B2 (ja) プリント板回路の自動検証処理方法
Wang et al. A new validation methodology combining test and formal verification for PowerPC/sup TM/microprocessor arrays
JPH08136614A (ja) 回路試験装置
Giambiasi et al. SILOG: a practical tool for large digital network simulation
JP2642265B2 (ja) 論理回路のテストパターンの検査方法
Wang et al. Test generation based on high-level assertion specification for PowerPCTM microprocessor embedded arrays
JPS63205760A (ja) 論理シミユレ−シヨンのテストカバレ−ジ方式