JPS5946010B2 - Auto clear circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an auto clear circuit, and is mainly directed to a circuit used in a printer electronic desktop calculator (hereinafter referred to as a printer calculator).

When turning the power on and off in a printer calculator, a circuit was used to clear the internal state of the circuit when the power was turned on.

This clear circuit was reset by operating the input key. However, it is desirable that the clear circuit be automatically reset without the initiation of a key operation. Due to the automatic reset of the rear circuit itself,
It is possible to have the printer calculator perform tasks such as printing before starting key operations. The present invention is intended to meet such demands, and its purpose is to provide a novel auto-clear circuit that can automatically perform a clearing operation.

One embodiment of the invention to achieve the above object is a power sign driven by a first clock pulse.

an application switching means, a level shift means to which power is applied via this switching means, a switching means provided on the reference potential terminal side to which the output of this level shift means is applied, and this switching means and a power supply voltage The latch circuit is provided between the latch circuit and the terminal and is driven by a second clock pulse that does not overlap with the first clock pulse, and the output is taken out from the output point of the latch circuit. do. The present invention will be specifically described below with reference to embodiments and drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The figure shows an insulated gate field effect transistor (FET)
), which uses a power supply to which a clock pulse φ is applied - VDD application -
I and the FET to which power is applied through this FETTI
A level shift circuit 1 consisting of T3 and T4, and a reference potential (
A FET T8 connected to the ground) terminal side and driven by the output of the level shift circuit, and a latch circuit 2 (
FETs T5, T7, T9, and Tlo), and the output Vout from the output point of this latch circuit 2
It is to take out.

Note that the FE connected in parallel to the power supply FETTI
TT2 is for discharging the charge existing in FET T3 of the level shift circuit when the power switch is turned off. In addition, FET T7 constituting the latch circuit 2
A FET T6, which is provided in parallel with and driven by clock pulse φ2, is for resetting this latch circuit. All FETs in this circuit are p-channel FETs, especially FETs T4, T5, T9 are depletion type, and other FETs (Tl, T2, T3, T6, T
7, T8) is an enhancement type. FIG. 2 is a timing chart for explaining the operation of the above circuit.

The operation will be explained below using the same figure. First, the power switch (not shown) is turned on and the voltage drops from the GND (ground) level to -
When the voltage rises to the VDD level, no voltage is generated in the level shift circuit at this time, so FET T8 is off.

Therefore, the latch circuit 2 is set, and the output V
Out is at GND level (period t1-T2)
. Next, when clock pulse φ1 rises, switching FE
TTl is turned on, and the potential Va at the input point of the level shift circuit rises. Therefore, the output Vb of the level shift circuit
It also rises with a little delay (period T2-T3). When the output Vb of this level shift circuit reaches a certain value, the switching F
ETT8 turns on. At this stage, the clock pulse φ2
When V rises, latch circuit 2 is reset and its output V
-VDD level is generated at Out (period T4). Therefore, when the latch circuit is in the set state, the output VOut
(If the GND level control is used as a clear signal and the state at reset is used as a release signal, it can be used as an auto clear circuit and the purpose can be achieved.If the circuit is configured as above, if Even if φ1 and φ2 rise at the same time when the power is turned on, since the level shift circuit 1 controls FET T8, it takes some time until the voltage reaches the logic threshold voltage that turns FET T8 on, which may cause malfunction. There isn't.

Furthermore, even if the clock pulse φ2 rises before the clock pulse φ1, the latch circuit 2 will not be erroneously set because the FET T8 is not turned on. For this reason, this circuit also has the advantage of a large noise margin. FIG. 3 is a circuit diagram showing an application example of the auto clear circuit of the present invention.

FIG. 3A is a circuit diagram in which the auto clear circuit 3 of the present invention and the counter circuit 4 are coupled via an inverter GO. Note that the logic combinational circuit 5 is composed of an inverter G2 which receives a clock pulse φ2 as an input, and a NOR circuit G1 which has two inputs the output of this inverter and the clock pulse φ1.
is for preventing clock pulses φ1 and φ2 from overlapping. The above auto clear circuit 3 is FET
The counter circuit 4 consists of four flip-flop circuits FFl-FF4 connected in cascade, FET Tl,~T,4 connected to the ground terminal and the output point of each flip-flop circuit, and the third flip-flop circuit 4. and the outputs of the fourth flip-flop circuits (FF3 and FF4) as two inputs, and the inverted output thereof is applied to the input of the first flip-flop circuit FFl, and the outputs of the flip-flop circuits FFl to FF3. The output of the inverter GO which receives the output of the NOR circuit G3 and the input of FF1 as four inputs is applied to the set terminal S, and the output of the above NOR circuit G3 is applied to the reset terminal R. The output terminal Q of this flip-flop circuit FF5 is
Let us retrieve the output from . For example, as shown in FIG. 3B, the structure of the flip-flop circuit FF1 includes a FET T15 to which a clock pulse φ1 is applied, a FET T16 to which a clock pulse φ2 is applied, and inverters G5 and G6. According to the circuit configured above,
At the same time as the power is turned on, the output VOut of the auto clear circuit becomes G.
The inverter G becomes ND level and receives the signal. Since the output of the counter circuit 4 becomes -VDD level, the last SR flip-flop circuit FF of the counter circuit 4 is set and its output becomes -VDD level. Next, clock pulses φ1 and φ2 are input to the auto clear circuit 3, and the output VOut is
When inverts to -VDD level, inverter G. The output of F becomes GND level, the counter circuit 4 starts operating, and after this counter operation is finished, the SR flip-flop circuit F
The -VDD level is applied to the F5 reset terminal, and the output Q is inverted to the GND level. Therefore, by using the above circuit, it is possible to increase the time during which resetting is applied by the amount of time that is being counted.

Therefore, it is extremely effective when used as a printer calculator. FIG. 4 is an example of an application in which the auto clear circuit of the present invention is used in a dual power supply circuit. As shown in the figure, an auto clear circuit 3 consisting of FETs Tl to TlO is connected to the first power supply VDDl, and FETs Tl7,
The level shift circuit 6 consisting of Tl8 is connected to the second power supply VOD.
2, and has three inputs: the outputs of the level shift circuits T3 and T4 constituting the auto clear circuit 3, the output of the level shift circuit 6 (Tl7, Tl8) provided in the second power supply, and the clock pulse φ2. G7 is provided, and the output of this NAND circuit G7 is passed through the inverter G8 to the FETT T6 which constitutes the latch circuit of the auto clear circuit 3.
applied to the gate of

With this configuration, two power supplies DDl
and V. It is possible to generate a clear τ output when both D2 rise, making it very effective as an auto-clear circuit that can prevent malfunctions in circuits using two power supplies. As explained above, the present invention provides an auto-clear circuit that generates a clear signal when the power supply is turned on and automatically releases the clear signal after a certain period of time has elapsed.

Furthermore, since a clock pulse is used, the auto clear circuit is stable and does not malfunction. The present invention is a circuit that can be modified in various ways in addition to the above embodiment and can be applied to a wide range of fields.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one example of the auto clear circuit of the present invention, and FIG. 2 is a timing chart for explaining its operation.
Fig. 3 shows an example of application of the present invention, and Fig. 3A is a circuit diagram thereof, Fig. 3B is a circuit diagram showing an example of a flip-flop circuit, and Fig. 4 is a circuit diagram showing another example of application of the invention. It is. 1, 6...Level shift circuit, 2...
Latch circuit, 3... Auto clear circuit, 4...
...Counter circuit, 5...Logic combinational circuit, T1-Tl8...FETlGl-G8...
...Gate circuit, FF1 to FF5...Flip-flop circuit.

Claims (1)

[Claims] 1 has a latch circuit that outputs a predetermined level by applying a power supply voltage, sets the latch circuit to the first level by a first clock pulse, and sets the latch circuit to the first level by a second clock pulse that does not overlap with the first clock pulse. An auto clear circuit that resets the latch circuit.