JPS605972B2 - Initial value setting circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an auto clear circuit (initial value setting circuit).
It mainly targets those used in printer electronic desktop calculators (hereinafter referred to as printer calculators).

When turning the power on and off in a printer calculator, a circuit was used to clear the internal state of the circuit when the power was turned on.

This clear circuit was reset by operating the input key. However, it is desirable that the clear circuit be automatically reset without the initiation of a key operation. Due to this automatic reset of the clear circuit itself,
It is possible to have the printer calculator perform tasks such as printing before starting key operations. The present invention is intended to meet such demands, and its purpose is to provide a novel auto-clear circuit that can automatically perform a clearing operation.

An embodiment of the present invention to achieve the above object includes an initial state setting circuit (auto clear circuit) that uses the count time of the counter circuit to set the logic circuit and generate a reset signal when the power is turned on. This is what we provide.

FIG. 1 is a circuit diagram showing an example considered by the inventor. The figure uses an insulated gate field effect transistor (hereinafter referred to as FET), and a power supply Vo to which a clock pulse 0 is applied. An application switching FET, and
FETL,t to which power is applied via this FETT,
a level shift circuit 1 consisting of a level shift circuit 1, an FETL connected to the reference potential (ground) terminal side and driven by the output of the above-mentioned bell shift circuit, and a latch circuit 2 connected between the drain of this FETT T8 and a power supply -Voo. (FET public,
L, T9, T,. ), and the output V skin is taken out from the output point of this latch circuit 2. Note that the FET T2 connected in parallel to the power supply FET T is used to discharge the charge existing in the FET T3 of the level shift circuit when the power switch is turned off. In addition, the FET constituting the latch circuit 2
Clock pulse provided in parallel with T7? The FETT driven by 2 is for resetting this latch circuit.

All the FETs in this circuit are p-channel FETs, especially FETs T4, T5, and T9 are depletion type, and the other FETs (T, L, T3, public, T7, and T8) are enhancement type. FIG. 2 is a timing chart for explaining the operation of the above circuit. The operation will be explained below using the same figure. First, the power switch (not shown) is turned on and the voltage drops from the GND (ground) level to -V.

. When the voltage rises toward the level, FET T8 is off because no voltage is generated in the level shift circuit at this time. Therefore, the latch circuit 2 is set, and the output at this time is V. ut is at the GND level (period t, - et al.). Next, when clock pulse J rises, switching F
ETT is turned on, and the potential Va at the input point of the level shift circuit rises. Therefore, the output V of the level shift circuit
b also rises a little later (period et al.~t3). When the output Vb of this level shift circuit reaches a certain value, the switching F
ETT8 turns on. Clock pulse at this stage? 2
When V rises, the latch circuit 2 is reset and its output V
-Voo level occurs on the skin (period t4). Therefore, the output V when the latch circuit is in the set state. ut(G
If the ND level) is used as a clear signal and the state at the time of reset is used as a release signal, it can be used as an auto-clear circuit and the purpose can be achieved. In addition, if the circuit configuration is as shown above, if ◇
, and 2 rise at the same time, since the level shift circuit 1 controls the FET T8, it takes a certain amount of time to reach the logic threshold voltage that turns the FET T8 on, and no malfunction will occur.

Further, even if the clock pulse ◇2 rises earlier than the clock pulse ◇2, the latch circuit 2 will not be reset by mistake since the FET T8 is not turned on. For this reason, this circuit also has the advantage of a large noise margin. FIG. 3 is a circuit diagram of the auto clear circuit of the present invention.

FIG. 3A shows the auto clear circuit 3 that the inventor previously considered.
and a counter circuit 4 are coupled via an inverter Go. Note that the logic combinational circuit 5, which consists of an inverter G2 which receives the clock pulse ◇2 as its input, and a NOR circuit C whose two inputs are the output of this inverter and the clock pulse ◇2, uses the clock pulse ◇2 as its input. - This is to prevent the stopper 2 from overlapping. The auto clear circuit 3 is composed of FETT, ~TM, and the counter circuit 4 is as follows:
Four flip-flop circuits FE, ~F connected in cascade
E4, FETTs, . ~T, and the third and fourth
The outputs of the flip-flop circuits FF3 and FF4 are used as two inputs, and the inverted output thereof is input to the first flip-flop circuit FF.
an exclusive OR circuit G4 which is applied to the inputs of , a NOR circuit G3 whose four inputs are the outputs of the flip-flop circuits FF to FF3 and the inputs of FF, and an inverter Go which receives the output of the auto clear circuit. An SR flip-flop circuit FF is formed by applying the output of the NOR circuit G3 to the set terminal S and applying the output of the NOR circuit G3 to the reset terminal R.
5, and the output is taken out from the output terminal Q of this flip-flop circuit FF5. For example, the structure of the flip-flop circuit FF, as shown in FIG. Consisting of According to the circuit with the above configuration, the output of the auto clear circuit Vout occurs at the same time as the power is turned on.
becomes GND level, and inverter G receives that signal.
Since the output of o becomes -Voo level, the counter circuit 4
The last SR flip-flop circuit FF5 is set and its output becomes -Vg level.

Next, clock pulses ◇ and ◇ are applied to auto clear circuit 3.
2 is input and the output Vout is inverted to the -Voo level, the output of the inverter Go becomes the GND level, the counter circuit 4 starts operating, and after this counter operation is completed, the SR
-V to the reset terminal of flip-flop circuit FF5. .
A level is applied, and the output Q is inverted and becomes the GND level. Therefore, by using the above circuit, it is possible to increase the time during which the reset is applied by the amount of time that is being counted.

Therefore, it is extremely effective when used as a printer calculator. FIG. 4 is an example of an application in which the auto clear circuit previously conceived by the inventor is used in a dual power supply circuit. As shown in the figure, FETT, ~T,. Connect the auto clear circuit 3 consisting of the following to the first power supply VDo,
The level shift circuit 6 consisting of ETT, 7, T, 8 is connected to the second level shift circuit 6.
The outputs of level shift circuits T3 and T4 constituting the auto clear circuit 3, the outputs of level shift circuits 6T, 7, T, and 8 provided in the second power supply, and the clock pulse ? NAND circuit G7 with 2 as 3 inputs
is provided, and the output of this NAND circuit G7 is connected to an inverter G8.
F that constitutes the latch circuit of auto clear circuit 3 via
Applied to the gate of ETT6. With this configuration, it is possible to generate a clear output when the two power supplies Voo and Voo2 are turned on together, making it extremely useful as an auto clear circuit that can prevent malfunctions in circuits using two power supplies. It will be effective for

As described above, the present invention provides an auto-clear circuit that generates a clear signal when the power is turned on and can automatically release the clear signal after a certain period of time has elapsed.

Furthermore, since a clock pulse is used, the auto clear circuit is stable and does not malfunction. The present invention is a circuit that can be modified in various ways in addition to the embodiments described above and can be applied to a wide range of fields.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing an example of an auto clear circuit that the inventor previously considered, Fig. 2 is a timing chart for explaining its operation, and Fig. 3 is a circuit diagram showing an example of an auto clear circuit that the inventor has previously conceived. FIG. 4A is a circuit diagram showing an embodiment, FIG. 4B is a circuit diagram showing an example of a flip-flop circuit, and FIG. 4 is a circuit diagram showing another example previously considered by the inventor. 1, 6... Level shift circuit, 2... Latch circuit, 3... Auto clear circuit, 4... Counter circuit, 5... Logical combination circuit, T ,~T,
8...FET, ○, ~G8...gate circuit, FF, ~FF5...flip-flop circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1 (a) a counter circuit for counting pulse signals; (b) a circuit for setting the counter circuit to an initial state; (c) means for detecting that the counter has reached a predetermined state; and (d) at least A combinational circuit outputs a first output value from the initial value setting to the predetermined state, and the output value of the combinational circuit is inverted upon receiving the output of the detection means. An initial value setting circuit characterized by: