JPS5943527A - Manufacture of resin sealed type electronic part - Google Patents

Manufacture of resin sealed type electronic part

Info

Publication number
JPS5943527A
JPS5943527A JP15410782A JP15410782A JPS5943527A JP S5943527 A JPS5943527 A JP S5943527A JP 15410782 A JP15410782 A JP 15410782A JP 15410782 A JP15410782 A JP 15410782A JP S5943527 A JPS5943527 A JP S5943527A
Authority
JP
Japan
Prior art keywords
lead frame
resin
lower surfaces
binding material
adhered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15410782A
Other languages
Japanese (ja)
Inventor
Hirokuni Mamiya
間宮　洋邦
Teruyoshi Shibata
柴田　輝義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP15410782A priority Critical patent/JPS5943527A/en
Publication of JPS5943527A publication Critical patent/JPS5943527A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PURPOSE:To enable to continuously produce multikind parts of a small quantity as well as to reduce the percentage of rejects by a method wherein a passivation is performed on a lead frame after an element has been die-inner bonded on a lead frame, and then a molded article is adhered to the upper and lower surfaces of the processing part through the intermediary of a binding material layer. CONSTITUTION:A passivation 4 is performed on a metal lead frame 1 after an element 2 has been die-inner bonded 6 on a metal lead frame 1. Then molded articles 8 and 8', consisting of phenol resin, epoxy resin and the like, are adhered to the upper and lower surfaces of the above-mentioned processed part through the intermediaries of binding material layers 7 and 7', and a resin sealed type electronic part is obtained. In this case, it is necessary that the molded articles are formed in one body by adhering them on the upper and lower surfaces of the processed part. It is desirable that one each of the molded articles is adhered to the upper and lower surfaces of the processed part respectively. The binding material layers may be formed using the application method such as coating, spraying and the like of a bonding agent, and a binding material layers may also be formed through the intermediary of a bonding sheet and the like.

Description

【発明の詳細な説明】 本発明は電ｆ機器、電気機器等に用いられる樹脂封止型
電子部品の製造方法に関するもので、その目的とすると
ころは少量多品種生産、連続生産を可能ならしめ且つ不
良発生率を低下せしめることにある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing resin-sealed electronic components used in electrical equipment, electrical equipment, etc., and its purpose is to enable high-mix low-volume production and continuous production. Moreover, the purpose is to reduce the rate of occurrence of defects.

従来の樹脂封止型電子部品の製造方法は第１図に示すよ
うにＩＪ　・−）’フレーｌ、　１に素子２をダイボン
デインクしてからインナーポンディング３し次にパＩｙ
ンベーンヨン４してからトランスファー成形して素子を
樹脂５て封止［７て樹脂封止型電子部品を得るもので、
大Ｉｉ、少品種生産、パッチ生産に好適であるが少量多
品種生産、連続生産に不向きで且つ不良発生率も６〜７
％と高いものであった本発明は上記欠点を解決するもの
で、リードフレー・ムに素子をダイインナーホンディン
グしてがらパッシベーションし、次に該処理部の」二下
面に接着剤層を介して成形品を夫々接肴一体化するため
少量多品種生産、連続生産を可能ならしめ［］４つ不良
発生率を１・〜２％に低下さぜることがてきたものであ
る。The conventional manufacturing method for resin-sealed electronic components is as shown in Fig. 1, in which an element 2 is die-bonded to an IJ・-)'flare 1, an inner bonding step 3 is performed, and then a piezoelectric film is applied.
After molding, the element is sealed with resin [7] to obtain a resin-sealed electronic component.
Large Ii, suitable for small variety production and patch production, but unsuitable for low volume, high variety production and continuous production, and has a defect rate of 6 to 7
The present invention solves the above-mentioned drawbacks, and involves passivating the device while die-inner bonding it to the lead frame, and then applying an adhesive layer to the lower surface of the treated area. Since the molded products are individually assembled, it has become possible to produce a wide variety of products in small quantities and to produce them continuously.[4] This has enabled the defect rate to be reduced to 1.2%.

以上本発明の一実施例を第２図の図面により説明する。An embodiment of the present invention will be described above with reference to the drawing of FIG.

１は金属製リードフレームで、す・−ドフレーム１に素
頂２をグイインナーホンディンクロしてからパッシベー
ション４し、次に該処理；１５の上下面にフェノール樹
脂、エポキシ樹脂、不飽和ポリエステル樹脂、ジアリル
フタ１／−ト樹脂、ンリコン樹脂、メラミン樹脂、ポリ
アミド゛、ポリイミド、ポリブタジェン、ポリウレタン
、ブチラール樹脂、ヒニル系樹脂、コム等の単独又は混
合物又は変性物からなる接着剤層７．７１を介してフェ
ノール樹脂、エポキシ樹脂、不飽和ポリエステル樹脂、
ジアリルフタレート樹脂、シリコン樹脂、メラミン樹脂
、ポリアミド、ポリイミド、ポリブタジェン、ポリスル
フォン、ポリウレタン等の単独又は混合物又は変性物か
らなる成形品８．８１を夫々接層一体化して樹脂材１に
型室子部品を得るものである。成ノし品は処理部の上下
面に夫々接着一体化させることが必要で好ましくは上下
面に夫々１個の成形品を接−４させることが望ましい。1 is a metal lead frame, after coating the bare top 2 on the lead frame 1, it is passivated 4, and then the upper and lower surfaces of 15 are coated with phenol resin, epoxy resin, unsaturated polyester. Through an adhesive layer 7.71 made of resin, diallyl phthalate resin, polycone resin, melamine resin, polyamide, polyimide, polybutadiene, polyurethane, butyral resin, hinyl resin, comb, etc. alone or in mixtures or modified products. phenolic resin, epoxy resin, unsaturated polyester resin,
Molded products 8 and 81 made of diallyl phthalate resin, silicone resin, melamine resin, polyamide, polyimide, polybutadiene, polysulfone, polyurethane, etc., alone or in combination, or modified products, are laminated and integrated with resin material 1 to form a mold module component. This is what you get. The finished product must be bonded and integrated with the upper and lower surfaces of the processing section, and it is preferable to attach one molded product to each of the upper and lower surfaces.

接着剤層は接着剤塗布、接着剤スプレー等の塗布方法に
よって接２４　ｉ’ｆｌ１層を形成してもよく又ボンデ
ィングシート等を介在させることによって接着剤層とす
ることもてきる。更に接台方法は常温接着、熱接青、光
硬化接着等の方法がとられ特に限定するものではないが
好ましくは生産効率の点で熱接右を用いることが望まし
い。加えて接着層はグイインナーポンディング前にリー
ドフレームに設けておくこともでき任意である。なお素
子、グイインナーホンディング、リードフレーム表向に
接着等の活性化処理を施しておくこともてきるものであ
る。The adhesive layer may be formed as a contact layer by a coating method such as adhesive coating or adhesive spraying, or may be formed by interposing a bonding sheet or the like. Further, the mounting method may include room temperature bonding, heat bonding, photocuring bonding, etc., and is not particularly limited, but it is preferable to use heat bonding from the viewpoint of production efficiency. Additionally, an adhesive layer can optionally be provided on the lead frame prior to inner bonding. It is also possible to perform an activation treatment such as adhesion on the surface of the element, inner bonding, and lead frame.

以上説明したように不発１９Ｊの樹脂封止型電子部品の
製造方法によれは少量多品種生産、連続生産を実現する
ことができ１つリードフレ・−ムの変形か全くないノコ
め不良発生率を従来方法より５％低下さゼるこ吉がてき
たものであるAs explained above, the manufacturing method of the resin-sealed electronic components of 19J can realize low-volume, high-mix production and continuous production, and can reduce the incidence of saw defects, such as lead frame deformation or no lead frame deformation. 5% lower than the conventional method.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の樹脂封止型電子部品の製造方法の簡略工
程図、第２図は本発明による樹脂封止型電子部品の製造
方法の簡略工程図である。 １はリードフレーム、２は素Ｔ−１ｓはインナーホンデ
ィンク、４はパッシベーション、５は樹脂、６はグイイ
ンナーポンディ／り、７．７′は接着剤層、８．８′は
成形品である。 特許出願人 松下電」二株式会社 代理人弁理士　　釣　元　敏　丸 （ほか２名） 第１１ １ 第２図FIG. 1 is a simplified process diagram of a conventional method for manufacturing a resin-sealed electronic component, and FIG. 2 is a simplified process diagram of a method for manufacturing a resin-sealed electronic component according to the present invention. 1 is a lead frame, 2 is a bare T-1s is an inner bond, 4 is a passivation, 5 is a resin, 6 is a guide inner pond, 7.7' is an adhesive layer, and 8.8' is a molded product. be. Patent Applicant Matsushita Den” 2 Co., Ltd. Representative Patent Attorney Toshimaru Tsurimoto (and 2 others) Figure 11 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] リードフレームに素子をグイインナーボンデインクして
からパッシベーションし、次に該処理部の上下面に接着
剤層を介して成形品を夫々接着一体化することを！　’
ＫＭとする樹脂封止型電子部品の製造方法。After bonding the element to the lead frame, passivation is performed, and then the molded products are bonded and integrated with the upper and lower surfaces of the processing area via an adhesive layer! '
A method for manufacturing resin-sealed electronic components referred to as KM.
JP15410782A 1982-09-03 1982-09-03 Manufacture of resin sealed type electronic part Pending JPS5943527A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15410782A JPS5943527A (en) 1982-09-03 1982-09-03 Manufacture of resin sealed type electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15410782A JPS5943527A (en) 1982-09-03 1982-09-03 Manufacture of resin sealed type electronic part

Publications (1)

Publication Number Publication Date
JPS5943527A true JPS5943527A (en) 1984-03-10

Family

ID=15577071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15410782A Pending JPS5943527A (en) 1982-09-03 1982-09-03 Manufacture of resin sealed type electronic part

Country Status (1)

Country Link
JP (1) JPS5943527A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5106784A (en) * 1987-04-16 1992-04-21 Texas Instruments Incorporated Method of making a post molded cavity package with internal dam bar for integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5106784A (en) * 1987-04-16 1992-04-21 Texas Instruments Incorporated Method of making a post molded cavity package with internal dam bar for integrated circuit

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