JPS5942553A - Image forming device - Google Patents

Abstract

PURPOSE:To evade abnormal operation and serious accidents, by stopping a device in safety after specific processing if abnormality occurs in data transfer to and from a peripheral device. CONSTITUTION:If abnormality occurs in data transfer during copying operation, the diagnostic flag of the step is not set, so ON operation is performed to start processing immediately. For example, when transferring paper is fed, the feeding is stopped immediately and after the transferring paper which is already fed is discharged, the device is stopped in a normal state. In this example, only data diagnosis and copy starting and stopping are described, but transfer contents of data are numerous actually. Thus, abnormal operation and serious accidents are evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field The present invention relates to an apparatus for forming an image under the control of a control unit capable of data transfer, such as a microcomputer.

(11) Prior Art There has been remarkable progress in electronic technology in recent years. Ir,
As the integration of electrical and electronic circuits progresses, high-performance microcontrollers have appeared and are used to control various devices. Recently, microcomputers have become commonplace in the control of f*forming devices (copying machines), and when copying (high performance, high speed, and multi-functionality is required), a single microcomputer is required. It is possible to use multiple microcontrollers rather than controlling
L Copy body by function, A1. )F.

When controlling multiple microcontrollers for each function, it is necessary to control computers, etc. , a method using serial transfer is considered.

However, when serial transfer means are used to control each device, there are cases where a section where a serial transfer error occurs due to poor connector contact, noise, etc., or the copier itself or peripheral devices may malfunction. , which could lead to a major accident.

For example, in two microcomputers (5) and (1, s), the serial transfer means usually sends a signal (ItJ=;Q, 0) to notify that data is to be transferred.
.

A signal indicating that transfer data can be accepted (1-tE
When it is determined that the transmission/reception system is ready in Q, E), serial transfer is activated and REQ is always generated from the microcomputer (A) at a predetermined cycle.
I wait for some reason, such as microcontroller (B) error! 'IJ ('F,), chair, etc., due to interface failure, I also EQ, 1', microcontroller (4
), the microcontroller (a) will always be able to
The program program is held until '+' when the Q and E signals are detected, and it becomes impossible to proceed to the program for the next processing.

Also, when checking the signal by operating a timer, for example, when the microcomputer (5) issues the REQ signal, a timer means built in the microcomputer is simultaneously operated to generate 1ζEq within a predetermined time, that is, within the timer time-up.
The serial transfer means is diagnosed by checking the z signal, and after the REQ and E signals are generated, the microcontroller (!l) operates a timer using the same means as the above-mentioned mark f controller, and transfers data within a predetermined time. If serial data is not sent to the computer, it is determined that there is an error, and if a data transfer error occurs during the copying operation, each microcomputer may be latched programmatically, especially the microcontroller in the sequence control system. In this case, if an abnormality occurs at the time of paper feeding or the lighting timing of the exposure lamp, the state may become latched and cause great damage to the entire copying apparatus.

(To) Purpose In order to improve the drawbacks of the above-mentioned conventional example, the present invention has a data monitoring means, and when an abnormality occurs in data transfer between peripheral devices, performs predetermined image forming processing to display an image. An object of the present invention is to provide an image forming apparatus having means for safely stopping the forming apparatus.

Embodiment FIG. 1 is a block diagram of microcomputer control used in the control of the present invention. First, in Figure 1, two microcontrollers (
The control means of the present invention will be explained using A) and (B).

Dialogue between the microcomputer and the operator - In other words, in order to inform the operator that the desired number of copies has been input using a key or other means, the number of copies to be set and the number of copies to be made, etc. can be displayed, and the copy command (start) can be displayed. , stop, 11 other cassette size selections, and display functions in real time. On the other hand, the My 21 (13) performs various controls necessary for the copying process, such as charging, I/3 light, transfer, etc.
The copying process consisting of static elimination and fixing is executed next to perform the copying process, and serves as a sequence controller, such as main motors (M, I), paper feed timing (PF'),
Exposure lamp ([,),)'C;C;Dynamic drive-\Vi))
Gives a signal of ¥f. In Book 1+, a serial transfer means is used as a means for exchanging information, that is, exchanging data between microcomputer (8) and microcomputer 7 ()1) c':.

Figure 1 shows the deceased C17 icon (^)'s IJ 'T 7 (SO) or r) microcomputer (11)'s 7 real person (SI), Miko 7 ([3) ( 7,,) ・7I
J7/l/Output (SO) to serial manual input (SI) of microcomputer (5), Sarani shift clock (SCK)
) is connected to the microcomputer (A) and the color microcomputer (13). In addition, from the output capo PE of the microcomputer (5), a signal (
IQ, 0) is output and connected to the human power port PAo of the microcomputer (13), and once the acceptance system of the microcomputer (J3) is established, the REQ' enable signal (REQ , E) are output and transmitted to the input port PAo of the microcomputer (4).

For example, when the microcomputer (5) determines that the operator has pressed the copy button, the sequence control microcomputer (13) determines that the operator has pressed the copy button.
) To transfer the copy start command data to the microcomputer (A), first set the copy command data in the shift register in order to output it from the SO in the microcomputer (A), and then
The signal REQout (R
Send EQ, O) to the microcomputer CB). The microcomputer (B) sends the fifJ AQRE Q out signal (REQ
, O), and sets the status of the microcomputer (B), for example, whether it is currently copy cycle or standby, to the shift register output from the data transfer SO, and informs the microcomputer (B) that the transfer status is ready. Let me know. At the door, the microcomputer (A) is the REQ controller 1.
゜When No. 1 (R1!] Q, E) is received, the 11 bytes of data 5η start from 1, 11, and at the point when the transmission ends at r, the microcontroller (A) and (+3) An internal interrupt occurs,
Among them, i'+ili'i! -i'-ta (υ
゛11 November 1st.

FIG. 2 is a control block diagram of the iI Shinono Trezisk in 1962. The pjt7 works of the software registers are controlled by the software, and the internal interrupts are interrupt 1 and 1.
'/F, l, ri occurs: ノ1. Ru. j'j'll included 1
7'/F'' is an interrupt signal (software) and a signal 1c generated when the shift register stops operating.
L is reset. Furthermore, the 7-foot register is 'icon's internal bassoon f), °Aki 1no, Leh Yu (Ace).
) and is touched and illuminated from 8CC/Notre, 1' to Instagram
- Tai C Hi, Soto Ij Ding 1 Class, 7 Shi 7 Tregi 2
It is also possible to transfer data from the star to the ACC.

FIG. 3 is a detailed diagram when the transfer means connected to the serial data I register is connected to the microcomputer (B).

The shift register used in the present invention has a 16-bit shift register, and has 4 bits each from 5TO to 8T3. Furthermore, the shift register operates in synchronization with the shift clock (SCIO) and generates 7 shift clocks from the marf controller (a).

FIG. 4 is a timing diagram of serial data transfer.

@ As explained < It l'; Q out (REQ
-0) and I7 EQ enable signal (1 is also EQ.

E) causes microcontrollers (A) and (B) to each
' - data is set in the shift register, interrupt enable is set, and shift register F/F is set to generate a shift clock (SCK) from the microcontroller, and the mutually set data is sent to each microcontroller along with the shift clock. Transfer data. Then, when the shift clock ends, the mutual microcontroller (5).

An internal interrupt occurs at (B), and data is determined within each internal interrupt process. In FIG. 5, the data contents for transferring information from the microcomputer to the microcomputer ([1)] are shown.

FIG. 6 shows the data contents for transferring information from the microcomputer 03) to the microcomputer (5).

We have described above the means of control using two microcomputers, but when devices become system-denominated, not only a copying machine but also an automatic document feeder (AI) and a sorter device become necessary.

FIG. 7 shows AI)F based on the transfer means described above.

FIG. 2 is a control block diagram including sorter control.

The microcontroller (A), (11) performs the above-mentioned Shidari ['', and the microcomputer (C) performs the A I)! The microcomputer 0)) controls the sorter.In other words, serial shift registers serving as means for exchanging information are connected in series to enable efficient transfer.

Figure 8 Guyo %' @ AI as if you got 1-11 in Figure 7)
F.

If a sorter or the like is added, this is a control block diagram in which serial shift registers are connected in parallel. Compared to the case where serial shift registers are transferred in series as shown in FIG. 7, the transfer speed (time required for making decisions) of each of the captivators connected in parallel as shown in FIG. 8 is faster.

Figure 9 shows two microcomputers (5) according to the present invention.

FIG. 6 is a flowchart showing the data transfer operation according to FIG. First, the microcomputer (5) will be explained.

After the power is turned on, step 1, step 1, I10, etc. are reset (cleared), and in step 2, the operating unit (not shown) performs manual key determination and display processing, and in step 3, the register Ji'/F is checked. This register”/
Ii'r,,t: Determine whether the shift register is operating.

Next, in step 4, it is determined whether the copy button was pressed in step 2. If the copy button is pressed ft, 1 is added to step 5. As shown in Figure 55, the copy start command sets 13 in Sr1 as data to be sent by the sequence microcomputer (B). To execute this, first add t3 to the accumulator (AcC).
In step 8, the contents of the accumulator (ACC) are shifted into a register. If the stop key is pressed, step 6 sets the value 14 to the AR V unit at step 7. 2 block 8 and shift register 111. Set the interrupt enable to enable the transfer and set the interrupt register F/F. Then, in step 10, the data is transferred to the microcomputer (B). [To notify that 7 days have passed, output port II'A is set and REQ is sent.
The out signal (REQ, 0) is sent to the microcomputer (13)
and at the same time set the diagnostic timer (A). In step 11, 1 from the microcomputer (+3), IE
When the Q enable signal is inputted, the process moves to step 13 and the timer (A) is reset, and in step 14, the It E Q out signal (J, tEQ,
0) to start data transfer starting at step 12.

In the data diagnosis of the present invention, the microcomputer (1
From '3)) If ζIDQ,E is not replied within a predetermined time, it is determined in step 12.

In other words, in step 11, it is determined in step 12 whether or not the one-hour timer set in step 10 has timed out, and if the time has expired, the process returns to step 1, clears the data memory, etc., and restarts from the initial stage. are doing. Also, in step 11, R within a predetermined time.
If an EQ or E response is detected, the timer (t) is reset as described above.

Next, the microcomputer (B) will be explained. )) OWEIt
After turning on, the data memory (RAM) Ilo is cleared (reset) in step 22] 7. In step 23, the copy preparation cycle is checked, and in step 24, the register F/F is checked to confirm the shift register operation. Next, in step 25, data is transferred from the microcontroller (4) using RTCQ.
Check if out exists, if so, step 2
6, preparations are made to set information to inform the microcomputer (4) of the operating state of the microcomputer (B) in the shift register (steps 26 to 28).

In this example, the microcomputer (B) has data 8 in the SUMBY state.
An example of setting TO to 0 is shown.

Data contents from the microcomputer (13) to the microcomputer (...
1) °α (similar to the one shown in Figure 5), after setting the data to the shift register, the register F/F is set.

The interrupt enable is set, and a signal (REQ, E) for data transfer (UK) is output in step 25. 17. At the same time, the data transfer diagnosis timer (B) in the microcomputer (II) is set. Next, in step 29, the timer (
13) Determine whether or not the time has expired. The set time of the timer (1) Q↓ is slightly faster than the data transfer rate sent from the microcomputer (t,)? Make sure to set the appropriate time. At step 29, the diagnostic flag is checked at step 10.

Occurs when data transfer is completed in (n)
- Since the program is programmed to be hit in the internal interrupt processing, it can be determined whether the data transfer was performed correctly by checking the diagnostic flag. If N 0 in step 30, it is considered abnormal and initial step 2
Start from the beginning. On the other hand, if the diagnostic flag is set, the process moves to step 31, where the diagnostic flag is reset and the timer (11) is reset. Then, in step 32, F/S TA RT is checked to confirm that the copy start command has been transferred by the interrupt routine.

Here, an explanation will be given of an interrupt routine that occurs when the microcomputer (5) starts data transmission in step 15 and ends the data transfer in step 17. The interrupt generation timings by the microcomputers (A) and (13) are almost simultaneous. Let's start with the microcomputer (A). When an interrupt occurs, the data sent from the microcomputer CB> is set in the shift register, so the contents of the shift register (in this case, S i" (only talks about l) are set in the aggregator (
Step 16) Then, in steps 17 and 19, the contents of the aggregator are judged to determine what data has been sent.

If A CC = 0 in step 17, the microcomputer (B
) is in standby state, operation 1;
11. ．． 1! Control the flag (Step 18).

Also, in step 19, A (: 8 is determined with c), then Ma I: 17 (13) is copied 11 tj) in the work i'),
The flag that enables the prohibition of KEY input, etc. is set to "7 try-+" (Step 2 (1)
. Then, register F'/t' and t't in the scheduler 21.
Q Enable 4.

Next, in the microcomputer (No. 1)'s ν; 1j; 7. Step 46-c' In case of icon (8) and rotation (1
Accumulate the contents of the shift register immediately (step 4 F+) and go to 4 at step 47 (C=
The case of 13 is determined to be a °-command for L, and in step 48, the flag F'/S'I'Alt'r is set to 1. ! tsu)
do. Also, with Sua ° Tsubu 49 and l:c=14:':>
iL i,f: Set Fract'/S "I" OP with copy stop command and fistless step 5o.

) and "C step 51 register l;'/F.

Interrupt enable is reset and REQ is executed in step 52.
Reset enable output.

Therefore, in step 32 of the microcomputer (B), [Z5TAIζ
Once ゛r is set, the copying operation starts (1j1).

The copying operation is performed in steps: (Steps 35 to 41 in step 4 are related to the data transfer means for determining whether or not F'/S i,' OP has been sent in step 42, and when a stop command is received, copying is performed at step 44. Moving on to the post-rotation process, steps 39 and 4U are performed as described above.
When an abnormality occurs in the data transfer during copying operation, the diagnosis flag of step 40 is not set, so the answer is NO.Step 4
After step 4, the process moves on to rotation processing. For example, in case 1) 4 when the transfer paper is being fed, there is a means 1 for data diagnosis and copy start in the embodiment.

Although we have described an example of only stopping, in reality, there are a large number of data transfer contents as shown in Figure 6 of PR5g.

The above explains the case where there are two microcontrollers, but in Section 7,
As shown in Figure 8, three or more microcontrollers are used and the serial transfer means are connected in series.

The case of parallel connection will be explained.

The data transfer method for each microcontroller is basically the same as the method using the two microcontrollers described above, but in order to reliably send each microcontroller's information to the desired microcontroller, each microcontroller must be assigned an m number, and the When determining whether the data has been sent or not, and when transferring data, it is necessary to add the microcomputer number of the destination. :H41 (Figure 1 is an actual diagram when one transfer number is determined for each microcomputer in the previous 812 series.

In other words, the transfer destination j4-y of each microcomputer is assigned to Si2 of the shift register. In this example, Si2 is 0001
In the case of m, microcontroller (5), l) (> 10+2
), the microcontroller (B).

In the case of 0011(3), the microcomputer ((shi), (1100
In the case of +41, I added the microcomputer (D). That is, when each microcomputer sets transfer data to the microcomputer to which it wants to transfer, it sets the transfer destination microcomputer number in Si2. Then, data transfer is started, and the destination microcontroller checks ST3 after an interrupt occurs to determine whether the data has been sent to itself. Si3
If the 0 number is data sent to you, STO~S
Determine the data content of T2 if tF<Midori data.

The flowchart of FIG. 11 specifically shows this. FIG. 11 shows an interrupt routine caused by the occurrence of an interrupt after data transfer from each microcomputer. Each microcomputer e, 1, step 60, first shift register 81'
3 to the accumulator (ACC) and
Check the contents of Acyuno and Rater with l. If the contents of the accumulator are 1, the microcomputer is trapped.

In the case of 2, it is the microcomputer (H), in the case of 3, it is the microcomputer (C), and in the case of 4, it is the microcomputer (D), so each microcomputer has its own data.Step 62
At step 63, the contents of shift 1/register S71'') to ST2 are stored in the data memory (IeAM) via the aggregator, and at step 63, the contents of the data are determined in I?, AM, and ST2. and performs each process.If it is not the content of the data sent to it in step 61, 'f' is returned.
If 1-31 is disconnected, 1-31 is added to step 64. −′
, the module 64 immediately prepares to transfer the data sent as is to another microcomputer. On the other hand, the data is transferred to the destination microcomputer in the storage register (steps 5, 7, and 7 in Figure 9).
8, 9, 1.0, l 1, 12, 13.

+ 4, using the same method as 1.5, but be sure to use %e here
Destination number 49 must be set in ST3. Therefore, by the above means, even when the serial transfer means of three or more microcomputers shown in FIGS. 7 and 8 are connected in series and in parallel, information can be easily exchanged between the microcomputers. However, if the serial transfer means are connected in parallel as shown in Figure 8, the microcontroller (5) will play the role of the master microcontroller, and only the microcontroller (5) will be able to transfer the data to each microcontroller as shown in Figure 11. If processing is necessary to determine whether it is connected to series 1 or V, each microcontroller is connected.

(B), (c), and (L)) each requires processing to determine the transfer destination data. Therefore, it is advantageous to connect the serial transfer means in parallel as shown in FIG. However, this device is effective regardless of whether the connection is serial or parallel.

(V) Effects As detailed above, according to the present invention, when an abnormality occurs in data transfer between microcomputers, the device is safely stopped after predetermined processing is performed. This made it possible to avoid major accidents.

Also, whether the microcomputer is connected in parallel or serially, it is easy to avoid abnormal operation of the device and major accidents (11th iQ).

[Brief explanation of drawings]

1131 Figure t, Maikiff computer-controlled pu1 cock diagram. The 21st number + is a 71st register control [111 block diagram. ;a; Figure 3 is a detailed diagram of the transfer method using the serial shift register (A), (r3) and the connection. Figure 1 is a detailed diagram of the serial data Quimming diagram of modulus j4. No. !'i Figure it: J: , -7-1 Krokon' Pikota Buddha) to Ma'ik'1 Kombi' upper-ta (13) Data for tj;< jX Diagram showing the contents. ηS6 Diagram Q": From the microcomputer (B) --
-fri11computer) -Information~: - Indicates the content of the data to send I4 by φrmi. Figure 7, A l) I”, :/ -ta'1'7
'Mo@meda1ltll fjl flock diagram. 81' = 4 is AI) J'', ;/-1' etc. 4 TV
Meda system! i A block diagram showing the case where the serial shift register is connected to the serial register. The figure $9 shows two microcomputers (A) according to the present invention. FIG. 3 is a flowchart showing a data transfer operation by CB. FIG. 10 is an implementation diagram when a transfer number is determined for each microcomputer. FIG. 11 is a flowchart of the interrupt routine for each microcomputer when an interrupt occurs after data transfer. Patent applicant: Canon Co., Ltd.

Claims (1)

[Claims] A control device capable of gutter transfer + 1J provides control of image formation, etc.
1. An image forming apparatus that performs +111 image forming apparatus, wherein when a data transfer abnormality occurs, the operation is stopped after performing a predetermined process such as image formation.