JPS602818B2 - digital data communication equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital data communication device, and more particularly, to a fault tolerance system.
It pertains to a digital data communication device with functions.

Although there are many prior arts that form the background of the present invention, the differences between these prior arts and the present invention will be described below to facilitate understanding of the present invention.

K. Thm technique r & e. Jensen, “A.S.
systematic approach to the
Design of DigineIBuSing S
UMture”, Pr ratio.FJCC, pp, 7
19 (1972) only considers a general data bus configuration, and specifically considers a configuration according to the invention, in which two of the four sub-buses are used for control information and the other two are It is not intended that one be used for control timing.

This paper also makes no mention of disability tolerance. I
BM TDB, Vol, 12・No. 1. Ju fertilizer 19
69 pp. H.163 deals with communication lines rather than general digital bus configurations.

The line adapter described in this article does not test for signals on thin lines, as does the present invention, and is not programmable. mM TDB, Vol. 9.No
．． 5,0ct. 1966, pp. 4 I am not disclosing time-sensitive communications such as the present invention.

IBMTDB, Vol. 8, No. Enter Aug. 196
5, pp. The third scale is not intended to use a separate sub-bus to provide control information.

No. 51,905 discloses an error checking method and apparatus, which does not utilize multiple sub-buses to check bus signal timing or programmable interfaces as the present invention does.

Although US Pat. No. 3,434,115 discloses a timed sequence controller, it does not disclose any of the interface units or bus configurations of the present invention.

No. 3,517,171 shows a data processing system that uses bus monitors, but these monitors are simply error detectors for the error detection codes used in the system.

Character validation as used in the present invention
n) There is no provision in this system for performing protocol timing checks. US Patent No. 3
Ball 4 Paper No. 7 discloses a data collection device that connects multiple remote locations and a central location with a common line, but does not contemplate a sub-bus for both control information and control signals. Further, there is no disclosure of any unique monitoring system or programmable interface unit as used in the present invention. US Patent No. 3,536,902'
However, it merely discloses a sequence step test circuit for a telephone exchange, and is unrelated to the configuration of the data bus.

No. 3,651, only contemplates a system for testing the operation of digital logic in response to commands from a processing unit. In contrast, the present invention is directed to a constantly operating test system that is capable of detecting signals sent over a sub-bus at any time. Also, this US patent does not mention the use of a programmable interface unit. While U.S. Pat. No. 3,648,256 discloses a serial bus configuration with some failure detection and retry functionality, the present invention relates to a general parallel bus configuration with both control and data signals. . It should be noted that the above-mentioned prior art merely represents what appears to the applicant to be the best, and does not imply that there is no prior art that is more suitable than these prior art. .

It is therefore an object of the present invention to provide a fault tolerant data bus architecture.

Another object of the present invention is to provide data communications such as a common communication protocol that can be modified for many uses.
The purpose is to provide a bus configuration.

Another object of the present invention is to provide a programmable system capable of detecting faulty communications and isolating such communications by using a common protocol.
The purpose is to provide an interface unit. Briefly, the data bus configuration according to the present invention includes:
The control information exchanged between modules is grouped into two sets of sub-buses for transmitting character information from the initiator module and the follower module; Controlled by other associated strobe sub-buses.

This bus configuration is symmetrical with each type of line being driven by each of the two modules involved in the communication. Using appropriate error detection and correction code, possible bus failures can be overcome without changing the basic bus communication protocol of the present invention. In addition to the bus monitor of the present invention provided in conjunction with this bus configuration, it operates to check the validity of characters being transmitted as well as to check the timing of control signals on the strobe sub bus. do.
Furthermore, a programmable interface unit is provided in connection with this bus. Preferably, this unit includes dedicated memory for controlling the operation of the sub-buses, as described below. Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a minimal bus configuration according to the invention.

Two modules exchanging data are shown in FIG.
tor) 1 and follower module (Follower)
It is called 3. In the following description, the initiating module refers to a module that starts a communication sequence, and the follow-up module refers to a module that responds to that communication. To couple these two modules, at least five sub-buses 5, 7, 9, 11 and 1
3 is provided. The sub labeled “1 strobe”
The bus 5 consists of one line driven by the initiation module 1 and signals the start and end of a single exchange sequence. The sub-bus 7 labeled "F strobe" consists of one line driven by the follower module 3;
Signals that a command from initiating module 1 has been received. The sub-bus 9 labeled "1 character" consists of one or more lines driven by the initiating module 1;
The initiating module 1 transmits the information to be given to the following module 3. The sub-bus 11 labeled "F-Character" consists of one or more lines driven by the follow-up module 3 and transmits information provided by the follow-up module 3 in response to the "1-Character" signal. Line 13 labeled ``Reset'' consists of a single line driven by bus monitor 15, as described below, to reset the bus interface to a known state when an error is detected. However, in order to simplify the description below, we will mainly focus on these sub-groups.
The description will be based on the signals appearing on the bus, and the above-mentioned notation will be used when referring to these signals. For example, a "1 strobe" signal refers to a signal sent to the 1 strobe sub bus 5, and so on. FIG. 2 shows a standard sequence for communication using the bus configuration shown in FIG. When the initiating module 1 is allowed to use the bus, it places an rl character as the desired command on the sub-bus 9 and, after a short deskew delay, sends a "1 strobe"
Raise the signal. These two activities start the complete sequence. When the “1 Strope” signal rises,
The tracking module 3 receives the ``1 character'' signal as a command, initiates the indicated operation, and places an ``F character'' signal on the sub-bus 11 in response. After another deskew delay, the tracking module 3 is "F-strop"
Raise the signal. The rising of this signal instructs the initiating module 1 to receive the "F letter" signal from the follower module 3 and to signal its reception by falling "one strobe one stroke". As shown in Figure 2, the ``1 character and 1 post'' signal also falls at the same time as the ``1 strobe'' signal. The falling of the "1 strobe" signal signals to the tracking module 3 that the "F character" signal has been received. When the tracking module 3 confirms this condition, it simultaneously lowers the "F Strope" and "F Character" signals, thereby terminating this sequence. When the "F Strope" signal falls, this bus is completely free, so that the initiation module 1 can restart this sequence with another command. The "1 Strobe" and "F Strobe" signals are for synchronizing all communications on the bus and are completely independent of the exact information being communicated over the bus.

The "Character 1" and "Character F" signals carry all information related to the request of the initiating module 1 and the response of the follower module 3, but not included in the actual timing of the information transfer. This is in sharp contrast to many bus configurations where the same bus lines are involved in both timing and information transfer. The bus architecture of FIG. 1 can be further refined without affecting the timing and control separation.

For example, although FIG. 1 only shows one initiator module and one follower module 3,
In order to share a bus by multiple initiator modules and multiple follower modules, well-known techniques can be applied in the usual manner. That is, any initiating module may assert its ``bus request'' line and initiate its communication when the ``bus grant'' line to that module is asserted. When the bus is granted, part of the initiating module's communication information in the "single character" signal can be the follower module's identification code, thus indicating which follower module should respond. Most buses, where the same wire carries both timing and information, require fault tolerance to detect and correct basic bus faults such as a broken connector or failure of the bus drive or receiver circuits. Even if it were possible, it would be a shame to create such abilities.

Even relatively sophisticated techniques such as error correction codes do not yield good results when the information being transferred is extracted based on variations in the time sequence on the various bus lines. The bus configuration shown in Figure 1 above is as follows:
This is the exact opposite. This means that all of the bus timing is provided by the ``1 strobe'' and ``F strobe'' signals, and since the ``1 character'' and ``F character'' signals are observed at rest, any standard error detection or Correction codes can be applied to these signals without any need to change the basic signal protocol shown in FIG. Similarly, "1 strobe" and "
Since the "F strobe" signals do not contain any communication-related information, these signals can be protected by any method more suitable for timing signals (eg, line duplication). The bus configuration of FIG. 1 merely represents a minimal bus configuration in accordance with the present invention.

It is also possible to add new sub-buses and control these sub-buses with the basic signal sequence described above. For example, a bidirectional data sub-bus may be added to the bus configuration of FIG. 1 to couple a central processing unit (CPU) to a memory module or 1/0 controller. FIG. 3 shows such an arrangement. In FIG. 3, sub-buses 5, 7, 9, 11 and 13 provide timing and command signal transfer buses, while data sub-bus 17 is a bidirectional data transfer bus between CPU 9 and memory 21. give. The operation of this array is under the control of a bus monitor and base controller 23. FIG. 4 illustrates the signal sequence for the arrangement of FIG. In this example, the starting module, CPUI9, is “Issue-Calculation-Write”
Memory 21 which requests the sequence and is a follower module.
transfers the data to CPUI9 in response to this request, and
The UI 9 modifies this data and returns it to the memory 21, and the memory 21 writes the modified data to its original location. The first piece of information is a ``single character'' signal labeled ``ICI,'' which indicates that an address is placed on data sub-bus 17. given to 9. After that, “FCI
The "F letter" signal, labeled "F," rises to indicate that the address has been received and that the motion has begun.
Subsequently, after the "F strobe" signal is raised, "this signal and the "FCL signal" end at the same time. Next, "IC2"
After the signal goes up indicating a request to receive data, the "1 Strope" signal goes up. After the "FC2" signal goes up indicating that data is placed on data sub-bus 17, the "F Strope" signal goes up. data·
The data on sub-bus 17 has the same duration as the "FC2" signal. After these three signals end at the same time,
A computation period is taken, following which modified data to be written to memory 21 is provided on data sub-bus 17.
At this point, the "IC3" signal is asserted to indicate that modified data is being placed on the data sub bus 17, followed by the "1 strobe" signal rising. After that, “FC3
'' signal is generated to indicate that modified data has been received and writing has begun, followed by an ``F STROBE'' signal. When these signals terminate, the sequence is complete. From the above, one character sub bus 9
, that the timing and synchronization for the F character sub-bus 11 and the data sub-bus 17 is derived entirely from the 1-strobe sub-bus 5 and the F-strobe sub-bus 7, and that the former bus transfers are based on command information. It will be appreciated that the bus monitor 23 according to the invention uses exactly the same, but different, signal protocols. module can be determined.

FIG. 5 shows a schematic block diagram of a possible monitor configuration. The monitor 23 consists of two parts, one of which has one strobe.
The signal protocols on sub bus 5 and F strobe sub bus 7 are checked, while the other checks the validity of the commands on single character sub bus 9 and F character sub bus 11. The protocol timing checker 31 is a one-strobe sub. It receives inputs from bus 5 and F strobe sub-bus 7 and provides an output signal on line 32 labeled "Strobe", as well as on lines 33 and 35 connected to OR circuits 37 and 39. supply the signal. The validity of commands on the single character sub-bus 9 and the F character sub-bus 11 is determined by the character validator 41.

This device has 1 character sub-bus 9 and F character sub-bus 1.
1 and receives input from the protocol timing checker 31 via the strobe line 32;
It then provides output signals on lines 43, 45 and 47. While line 43 is connected to the second input of OR circuit 37,
Lines 45 and 47 are connected to two inputs of OR circuit 51.
The output of OR circuit 51 is connected to the second input of OR circuit 39, and the outputs of OR circuits 37 and 39 are connected to the input of OR circuit 53. OR circuit 53 supplies an output to reset line 13. Also, the outputs of the OR circuits 37 and 39 are “FL
and to the lines labeled "FF", respectively. These lines indicate faults in the initiator module and follower module, respectively. Protocol timing inspection device 3
1 output line 33 indicates an invalid timing of the start module, while output line 43 of character validator 41 indicates an invalid "1 character" signal. Either of these conditions will cause an output on line FI to indicate a fault in the initiating module and will also cause a signal on reset line 13. Line 45 indicates an invalid "F letter" signal and line 47 indicates an invalid combination. The state of any of these is OR
Producing an output from OR circuit 39 via circuit 51 indicates a failure of the tracking module and also indicates when an output is produced from protocol timing checker 31 on line 35. In this way, the line FF
An output is also applied to the reset line 13 via the OR circuit 53. FIG. 6 is a state diagram of the protocol timing checker 31, representing the various possible states and their transitions. Each circle labeled A through E represents a possible state of the device. In general, states A through D represent four possible combinations of values that the "1 strobe" and "F strobe" signals can take. In other words, state A indicates that the "1 strobe" and "F strobe" signals are both inactive, and state B indicates that the "1 strobe" signal is active and the "F strobe" signal is inactive. In state C, the "1 strobe" and "F strobe" signals are both active, and in state D, the "1 strobe" signal is inactive and the "F strobe" signal is active.
Indicates that the signal is active. State E represents a failure of the follower module, and state F' represents a failure of the initiator module. The binary numbers in parentheses and the binary numbers adjacent to the arrows represent the states of "1 strobe" and "F strobe 1 stroke" that caused the state transition. State A is a normal stationary state, and bus communication is not performed. This corresponds to the case where the

The transition to state B occurs when the "1 strobe" signal rises. State C is entered if the "F Strobe" signal subsequently rises. "1 Strope"
The falling signal causes a transition to state D, followed by a return to state A when the "F STOP" signal falls. Therefore, the normal state sequence is A1B1C1D-A. As is apparent from FIG. 6, other sequences of the "1 strobe" and "F strobe" signals are incorrect and will result in a transition to state E or state F depending on the cause of the fault sequence.

Also, in states 8-D, an error indication is generated when the ``1 strobe'' or ``F strobe'' signal does not change within a certain time period due to a fault. This feature can be used to detect when either the initiation or follower module does not respond within the expected time. protocol·
Details of the timing inspection device 31 will be described later. The character confirmation device 41 is explained here. Its main purpose is to check that the command characters transferred via the single character sub-bus 9 and the F character sub-bus 11 are correct, and that the combination thereof is also correct. The purpose is to inspect.

This device performs this test when it receives an input signal from the protocol timing tester 31 via the strobe line 32, that is, when the 1-character sub-bus 9 and the F-character sub-bus 11 provide stable information. This is the case when the time to hold is specified. This strobe is in state B in Figure 6.
is derived based on the transition from to state C, and this coincides with the rising edge of the "F strobe" signal in FIG. In most applications, the verification operations performed by the character verification device 41 include: ■ that the '11 "1 character" signal is a valid command, ■ that the "F character" signal is a valid command, and that the "F character" signal is a valid command; This could be a simple table lookup function that confirms that the combination of the ``Character 1'' and ``Character F'' signals is valid.

It is relatively easy to implement such a test, and PLA (Pr
This includes using a memory (LogArray) or private memory (ROM). Adopting the latter approach, you only need to design one basic configuration of a standard bus monitor, and it only requires PLA or ROM.
The effect is great because it can be applied to various systems by simply changing the programming. If a ROM is utilized for the character verification device 41, the number of its input address bits must be equal to at least one character sub-bus 9 and the number of lines contained in the F-character sub-bus 11, and the POM must be small. Both have 3 outputs (1
3 bits per word). Each word of this ROM corresponds to a different combination of "1 character" and "F character" signals. As already mentioned, the character verification device 41 has three output signals, by means of which various disturbances can be detected, namely an invalid "1 character" signal, an invalid "F character" signal or a "1 character" and a "1 character" signal. F letter”
Indicates an invalid combination of signals.

The last two cases represent situations where the tracking module is faulty. The outputs of character verification device 41 and protocol timing verification device 31 are combined in a plurality of OR circuits as described above, thus indicating failure of the initiator module and/or follower module. If either of these is commanded, reset line 13 will be raised to cancel communication and force both modules into an error recovery sequence. It should be noted here that for new applications, only the programming of the PLA or ROM in the character verification device 41 needs to be changed, and the rest of the device does not need to be changed at all. Various modifications can be made to the basic bus monitor of FIG. 5 to perform additional tests on data communications. For example, if "1 character" and "
ROM or PL if standard error detection and/or correction codes are used to protect the F character signal.
Extend A to give 5 outputs, and add that additional 2
The bits can indicate fault codes for the "1 character" and "F character" sub-buses. This is an invalid '
This is different from the situation involving a "1 character" or "F character" signal. This is because the use of error correction codes in conjunction with the table lookups for these sub-buses would lead to the true content of the "1 character" or "F character" signal. The fault code line will be raised when the code is not an error free word, and these additional two wire outputs will be used to indicate a potential module interface or bus fault. As already indicated, the bus arrangement according to the invention is suitable for implementation using standard programmable interface units that can be adapted to any device to be connected to the bus.
This same design can be used not only for devices that can themselves generate complex communication sequences, such as CPUs, but also as virtually a complete controller for simple peripheral devices. can. A general design of a programmable interface unit according to the invention is shown in FIG. This design is based on using ROM for simplicity. This interface unit accepts ``1 character'' and ``F character'' signals, ``F strobe'' and ``1 strobe'' signals, as well as other sets of signals intervening between this unit and its associated peripheral device. Requires. These signals include ``1 mode'' or ``F mode'' to select the type of operation of this unit, a set of ``character select'' signals to indicate the next character to output, and a set of ``character select'' signals to indicate the next character to output. "1 Sequence Start" signal to start the sequence, "F Sequence Start" signal to start the follower module's sequence, post-technique character to be received from the other module last involved in communication with this module. Contains an ``input character'' signal that indicates the ``input character'' signal. There is also an "input character available" signal that indicates that the "input character" signal is valid. In the arrangement of Figure 7, when a device becomes the initiating module, a ``1 mode'' signal is provided to the programmable interface unit, and a ``character select'' signal is set to a code that selects the desired ``1 character'' signal. , and the "Start 1 Sequence" signal is raised.

Then, under the control of the CHARACTER SELECT signal, the desired single character produced at the output of ROMI is gated into the RI register, from which one further character sub-bus 9 is decoded. , in this situation the line SI rises and
This is because the circuit 61 is energized. The line SI rises when "1 sequence start" is added to the input of the AND circuit 66.
This is because the signal is up and the output of flip-flop 64 is down. After a short delay provided by delay circuit 63 to ensure that the ``1 character'' signal is stable, the ``1 strobe 1 signal'' rises. When placing A
An input is supplied to the ROM 2 via the ND circuit 62 . R
OM2 converts this ``F letter'' into a status indication desired by the device in question. This indication is loaded into the R2 register, from where it is accessible to the associated device via the ``Input Character'' line. . At this point, one of the ``mode'' signals is up and the ``F strobe one stroke'' signal is also up, so a set signal is given to the flip-flop 64. Thus, the r input character available signal goes up and the Indicates the arrival of the "F character" signal. At the same time, due to the rise of the "input character available J signal", the "1 stroke"
The signal falls, thus completing a sequence and also resetting flip-flop 64. The F sequence is also the same as above.

A device trailing to the interface unit supplies an "F-mode" signal to the unit, which gates the "one character" signal into ROM2 for decoding. "1
When the STROBE signal goes up, the R2 register is loaded and flip-flop 64 is set. After performing its desired activity, the device performs the desired "
Place a code to select the "F character" signal on the "Character selection" line, and raise the "F sequence start" signal. This causes line S2 to rise and, after a short delay by delay circuit 65, the "F Strope" signal to rise. Therefore,
The "F letter" signal is placed on sub-bus 11, and after the time required for this signal to stabilize, the "F strobe"
The signal rises. "1 When the strobe J signal falls,
The "F strobe" signal also falls accordingly. "Input characters available" for either 1 mode or F mode
The signal goes down at the completion of the sequence.

Using ROM in this application provides several advantages.

First, device-dependent signals such as "character select" and "input character" signals can be converted in any manner to actual character signals placed on the sub-bus. Second, character signals placed on the sub-bus can be defined and their meanings standardized without any changes to the devices connected to the programmable interface unit. Third, arbitrary error detection and/or correction codes can be added to the output "1 character" and "F character" signals, and input characters can be decoded in an equivalent manner. To realize this posthumous functionality, it is only necessary to increase the size of the ROM, for example to generate and decode encoded characters. Additionally, the arrangement of FIG. 7 allows all or part of the output of ROM 2 to be fed back to other device interface signals, such as the ``Start of Sequence'' or ``Character Select'' signals.

In this case, once activated, the programmerful interface unit proceeds directly through several character exchange sequences without requiring any interaction with the device. Also, since the content retrieved from ROM 2 is a function of the mode and the input character, the next character sent out for this unit's half-time is also a function of the previous input character. Thus, complex communication sequences between interface units can be integrated in the units, so that little or no programmability needs to be provided to the devices coupled to the bus system by these units. do not have. Therefore, "input character" and "
The use of the "Character Select" signal allows the programmerful interface unit to be a relatively complex controller for a simple peripheral device. This is discussed in more detail below in connection with FIG. The programmerful interface unit of FIG. 7 has a modular structure. The size of the ROM is relatively arbitrary and can be changed to the number of bits needed to interface the device. The constraints are that the number of bits per word in ROM1 is at least equal to the number of bits in the "1 character" signal, and the number of address bits in ROM2 is at least equal to the number of bits in the "F character" signal. This means that they must be equal. ROM
The number of words in I or the number of bits per word in ROM2 can be freely adjusted to meet the requirements of the device to which this interface unit is to be connected. As already explained, the basic bus configuration according to the invention can be extended, for example by adding "bus request" and "bus grant" signals in situations where multiple initiating modules are present, or by adding "bus request" and "bus grant" signals, Just add a wide data path controlled by the configuration. Such a mechanism can be easily added to the basic programmerful interface unit shown in FIG. For example, the programmable interface unit is
Certain bits of the ``Input Character'' and ``Character Select'' signals may be used to gate data onto and retrieve data from the data sub-bus. The initiation module of the present invention having the above-mentioned functions is the eighth
It is detailed below with reference to figures and tables (see below).

Table 1 describes the code names for the "1 character" and "F character" signals for the sample transfer described in connection with FIG. Table 2 shows the corresponding programming of the ROM utilized in connection with FIG. Table-1 11 - CPU and 1-character code for "Continuation--Reading--Calculation-Writing--Data transmission" 13 - "End of discussion - Calculation at a glance" - One-letter code FI for "data on the bus" - F-letter code for "proposal - start of integrated calculation - address retrieval" or failure) FIC-Disable one-letter code for follower module F
2 - F character code for "data on bus" F3 - F character code table for "data reception - sequence completion" - 2 So=1 occurs when there is an error in the "F character" signal.

SI=1 means that the start module tells the CPU “
This is the case when requesting data to be placed in the ``data output register'' and then raising the continuation signal.

S2=1 if the initiating module is able to continue operating on the next "one character" signal without requiring CPU intervention.

S3=1 if the initiating module enables the Data In Register to receive the data sub-bus when the F Strobe signal rises.

S4:1 occurs when the "data input register" has data.

S5=1 when the sequence is completed.

S6=1 when data is output from the start module.

Details of the arrangement shown in FIG. 8 will become apparent from the operation during a typical cycle, which will be described below in connection with the timing diagram of FIG.

At the beginning of this cycle, the CPU places the code for the "Issue-Calc-Write-Start" operation on the input line of the start module and places the address data in the data output register 75 with the input code equal to "11". .

In the next step, the CPU runs the "Start module start" line 8
1 is raised, which causes the CPU start code to be latched into 1 latch 87 via AND circuit 83 and OR circuit 85. At the same time, F latch 91 is reset by the signal on line 81- and one-strobe flip-flop 93 is set from line 81 via OR circuit 95. As a result, a code "11" is placed in the 1 latch 87 and a 0 is placed in the F latch 91, so that the (11, 0) word is read from the ROM 97. 1
The output of the strobe flip-flop 93 is connected to the delay circuit 9.
Connected to 6.

Delay circuit 96 is provided to provide sufficient time for accessing ROM 97 with the output of latch 87.
At the end of this delay, a signal is sent over line 99 to
Activate D circuits GI and G2.

When these AND circuits are activated, single character sub-bus 9 and data sub-bus 17 transfer the "11" code and its address, respectively. At this time, ROM9 is in the darkness
AND circuit G2 is activated by the output S6 from 7. Shortly after this, an output is generated from delay circuit 98 causing the "1 strobe" signal to rise.

Delay circuit 98 is provided to provide the necessary time for the signals on single character sub-bus 9 and data sub-bus 17 to stabilize. At this stage, the initiating module is ready to use when the follower module receives the address and the "F character".
Wait to respond by returning the signal. If all operations are correct, the "F character" signal is F
Equal to I. If there is a memory failure, the nuclear memory
If the bus monitor were to return another F character code such as ``FIE'' or ``FIC,'' or if the follower module failed, the bus monitor would cause a timeout. However, it is assumed here that the F character sub-bus 11 transfers the "FI" code. According to this assumption, the follower module places a "FI" code on the F character sub bus 11 at this time, indicating that the address has been received and that the initiator module should proceed. After this, “F
Strobe” signal rises. When the "F STROBE" signal rises, the contents of 1 character sub-bus 9 and F character sub-bus 11 are latched into 1 latch 87 and F latch 91, and 1 strobe flip-flop 93 is ORed.
It is reset by the "F STROBE" signal supplied via circuit 113.

Then, after a delay equal to the access time of ROM 97 is provided by delay circuit 96, the signal on line 99 falls, disabling AND circuits GI and G2.

Also at this time, status signals SO through S5 are activated as the output of the word located at (11, FI) in ROM 97, and a delay time is started to lower the "1 strobe" signal. After the delay by the delay circuit 98,
The "1 strobe" signal falls, thus causing the tracking module to eventually drop the "F letter" and "F strobe" signals.

In this situation, the signal S2 at the input of AND circuit 115
is at a high level, so one strobe flip-flop 93 will be set when the "F Strope" signal falls.

This means that the programming of the start module is
Indicate that the next command was allowed to be sent without intervention.

After a delay by delay circuit 96, line 99 is raised and RO
The word (11, FI) of M97 is output and “1
The "12" code is gated to the single character sub bus 9 via the AND circuit GI in a manner similar to that described above for the "1" code.

In this case, the “12” code is “12” includes “Issuance and calculation included -
After a delay by delay circuit 98, the ``1 strobe'' signal rises and the system thus waits for activity on the part of the tracking module.

At this time, the tracking module places an "F2" code on the F character sub-bus 11 specifying "data on the bus."

Furthermore, the follower module places the required data word on the data sub-bus 17 and thereafter raises the "F strobe" signal. Since signal S3 is active at this stage, this data is latched into data input register 76. Due to the rise of the “F strobe” signal, “12
” and “F2” codes are 1 latch 87 and F latch 91
and one strobe flip-flop 93 is reset.

After a delay by delay circuit 96, AND circuit GI is deenergized and status signals S1 and S4 are supplied from ROM 97 to the CPU. The rise of signal S4, relative to CP, signals that data input register 76 has a memory word. The rise of signal SI indicates to the CPU that the initiation module is now waiting for the return of the data word by the CPU. After the delay by delay circuit 98, the ``one strobe'' signal falls, and the follower module causes the F strobe, F character, and data sub-buses 7, 11, and 17 to fall accordingly.

Meanwhile, the CPU removes data from data input register 76, modifies it, and places the resulting data in data output register 75.

The CPU then raises the continuation line through OR circuit 95, setting one strobe flip-flop 93. This flip-flop is only set after the F STROBE signal falls, to eliminate invalid sequences if the CPU is faster than the tracking module. After the delay by the delay circuit 96, the ROM
“13” code from word 97 (12, F2) is AN
gated to single character sub-bus 9 via D circuit GI;
Then, in order to output data from the data output register 75 to the data sub bus 17, the signal S6 is sent to the AND circuit G2.
energize. After the delay by the delay circuit 98, the "one strobe one stroke code" rises, thus the follower module is "13"
Receive the code and then write the data back to memory. The follower module then places an "F3" code on the F character sub-bus 11 indicating that the data has been retrieved, and also raises the "F strobe" signal. 93 is reset and word (13, F3) is also read from ROM97.
To read the ``13'' and ``F3'' codes are latched into 1 latch 87 and F latch 91, respectively. After a delay by delay circuit 96, AND circuits GI and G2 are de-energized, and after a delay by delay circuit 98, the "1 strobe" signal falls. After that, the tracking module will
"character" and "F strobe" signals are lowered, and "
When the "F STROBE" signal falls, it functions to transfer a signal S5 to the CPU specifying sequence completion.
Now that we have explained the operation of the start module, let's move on to the first module.
Timing diagram in Figure 1 and ROM in follow-up module
The configuration and operation of the typical tracking module shown in FIG. 10 will be explained with reference to Table 3 showing part of the code.

Table-3 R provided in the tracking module in relation to the following explanation
The following meanings are given to the output status signals of the OM.

That is, the signal FSO latches the address register 205, raises the "F strobe signal" and instructs to start the bell, the signal FSI waits for memory completion and then outputs the data from the memory to the output register 209. , energizes AND circuits FGI and FG2, and instructs the "F STROBE" signal to rise, signal FS2 clocks data into data input register 211 and writes it to memory. Raise the START signal, wait for memory completion before raising the "F STROBE" signal, and indicate to reset the F latch. This description assumes that the preceding sequence has completed successfully and that the ROM's F character output is an "FC" code indicating sequence completion.

It is also assumed that the sequence described below is performed at the follower module end of a "problem-compute-write" sample sequence, and that the follower module is connected to a memory device. The operating cycle is initiated by the initiating module placing the ``11'' code on the character sub-bus 9, the address on the data sub-bus 17, and raising the ``1 stroke''.
1 Strope” signal rises, “11” and “FC
” code is loaded into the 1 latch and the F latch, respectively. Also, F Stroop Fritzpf. 150 is set, a delay by delay circuit 151 is started. At the end of this delay, the ROM word (11, FC)
A signal FSO is applied from the AND circuit 201 to energize the AND circuit 201. This circuit connects the output of the ROM to the F character sub bus 11.
AND circuit FG via OR circuit 203 in order to
Energize I. Additionally, address register 205 is enabled to receive data from data sub-bus 17 at this time. The output of the OR circuit 203 is sent to the delay circuit 15.
3 and at the end of the delay, the "F Strope" signal is raised. If you recognize this rise,
The initiation module removes the address from the data sub-bus 17, removes the ``1L code'' from the single character sub-bus 9, and also lowers the ``1 strobe'' signal.

The fall of the ``rl strobe'' signal resets the F strobe flip-flop 150, resulting in
The ND circuit FGI is deenergized and the "F strobe" signal falls. At this stage, the start module places a ``12'' code on the 1-character sub bus 9 and ``1 strobe''.
Raise the signal.

The "12" code is now loaded into 1 latch, and the F
Strobe flip-flop 150 is set to begin another cycle of delay circuit 151. During this time, the line FSI goes up at the output of the ROM, making it possible to check whether the memory logic has been completed. When the memory is complete, AND circuit 207 is activated by the rise of the memory complete line, thus allowing the data output register 209 to be loaded with the memory's data output. AND circuit FGI is activated via OR circuit 203, and at the same time, data output register 20
A to thin data from 9 to data sub bus 17
ND circuit FG2 is activated. After a delay by delay circuit 153, the "F strobe" signal rises. If this rise is recognized, the initiating module
7 and lowers one character sub-bus 9 and one strobe sub-bus 5. When sub-bus 5 falls, the follower module resets F strobe flip-flop 150, de-energizes AND circuits FGI and FG2, causes data sub-bus 17 and F-character sub-bus 11 to fall, and then Lower the strobe sub bus 7.

When providing data to be stored in memory, the initiation module performs the following activities.

In other words, data is placed on the data sub bus 17 and
13'' code on one character sub-bus 9 and raises one strobe sub-bus 5. At this stage other subcycles are carried out as described above, during which
Information is loaded into the 1 latch and the F latch, and the F-strope flip-flop 150 is set to begin the cycle of placing data on the F character sub-bus 11. At the end of the delay by delay circuit 151, the output of the ROM is available on line FS2 and is used to clock data surf bus 17 into data input register 211 and initiate a memory write cycle. The write start line can be raised to command. If the memory has started a write cycle, the memory complete line goes down; if the write is completed, the memory complete line goes up, which energizes the AND gate FGI and raises the F strobe sub-bus 7. .

At this time, the initiating module
, the code is taken from the one-character sub-bus 9, and the one-strobe sub-bus 5 is lowered.

This 1 strobe sub-bus 5 falls, resulting in F strobe. Flip-flop 150 is reset and AN
D circuit GI is deenergized and F strobe sub-bus 7 is lowered. The F latch is also reset with the "FC" code indicating that the tracking module has completed its cycle. In connection with FIG. 5, the bus monitor was described as including a character verification device 41.

FIG. 12 shows an arrangement that can perform the functions of such a verification device 41. As seen in this drawing, the basic unit of this character verification device is a ROM 301.
For this example, it is assumed that the "1 character" signal consists of N bits of information and the "F character" signal consists of M bits of information. Therefore, ROM 301 has 2N+M 3-bit words. Of the 3-bit word, bit 0 indicates an invalid "1 character" signal and bit 2 indicates an invalid "1 character" signal.
F character” signal, and bit 3 signals “1 character” and “F
"Character" indicates an invalid combination of signals.

The device has a set of latches 303 connected to the 1 character sub-bus 9 and a set of latches 304 connected to the F character sub-bus 11.

Line 3 from the protocol/timing inspection device 31 to be described later
When a strobe signal is received through 2, the output of the latch is loaded into ROM 301. In this case, R
Combination of inputs given to OM301 and ROM301
The ROM output is given according to the program. After a delay by delay circuit 305, the output data of 3-bit latch 307 is transferred to line 4, as described in connection with FIG.
3, 45 and 47. In any case, the first
ROM 301 used in a character verification device as shown in Figure 2
has input address bits equal to the number of lines contained in at least one character sub-bus 9 and F character sub-bus 11, and corresponds to various combinations of "1 character" and "F character" signals. Each word shall have at least 3 bits. FIG. 13 depicts an arrangement that may be used in the protocol timing checker 31 described in connection with FIG. The device includes four flip-flops 401, 403, 405 and 407 respectively indicating states A through D of FIG. These flip-flops are 1 strobe sub bus 5 and F strobe. It is connected to the sub-bus 7 and also to the preceding flip-flops in order to verify that the sub-bus is operating in the proper sequence as shown in FIG. If such a sequence is not confirmed, appropriate instructions will be given. Under condition A, where the ``1 strobe J'' and ``F strobe'' signals are both at the down level, AND circuit 427 energizes the set input of flip-flop 401. Therefore, flip-flop 401 turns on and indicates state A. Line 429 is fed back to one input of AND circuit 431, so that when the input of AND circuit 427 changes, AND circuit 431 is energized and resets flip-flop 401. Fritsuf. The output of flop 401 is also provided via line 429 to one input of AND circuit 435, the other input of which is routed to F strobe sub-bus 7. If the "F STROBE" signal is to go up at this time, the other input of AND circuit 435 is activated, and via OR circuit 437 latch 423 is activated.
is set, resulting in a tracking module fault indication on line 33. However, if this sequence does not occur properly, i.e., if the ``1 STROBE'' signal goes up while the ``F STROBE'' signal goes down, each input of AND circuit 439 will be energized and its outputs will be ANDed. It is given to one input of the circuit 441. Since flip-flop 401 is on at this time, flip-flop 403 is set on. As already pointed out, in response to the rise of the "1 strobe" signal, a reset signal is supplied via the AND circuit 431, so that the flip-flop 401 is now turned off. Flip-flop 403 turning on signals by its output on line 443 that the transition to state B has been successfully made. The output on line 443 is provided to the reset circuit of flip-flop 403 in the same manner as described above for flip-flop 401. The output on line 443 also starts operation of timer 413. If the F STROBE signal is down at the time that timer 413 times out, an output is provided from AND circuit 445 which turns on follower module fault latch 423 via OR circuit 437. . This operation corresponds to the transition from state B to state E, as shown in FIG. If line 4
If the "1 strobe" and "F strobe" signals both go up while 43 is up, flip-flop 405 is set via AND circuits 447 and 449, and its on state causes state C to be set. Instruct. Therefore, there is an output on line 451 at this time.

This output is connected to a strobe line 32 which is used to energize the character verification device described above. Timer 415 provides a time-out function following state C, which causes a transition to state F as shown in FIG. If the "1 strobe" signal falls while the "F strobe" signal and line 451 are up, the circuitry that is obvious from the drawings is applied to flip-flop 407 representing state D.

The time-out function provided by timer 417 is controlled by the output of flip-flop 407. If a time-out occurs, an input is provided to latch 423 via OR circuit 437. A legal transition from state D is to a state where the "1 strobe" and "F strobe" signals are both down.

The outputs of timers 413 and 417 create condition E, which indicates a fault in the follower module, via OR circuit 437, latch 423 and line 33, while the output of timer 415 produces condition E, which indicates fault in the follower module, via OR circuit 453, latch 425 and line 35. causes state F, which indicates a failure of the initiating module.

Referring to the circuits of FIG. 13 in conjunction with the state diagram of FIG. 6, an examination of all state handling transitions made by the apparatus will be apparent.

As can be seen from the foregoing description, the present invention provides an improved data communications bus configuration with novel means for verifying correct operation, and a novel interface unit used in connection therewith. provided.

[Brief explanation of the drawing]

1 is a schematic block diagram showing the main elements of a bus configuration according to the invention; FIG. 2 is a timing diagram showing the timing relationships between the signals on the sub-bus; and FIG. 3 is an application of the invention. 4 is a timing diagram related to FIG. 3; FIG. 5 is a block diagram showing components of the bus monitor of FIG. 3; FIG. 6 is a protocol timing check of FIG. 5. FIG. 7 is a state diagram illustrating the states of device 31 and their transitions; FIG. 7 is a block diagram illustrating one form of a programmable interface unit according to the invention; FIG.
9 is a detailed block diagram of a typical starting module, FIG. 9 is a timing diagram showing the operation cycle of the starting module of FIG. 8, FIG. 10 is a detailed block diagram of a typical follow-up module, and FIG. 12 is a block diagram showing one form that can be used as the character confirmation rhombus 41 in FIG. 3 is a block diagram of one form that can be used as device 31. FIG. 1...Starting module, 3...Following module, 5
...1 strobe sub-bass, 7...F strobe
Sub bus, 9...1 character sub bus, 11...
・F character sub-bus, 13...Reset line, 1
5...Bus monitor. FHG. IF;G. 2 FIG. 3 FIG. 4 FIG. 5 FIG. 6 Fig. 7 FIG. 8 FIG. 9 FIG. 10 Yen G - FTG. 12 FIG. 15

Claims (1)

[Claims] 1. At least one start module and at least one follower module are interconnected by an information signal bus, and information signals are transferred between the start module and the follower module via the information signal bus. a data communication device, comprising: a control signal bus connected to the start module and the follower module to transfer control signals between the start module and the follower module; a first character sub-bus and a first strobe sub-bus driven; a second character sub-bus and a second strobe sub-bus driven by the follower module; When an information signal is transferred to the follow-up module, a first control signal generated by the control signal generating means in the start module is transmitted to the first supplying a first strobe signal generated by strobe signal generating means in the start module to the first strobe sub-bus at a predetermined time after generation of the first control signal; Only when the strobe signal receiving means in the following module receives the first strobe signal on the first strobe sub-bus, the control signal receiving means in the following module is enabled to receive the first character. receiving the control signal on the sub-bus, and supplying a control signal for controlling the processing operation of the information signal in the follow-up module from the control signal receiving means; When an information signal is transferred to an initiating module, a second control signal generated by the control signal generating means in the follower module for controlling the processing operations of the initiating module with respect to the information signal is expressed by the second character. supplying a second strobe signal generated by strobe signal generating means in the follower module to the second strobe sub-bus after a predetermined time from generation of the second control signal;
Only if the strobe signal receiving means in the starting module receives the second strobe signal on the second strobe sub-bus will the control signal receiving means in the starting module be enabled to read the second character. A digital data communication device, wherein the control signal on the sub-bus is received, and a control signal for controlling the processing operation of the information signal in the start module is supplied from the control signal receiving means.