JPH0381146B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing apparatus that can perform image processing using a plurality of control means.

[Prior Art] Recent advances in electronic technology have been remarkable. In particular, the integration of electric and electronic circuits has progressed, and high-performance microcomputers have appeared and are used to control various devices. Recently, it has become common to use microcomputers to control image processing devices such as copying machines and printers. However, when equipment is required to have even higher performance, functionality, and multi-functionality,
It has become necessary to use multiple microcomputers for control rather than one microcomputer.

However, as the number of operating parts and displays increases due to the increase in the number of control means, as well as the further increase in speed, multifunction, and sophistication of image processing devices, there are problems with the reliability of data transfer and the problem of the reliability of each part. There was a need to give greater consideration to control consistency.

[Objective] In view of the above points, the present invention aims to eliminate the above-mentioned drawbacks.

In view of the above points, the present invention uses a plurality of control means to control image processing. By prohibiting the storage of further data after it is stored in memory, and allowing it after the transfer is complete, data destruction may occur, such as erasing the previous data before transfer. An object of the present invention is to provide an image processing device that can prevent such problems from occurring.

Furthermore, in the present invention, since the transferred data is mutually transferred to an area where no useful data is stored, useful data is not destroyed at the transfer destination, and high-performance image processing can be performed. An object of the present invention is to provide an image processing device that can be accurately controlled.

[Example] The present invention will be described below using a copying machine as an example of an image processing apparatus. FIG. 1 shows a sectional view of a copying machine to which the present invention is applicable. The surface of the drum 11 is made of a three-layer photoreceptor using a CdS photoconductor, is rotatably supported on a shaft 12, and starts rotating in the direction of an arrow 13 in response to a copy command.

When the drum 11 rotates to the normal position, the document placed on the document table glass 14 is illuminated by an illumination lamp 16 that is integrated with the first scanning mirror 15, and the reflected light is used for the first scanning. Mirror 15 and second
It is scanned by a scanning mirror 17. First scanning mirror 1
5 and the second scanning mirror 17 move at a speed ratio of 1:1/2, so that the original is scanned while the optical path length in front of the lens 18 is always kept constant.

The above reflected light image shows the lens 18 and the third mirror 19.
After passing through the fourth mirror 20, the exposure section 21
Then, an image is formed on the drum 11.

After the drum 11 is charged (for example, +) by a primary charger 22, an image irradiated by an illumination lamp 16 is slit-exposed in the exposure section 21. At the same time, AC or primary charge removal with a polarity opposite to that of the primary charge (for example, -) is performed by a charge remover 23, and then a high-contrast electrostatic latent image is formed on the drum 11 by full-surface exposure using a full-face exposure lamp 24. The electrostatic latent image on the photosensitive drum 11 is then visualized as a toner image by the developing device 25.

The transfer paper 27-1 or 27-2 in the cassette 26-1 or 26-2 is transferred to the paper feed roller 28.
-1 or 28-2 into the machine, the first register roller 29-1 or 29-2 takes approximate timing, and the second register roller 3
With accurate timing at 0, the photosensitive drum 11
sent in the direction.

Next, while the transfer paper 27 passes between the transfer charger 31 and the drum 11, the toner image on the drum 11 is transferred onto the transfer paper.

After the transfer is completed, the transfer paper is guided to the conveyor belt 32, and then to a pair of fixing rollers 33-1, 33-2, where it is fixed by pressure and heat, and then discharged onto the tray 34.

After the transfer, the surface of the drum 11 is cleaned by a cleaning device 35 composed of an elastic blade, and the process proceeds to the next cycle.

Further, in order to control the above image forming cycle at each point in time, a drum clock pulse DCK is generated by a sensor 11b which optically detects the clock point of a clock board 11a which rotates with the rotation of the drum 11.

FIG. 1-2 is a plan view of the operation section of the copying machine shown in FIG. 1-1, in which 40 is a key for starting a copying operation, 41 is a numeric keypad and clear key C for setting the number of copies, and 42 43 is a sliding resistance for determining the copy density, 44 and 45 are keys for selecting paper feed from each cassette 26-1 and 26-2, and 46 is a numeric keypad. 41 indicates the set number, and 47 indicates the copy count number, each consisting of a 7-segment LED with two digits. If the clear key C is turned on during repeat copying using the key 41, the repeat copying is interrupted and the remaining number of copies is canceled, but even if the stop key 42 is turned on, the remaining copying can be continued and completed by simply interrupting the repeating. can. While the repeat is interrupted by this stop key,
When the interrupt key 48 is turned on, the memory associated with the indicators 46 and 47 and the number associated with the first copy of the counter are saved in another memory area, and 1 and 0 are displayed on each indicator. This allows the desired number of second copies to be executed and completed during the repeat interruption, and then the first copy can be resumed.

The control circuit shown in FIG. 2 will be explained. In the diagram
MCOMA, B is each microcomputer,
The MCOMA inputs and sets the desired number of copies using the key 41, drives the display 46 to notify the operator of the number, and drives the display 47 to add to the number of copies remaining during copying. Also key 4
Sense input 0 and output copy start signal,
It controls the output of a stop signal by the key 42, a cassette select signal by the cassette select key, and a display signal corresponding to the selection. For this purpose, it has a built-in memory (ROM) programmed with instruction code routines. The MCOMB outputs sequence control for each operating load to perform charging, exposure, and other copying processes necessary for copying operations. For this purpose, it has a built-in memory (ROM) programmed with instruction code routines. The MCOMA has a memory (RAM) that can store necessary copy numbers, copy set numbers, etc. in addition to display, and the MCOMB has a memory (RAM) that can temporarily store timing data and other data necessary for sequence control. Also, each computer has a shift register function.

In this example, it is possible to provide a copy control method that skillfully utilizes this shift register function. This makes it extremely easy and fast to control a diversified copying machine that has a large number of operating loads, a large number of displays, a large number of input sensors, and a large number of command input keys, especially a copying machine that uses multiple computers. can be achieved.

That is, data is exchanged between MCOMA and MCOMB by serial transfer using this shift register function.

In the figure, the output port SO of MCOMA and B is used as a serial signal output port, the input port SI is used as a serial signal input port, and the port SCK is used for inputting and outputting a shift clock pulse. MCOMA's SO is
MCOMB's SI, B's SO to A's SI, and
SCK comrades are connected to each other. Port PA1 is
A port that outputs the signal REQO to notify B of data transfer in advance from MCOMA to B.
PB1 of MCOMB is a port for inputting the signal, and PA1 and PB1 are connected to each other.
Port PB2 of MCOMB is a port that outputs a signal (REQE) indicating that the MCOMB reception system is ready, and port PA2 of MCOMA is a port for inputting this signal.

Here, for example, in order for MCOMA to judge that the copy key 40 has been turned on, and to start operating the copying load connected to MCOMB, MCOMB
Send start command data from MCOMA to.
To do this, set the start command data in the MCOMA shift register and prepare to output it from port SO. Then, a signal REQO indicating that data transfer is desired is sent from port PA1 of MCOMA to input port PB1 of B. At MCOMB, set the shift register of B to output data indicating the current state of the copying machine, for example, whether copying is suspended or in standby, from B's output port SO, and notify A that B is ready for transfer. Boku Port PB
2 transmits the enable signal REQE. and
When MCOMA receives REQE from B and senses it, it starts data transfer from A's SO to B's SI. At the end of the transfer, these data are determined by internal interrupt processing in MCOMA and B.

FIG. 3 is a circuit diagram of the shift register in MCOMA,B. The operation of the shift register 300 can be controlled by software controlling the register control flip-flop 302 (hereinafter referred to as register F/F), and the generation of internal interrupt instructions is controlled by the interrupt flip-flop 303 (hereinafter referred to as interrupt F/F).
F). The interrupt F/F is set by the interrupt enable signal E and the signal STP generated when the shift register stops operating. Furthermore, the shift register 300 is connected to the accumulator ACC of 301 through the internal pass line of the microcomputer, so that data can be set from the ACC to the shift register, and data can also be set from the shift register to the ACC.
You can also move data to .

FIG. 4 is a detailed diagram when the transfer means using a serial shift register is connected by MCOMA and B. The shift register used in the present invention has a 16-bit shift register, and each has 4-bit unit shift registers STO to ST3. Further, the shift register operates in synchronization with the shift clock SCK. Note that, as is clear from the figure, the mutually transferred data is transferred to an empty area of the shift register, that is, an area where there is no useful data. Also, regarding the shift clock, in this example, the shift clock is generated from MCOMB.

FIG. 5 is a timing diagram of serial data transfer. As explained above, REQ-O and REQ-
By each signal of E, MCOMA and B set their respective data in the shift register, set the interrupt enable output, and set the shift register F/F, thereby generating the shift clock SCK from MCOMA and transmitting the mutually set data together with the shift clock. Transfer data to each computer. Then, when the shift clock ends, an internal interrupt is generated in both MCOMA and B, and data is determined within each internal interrupt process.

FIG. 6 shows various data contents for transferring information from MCOMA to MCOMB, and FIG. 7 shows data contents for transferring information from B to A. That is,
The shift register ST2 of MCOMA stores data of cassette stage and cassette size, data 9 indicates a small size in the upper stage, and data 1 indicates a small size in the lower stage. Note that the copying machine shown in FIG. 1 is of the upper and lower stage type, so the middle stage data is not used. In the shift register ST3, 13 indicates copy start command data, and 14 indicates copy stop data. The shift register of MCOMB in FIG. 7 stores data indicating control mode (ST3), timing mode (ST2), jam mode (ST1), and sequence mode (ST0) by MCOMB. For the data indicating the standby mode in which several new sets can be input using the key 41 and the copy is completely completed and the drum is stopped and paused, set O to ST0.
While repeat copying is in progress, the data indicating from the copy key-on to the last transfer is 8 in ST0, and the following data indicates the drum post-rotation mode (until the drum stops) for so-called cleaning and potential equalization after the last transfer of repeat copying is completed. 10 is the data indicating the mode in which the drum is stopped due to a jam etc. and the number cannot be changed using the key 41 (after the jam is detected until the copy key becomes available), 11 is the optical system that causes the MCOMA copy counter to count up. 10 is stored in the register ST0 as data indicating the start time of the return operation, and 12 is stored in the wait mode data that cannot be copied even if the copy key is turned on after the power is turned on. If the sheet sensor 390 in FIG. 1 does not sense the sheet within a predetermined time after starting paper feeding, set 1 to ST1
2 when the output sheet sensor 39 senses the skew of the sheet, 3 when the output sheet sensor 39 is present on the sensor 390 for a predetermined time or more, and 4 when the output sheet sensor 39 does not sense the sheet within a predetermined time after the detection operation of the sensor 390. 5 if it stays for more than a predetermined time, 15 if execution of the above jam detection routine program is prohibited.
Set. This prohibition mode is set by switching (grounding) one of the MCOMB input ports before starting copying.

By the way, when the apparatus is systemized, it becomes necessary to provide the copying machine shown in FIG. 1 with a device (ADF) that automatically feeds and sets originals on a platen and a sorter device (SOT) that distributes copy paper.

FIG. 8 shows the copying machine shown in FIG. 1 provided with an ADF and SOT, and FIG. 9 is a control circuit diagram for controlling the ADF and SOT based on the control method described above. MCOMA,B is the same as above,
MCOMC controls the ADF, and MCOMD controls the sorter. This is a control block diagram in which serial shift registers serving as information exchange means are connected in series as shown in FIG. 8 to enable efficient transfer.

Figure 9 provides an optimal control method when ADF, sorter, etc. are added to the equipment shown in Figure 1, as illustrated in Figure 8, and is a control block diagram in which serial shift registers are connected in parallel. It is.
This means that the data transfer speed (time required for judgment) to the ADF and sorter is faster than when the serial shift register is transferred in series as shown in FIG.

FIG. 10 is a flowchart showing control operations by the microcomputer MCOMA for managing key entries, displays, etc. and the microcomputer MCOMB for controlling copy sequence shown in FIG. First, the management microcomputer
Explain MCOMA.

Execute the main flowchart from POWER ON by turning on the power switch SW, and proceed to step 1.
The key input determination and display processing of the operating section shown in FIG. 2 are performed immediately after the power is turned on. In step 2, check the register F/F. This register F/F is
Determine whether the aforementioned shift register in MCOMA is performing a transfer operation.

Next, in step 3, the flag 1, which was set when the copy key was pressed in step 1, is
By determining 0, input of the copy key is determined. If the copy key is pressed, the process moves to step 4 and the sequence MCOMB is created as shown in Figure 6.
13 is set in shift register ST3 as data for the copy start command to be sent to. That is, 13 is set in the accumulator ACC, and in step 5, the contents of the accumulator ACC are set in ST3 of the shift register.

Also, if the stop key is pressed, step 6
After determining this, 14 is set in the accumulator ACC in step 7, and data 14 is similarly set in the shift register ST3 in step 5.

After that, in step 8, the register F/F is set to enable shift register transfer, and the microcomputer
Interrupt to set interrupt F/F of MCOMA
Set the output of enable to output. Then, in step 9, set output port PA1 to MCOMB.
Send the REQ out signal to MCOMB. step 10
Then, it is determined whether or not REQenable from MCOMB has been input. When the REQenable signal is input, the process moves to step 11 and the REQout signal is reset. And starting with step 12, output port SO
Start data transfer from .

Next, MCOMB for sequence control will be explained. After turning on the main switch SW (POWER ON) as described above, check the copy preparation cycle in step 19, and check the copy preparation cycle in step 20.
Check the register F/F to confirm the transfer operation of the shift register in the same manner as in step 2. Next, in step 21, check whether there is a REQout signal for data transfer from MCOMA.
If there is a REQ, the process moves to step 22, and preparations are made to set the information to notify MCOMA of the operating status of MCOMB in the shift register (steps 22 to 22).
twenty four). Here, an example is shown in which MCOMB sets O to the register STO as standby state data. The data contents from MCOMB to MCOMA are shown in FIG.

After the data is set in the shift register, the register F/F interrupt enable output is set and the signal REQenable output port PB indicates that the data may be transferred.
2 is output in step 25. Then, in step 26, F/START is checked to indicate that the copy start command has been transferred by the interrupt routine. here
The interrupt routine that occurs when the data transfer is completed after starting data transfer in step 12 of MCOMA will be explained. The interrupt generation timings by MCOMA and B are almost simultaneous. Let me explain from MCOMA. When an interrupt occurs, the data sent from MCOMB is set in the shift register, so the contents of the shift register (only STO will be discussed here) are set in the accumulator ACC (step 13), and in steps 14 and 17, the contents of the shift register are set in the accumulator ACC. The contents are judged to determine what kind of data has been sent. At step 14
When ACC=0, it indicates that MCOMB is in standby state, and controls a processing flag that enables input from each key on the operation unit and display change using the keys (step 15). Also, if ACC=8 in step 17, it can be determined that MCOMB is in the process of copying, and a flag that enables inhibition of key input is controlled (step 18).
Then, in step 16, enable register F/F and interrupts.
Reset.

In the interrupt routine of MCOMB, the contents of the shift register are moved to ACC (step 35) as in the case of MCOMA, and if ACC = 13 in step 13, it is determined that it is a copy command, and in step 37, the flag F/
Set START. Also, at step 40, ACC=
If it is 14, it is considered as a copy stop command and the step
Set flag F/STOP at 41. Then, in step 38, the register F/F and interrupt enable output are reset, and in step 39, the REQenable output is reset. Therefore, the copying operation starts only when F/START is set at step 26 of MCOMB. The copying operation is at step 27. Steps 28 to 32 are for determining whether or not F/STOP has been sent in step 33. If a stop command is received, the process moves to step 34, which is the post-rotation cycle. Although the present invention has been described as an example of only copy start and stop, in reality, there are many types as shown in FIGS. 6 and 7, and copy control including key input and display is performed in the same way as described above. Incidentally, as is clear from the embodiment, MCOMA performs operation control in addition to display control, and even if the operation control and display control are appropriately divided and controlled by each control section, the present invention does not apply. It doesn't go against the main idea.

3 microcomputers as shown in Figures 8 and 9.
The case where the serial transfer means are connected in series and in parallel will be explained.

The data transfer means for each microcomputer is basically the same as above, but in order to reliably send each microcomputer's information to the desired microcomputer, assign an address number to each microcomputer and first determine whether the data is being sent to you. let For this purpose, when data is transferred, the microcomputer number of the transfer destination is added to the data.

FIG. 11 is an explanatory diagram of data when a transfer number is determined for each microcomputer. In other words, the transfer destination data of each microcomputer is distributed in advance to ST3 of the shift register. In this example, if ST3 is 0001,
MCOMA, 0010 as MCOMB, 0011 as MCOMC, and 0100 as MCOMD.
In this way, when each microcontroller sets the data to be transferred to the desired microcontroller, it inputs the transfer destination microcontroller number.
Set to ST3. Data transfer is then started, and the destination microcontroller checks the ST3 data that is serially output from port SO after an interrupt occurs, thereby determining in advance whether or not the data is being sent to itself. If the number in ST3 is the data sent to you, the following ST0 to ST2
Read the data and judge the data content.

The flowchart of FIG. 12 specifically shows this. FIG. 12 shows an interrupt routine caused by the occurrence of an interrupt after data transfer by each microcomputer.
That is, each microcomputer first moves ST3 of the shift register to the accumulator (ACC) in step 50, and checks the contents of the accumulator in step 51. If the content of the accumulator is 1,
MCOMA, MCOMB for 2, MCOMB for 3
MCOMC, MCOMD in the case of 4, so if each microcontroller determines that it is its own data, step
At step 52, the contents of the shift registers ST0 to ST2 are stored in a data memory (RAM) via an accumulator, and at step 53, the contents of the data stored in the RAM are determined and the respective processes are performed. step
If it is determined in step 51 that the data is not the content that was sent to it, the process moves to step 54. In step 54, preparations are made to immediately transfer the data sent as is to another microcomputer. On the other hand, steps 4, 5, and 7 in FIG.
Same as 8, 9, 10, 11, 12. However, the MCOM number of the transfer destination must be set in register ST3 here. Therefore, from the above, the 8th and 9th
Even when the serial transfer means of three or more microcomputers shown in the figure are connected in series and in parallel, information can be easily exchanged between the microcomputers.
However, when the serial transfer means are connected in parallel as shown in Figure 9, the MCOMA plays the role of master central management, and only the MCOMA requires the processing steps shown in Figure 12 to determine the transfer destination data of each microcomputer. do. If connected to the series
Each of MCOMA to MCOMD requires a processing step to determine the transfer destination data. Therefore, it is advantageous to connect the serial transfer means in parallel as shown in FIG.

Also, in Figures 2, 8, and 9, the copy number display and wait up display 4 are displayed by the output of MCOMA.
8 and various other display devices, auto-off and hold control of the computer power supply, and load operation control for executing part of the copying process. That is,
When jam data is input from MCOMB,
You can turn on the MCOMA's jam display, change the number displayed on the copy number display 47 to a different number, or display +1 on the MCOMA's number display 47 when the optical system's double movement start signal is input. When detecting special troubles using MCOMB, the data
You can also reset the power by turning off the power of MCOMA for a predetermined period of time.

[Effects] As detailed above, the present invention controls image processing using a plurality of control means, and can transfer various data necessary for image processing to each other in large quantities and at high speed. After storing data in memory for transfer, further storage of data is prohibited.
Also, by allowing it after the transfer is completed,
This makes it possible to prevent data destruction from occurring, such as erasing previous data before transfer. Furthermore, since the transferred data is mutually transferred to an area where no useful data is stored, useful data is not destroyed at the transfer destination, and high-performance image processing can be accurately controlled. It has the effect of making it possible.

[Brief explanation of drawings]

1-1 is a sectional view of a copying machine to which the present invention can be applied, FIG. 1-2 is a plan view of the operating section of the copying machine shown in FIG. 1-1, FIG. 2 is a control circuit diagram of the present invention, and FIG. , Figure 4 is a detailed circuit diagram of the circuit diagram in Figure 2,
Figure 5 is the output time chart of Figure 2, Figure 6,
7 is a data content diagram in FIG. 2, FIGS. 8 and 9 are other control circuit diagrams, FIG. 10 is a control flowchart in FIG. 2, FIG. 11 is a circuit diagram of another control example, and FIG. The figure is a flowchart for the case of Figure 11. In the figure, MCOMA, MCOMB, MCOMC,
MCOMD is a microcomputer, 46,47
is a number indicator, SO is an output port, and SI is an input port.

Claims (1)

[Scope of Claims] 1. A plurality of operating means including paper conveyance for performing image processing, a first program memory means storing a program for controlling display related to image processing, a processor, and a capacity of a plurality of bits. and a first memory means for storing information indicating whether data can be stored in the first memory means for data transfer.
a first control means having a storage means; a second program memory means storing a program for controlling the plurality of operating means; a second memory means having a capacity of a processor and a plurality of bits; a second control means having a second storage means for storing information indicating whether or not data can be stored in the second memory means; a second control means having second storage means for storing information indicating whether data can be stored in the second memory means; A plurality of types of command data are serially transferred to the second memory means of the second control means, and a plurality of types of status data of some operation means stored in the second memory means are transferred to the second memory means of the second control means. 1
connection means connecting the first control means and the second control means for serially transferring data to the first memory means of the control means; Based on the information indicating whether or not the stored data can be stored, the first
The second control means enables data storage in the memory means, and the second control means controls the data transfer based on information indicating whether or not the data stored by the second storage means can be stored. to the second
After storing the data to be transferred into the first memory means, the first control means sets the first storage means and stores the data into the first memory means. prohibiting storage of further data to be transferred, and after the completion of the data transfer, resetting the first storage means to allow storage of further data to be transferred in the first memory means; After storing the data to be transferred in the second memory means, the means sets the second storage means to prohibit further storage of the data to be transferred in the second memory means, After the completion of the transfer, the second storage means is reset to allow further storage of data to be transferred to the second memory means, and the first control means causes the first storage means to transfer data to the first memory means. If the plurality of types of instruction data to be transferred are stored in the first memory means, the instruction data is transferred to the first memory of the second control means via the connection means. 2, and the second control means executes the program by the operating means based on the command data transferred from the first control means and the program stored in the second program memory means. After controlling execution of image processing and storing the plurality of types of situation data to be transferred in the second memory means, the situation data is transferred to the first memory means.
serially transferred to a free area of the first memory means of the control means via the connection means, and the first control means stores the transferred situation data and the program stored in the first program memory means. An image processing device that controls display related to the image processing based on the image processing.