JPH0646318B2 - Office equipment control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for office equipment such as a copying machine, and more particularly to a control device for office equipment using a control means for performing sequential processing such as a microcomputer. .

[Prior Art] In office equipment, especially in copying machines, switches, indicators,
It has a large number of components such as sensors, motors, solenoids, exposure lamps, heaters, etc., and its configuration is complicated. Therefore, it is difficult to control it.

FIG. 14 shows an example of a conventional control circuit configuration of a copying machine. In this example, three control units, that is, a sequence control unit 1, an operation control unit 2 and an optical system control unit 3 are provided, and each control unit is provided with a microcomputer. The sequence control unit 1 has an input terminal and an output terminal each having a large number of sensors 4,
A large number of actuators 5, a main motor 6, a fixing heater 7, an exposure lamp 8, a fixing controller 9, a lamp regulator 10 and the like are connected.

A large number of indicators 11 and a large number of key switches 12 are connected to the input terminals and output terminals of the operation control unit 2. A scanner motor 13, a mirror motor 14, a lens motor 15 and the like are connected to the input terminal and the output terminal of the optical system control unit 3.

In this example, a fixing controller 9 is provided to control the temperature of the fixing heater 7, and a lamp regulator 10 is provided to control the light amount of the exposure lamp 8. Fixing controller 9 and lamp regulator 10
Are each composed of an analog control circuit.

However, it is difficult to correct the energization phase angle with respect to the voltage fluctuation and to set the stepwise light amount in the lamp regulator configured by this kind of analog control circuit. When performing copy density adjustment, it is preferable to adjust the exposure amount according to the set density step, but for that purpose, it is necessary to use a lamp regulator that can accurately obtain a predetermined light amount for each step.

When the digital control is performed by using a microcomputer, the light quantity adjustment of the exposure lamp is simple and accurate.
As a lamp regulator of a copying machine using a microcomputer, for example, the one disclosed in Japanese Patent Laid-Open No. 59-88728 is known. However, if such a device is used as it is instead of the conventional analog type lamp regulator, the number of components increases, the configuration becomes very complicated, and the cost increases.

[Object of the Invention] It is an object of the present invention to accurately control an exposure lamp of an office equipment by digital control and to simplify the device configuration.

[Structure of the Invention] In order to achieve the above object, in the present invention, a plurality of input means (240); a plurality of display means (250); a data transmission means (B) for performing data transmission with another control device.
1); AC load means (8) including at least an exposure lamp; Switching means (TRC501 to TRC503) for controlling ON / OFF of energization of the AC load means; Outputting a signal according to the applied power of the AC load means Load state detecting means (150); zero cross detecting means (500) for outputting a signal synchronized with the zero cross point of the AC power supply waveform; and state reading scan control of the input means, dynamic display energizing control of the display means, other Control of data transmission with the control device, reading control of the signal from the load state detection means,
The calculation based on the signal and the control of the switching means according to the result are repeatedly performed at mutually different timings, and at least the 0th cycle is set according to the result of counting the synchronization signal (ZCP) output by the zero-cross detection means. Means for distinguishing from the first cycle (ZCPC
NT, S3, S5), in synchronization with the synchronization signal, the signal read from the load state detecting means is executed in the 0th cycle, and the signal is read in the 0th cycle in the first cycle. Electronic control means (10) for performing the calculation and controlling the switching means according to the result
0);

Note that the symbols shown in the above parentheses are reference numerals of corresponding elements in the examples to be described later, but each component of the present invention is limited to only specific elements in the examples. It is not something that will be done.

[Operation] According to the present invention, by performing time-division processing, a single computer device (electronic control means) performs digital exposure lamp control, input key scanning control, display dynamic display control, and the like. Therefore, many conventional analog circuits can be replaced with one microcomputer device.

By the way, when this type of time-division control is performed, the actual processing amount may be temporarily excessive compared to the limit of the processing capacity of the computer, and as a result, the control accuracy is expected to decrease. However, for example, in a copying machine or the like, unless the light quantity of the exposure lamp is controlled with high accuracy, the image quality is deteriorated.

Therefore, in the present invention, the synchronization signal (ZCP) output by the zero-cross detection means is counted and the 0th cycle (eg, positive half-wave of AC waveform) and the first cycle (eg, negative half-wave of AC waveform) are calculated. The signal is read from the load state detecting means in the 0th cycle in synchronization with the synchronization signal, and the operation is performed based on the signal read in the 0th cycle in the first cycle and the result thereof. The switching means is controlled.

In order to control the exposure lamp or the like with high accuracy, it is necessary to detect the effective value of the voltage applied to the exposure lamp and feed back the effective value to the control. , A large number of instantaneous values are sampled (process 1), the effective value is calculated from the instantaneous values, an appropriate control amount is calculated according to the effective value and the control target value, and the energization timing of the switching means is corrected (process 2). )Must. However, the "processing 1" causes a detection error due to a slight deviation in the timing of executing it, and the "processing 2" has a huge processing amount. Control error increases. However, according to the present invention, "Process 1"
Is executed in the 0th cycle and "Processing 2" is executed in the first cycle, so that there is no fear that the sampling timing is shifted, and high-precision control is realized.

By the way, office equipment such as a copying machine is equipped with a large number of key switches and a large number of indicators. Therefore, many signal lines are required to control them. When performing this type of control, conventionally, the Keith switch and the display are connected in a matrix to reduce the number of signal lines. However, it still requires quite a lot of signal lines.

If the number of signal lines increases, a single-chip microcomputer with a small number of input / output ports cannot support it, and the configuration becomes complicated. Therefore, in the preferred embodiment of the present invention, one of the rows and columns of the switch matrix and the display matrix is commonly connected to each other. This reduces the number of required signal lines,
The present invention can be implemented by a single-chip microcomputer.

Further, in a complicated device such as a copying machine, it is not possible to control all with only one control unit, and therefore, as shown in FIG. 14, for example, a plurality of control units each having a microcomputer are provided. In that case, wiring for data transmission between each unit is difficult. Therefore, in the preferred embodiment of the present invention, the parallel-serial conversion circuit and the serial-serial conversion circuit are
A parallel conversion circuit is provided to perform serial data transmission with another control unit. This reduces the number of wires.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1a shows a schematic electric circuit of one type of copying machine embodying the present invention. Referring to FIG. 1a, this electrical circuit is equipped with three large control units, a sequence control unit 20, an operation control unit 30 and an optical system control unit 40. Each control unit is equipped with a microcomputer.

The actuator 4 and the sensor 5 are connected to the sequence control unit 20. The operation control unit 30 is connected to a display 11 including a large number of display elements, a key switch 12 including a large number of switches, a main motor 6, a fixing heater 7, and an exposure lamp 8. A scanner motor 13, a mirror motor 14, and a lens motor 15 are connected to the optical system control unit 40. The sequence control unit 20, the operation control unit 30, and the optical system control unit 40 are connected to each other via a serial bus.

FIG. 1b shows the operation control unit 30 of FIG. 1a in more detail. Referring to FIG. 1b, this unit is equipped with a microcomputer 100. The serial bus has three signal lines SEL, TXD and RXD
It consists of TXD is a transmission line, RXD is a reception line, and SEL is a unit selection control line.

In this embodiment, the sequence control unit 20 shown in FIG. 1a takes the initiative in the serial bus, and by setting the level of the signal line SEL, the operation control unit 30 and the optical system control unit 40 are connected. One of them is selected, and data transmission is performed between the selected unit and the sequence control unit 20.

External interrupt request line I of the microcomputer 100
A zero-cross signal (pulse) ZCP indicating the zero-cross point of the AC power supply waveform is applied to NT. To the analog input port (AN) of the microcomputer 100, analog signals of a set voltage (SV), a lamp applied voltage (LV) and a fixing temperature (FT) are applied.

The keys (key matrix) and the display (light emitting diode matrix) are connected in a matrix. The 8-bit row line of the key matrix is connected to the input port PA of the microcomputer 100, and the 20-bit row line of the light emitting diode matrix is connected to the output ports PD, PB and PFH, and the key matrix and the light emitting diode matrix are each 8 The bit column lines are commonly connected to the output terminals of the decoder. The input terminal of the decoder is connected to the output port PFL of the microcomputer 100.

An exposure lamp, a fixing heater, and a main motor are connected to three lines L, H, and M connected to the output port PCH of the microcomputer 100, respectively.

That is, one microcomputer 100 controls reading and scanning of the key matrix, dynamic display energizing control of the light emitting diode matrix, serial data transmission control with other units, exposure lamp light amount (applied voltage) control, fixing heater temperature control, Controls the main motor.

Next, each control operation will be briefly described.

(A) Exposure lamp control: A signal level similar to the voltage applied to the lamp is repeatedly sampled at a short cycle from the signal line LV, converted into digital data, and the root mean square value is calculated to calculate the effective value. Calculate the voltage and set the level of the signal line SV to A / D
(Analog / digital: The same applies below) The energization phase angle of the exposure lamp is obtained from the difference from the target value data obtained by conversion. The phase angle is set in the timer, and the zero-cross signal Z
The timer is started in synchronization with CP, and when the timer times out, energization is started and energized until the half cycle of the alternating current ends. This operation is repeated.

(B) Heater temperature control A voltage proportional to the heater temperature is sampled from the signal line FT, A / D converted, an average value is calculated, and the result and a predetermined target value are calculated by PID (described later). The heater is energized only for the period of the wave number according to the result.

(C) Main motor control In response to a main motor on / off signal sent from the sequence control unit 20 via the serial bus, the main motor is energized if it is on, and the main motor is deenergized if it is off. .

In FIG. 1b, the interface circuit, the driver circuit, etc. for converting the signal level are omitted.

2a, 2b, and 2c show a specific configuration of the operation control unit 30 of FIG. 1a. First, refer to FIG. 2a and FIG. 2b. The microcomputer 100 used here is a single chip microcomputer 78PG11E manufactured by NEC. In addition to the microcomputer 100, the operation control unit 30 includes a reset circuit 110, a three-state buffer 120, comparators 130 and 131, a timer circuit 140, a level conversion circuit 150, drivers 160, 180, 190 and 22.
0, the decoder 170, the noise filter 200, the resistor arrays 210 and 230, etc. are provided.

The connector CN202 shown in FIG. 2a and the connector CN501 shown in FIG. 2c are connected to each other. 2c
Referring to the drawing, the exposure lamp LP, the main motor MT, and the fixing heater HT (corresponding to 8, 6, and 7 in FIG. 1a) are respectively triacs TRC501, TRC502, and TR.
It is connected to the power supply line (AC100V) via C503.

To the control terminal of the TRIAC TRC501, a trigger circuit including a photocoupler PC501 including a light emitting diode and a photothyristor, a diode bridge DB503, and the like is connected. Similarly, a control circuit of the triac TRC502 is connected with a trigger circuit including a photocoupler PC502 and a diode bridge DB504, and a control circuit of the triac TRC503 is connected with a trigger circuit including a photocoupler PC503 and a diode bridge DB505. .

The circuit consisting of the transformer TR501, diode bridge DB501, transistor Q501, etc. is the zero-cross detection circuit. The transformer TR501 steps down and insulates AC100V AC voltage to a low voltage and isolates its output signal from a diode bridge.
DB501 performs full-wave rectification. The transistor Q501 is normally on and turns off when the level of the rectified signal is near zero. A zero-cross signal is obtained by turning on / off the transistor Q501. This zero-cross signal is sent to buffer 1
It is applied to two external interrupt request input ports INT1 and PC3 of the microcomputer 100 via 20.

A circuit consisting of a transformer TR502 and a diode bridge DB502 detects the applied voltage of the exposure lamp. Transformer TR502
Reduces the AC voltage applied between both terminals of the exposure lamp LP, and the diode bridge DB502 full-wave rectifies the AC voltage. The output of this circuit is applied to the analog input port AN1 of the microcomputer 100 via the level conversion circuit 150. The variable resistor VR201 of the level conversion circuit 150 is for full-scale adjustment, and is adjusted so that the peak value of the ramp voltage signal matches the full-scale level of the analog input port AN1.

A thermistor TH is provided near the fixing heater HT. The output terminal of the thermistor TH is the connector of Fig. 2a.
It is connected to CN201-9 and CN201-10. One end of the thermistor TH is grounded, and a constant DC voltage (5V) is applied to the other end via a resistor R222. The voltage across the thermistor TH is applied to the analog input port AN2 of the microcomputer 100. Therefore, by monitoring the level of the input port AN2, the microcomputer 100
Can know the heater temperature.

The output signal of the thermistor TH and the applied voltage signal of the exposure lamp are also applied to the comparators 130 and 131, respectively. The output terminal of the comparator 130 is normally at the high level H, but goes low when the output signal of the thermistor TH exceeds the overheat level (208 ° C. in this example). The output terminal of the comparator 130 is connected to the reset terminal of the timer circuit 140. When the timer circuit 140 is reset, the safety relay RA501 shown in FIG. 2c is turned off, and the AC power source (AC100) applied to the exposure lamp LP and the fixing heater HT.
Shut off V).

The output terminal of the comparator 131 is normally at low level L, but becomes high level H when the exposure lamp LP is turned on. The output signal is applied to the input terminal of the timer circuit 140, and if the high level H period is longer than a predetermined period, the timer circuit 1
40 turns off the safety relay RA501 to cut off the AC power supply. That is, when the lighting time of the exposure lamp exceeds a predetermined time (10 seconds in this embodiment), the power is automatically cut off.

Variable resistor VR202 provided in the level conversion circuit 150
Is for setting the target value of the lamp voltage. The output terminal of the variable resistor VR202 is the microcomputer 100.
Connected to the analog input port ANO. In this embodiment, the output voltage of the variable resistor VR202 is 0-3.
By adjusting in the range of 7V, the applied voltage of the exposure lamp LP can be adjusted in the range of 50V to 85V (effective value).

Please refer to FIG. 2b. The decoder 170 decodes the 3-bit octal code data output from the microcomputer 100 to the output ports PF0 to PF2 and outputs the decoded 8-bit code data to eight signal lines. This signal line is the driver 180
And 190, the column lines of the key switch matrix 240 and the light emitting diode matrix 250 are commonly connected.

The microcomputer 100 outputs the output ports PF0, P0.
For F1 and PF2, "000"-"001"-"01"
0 "-" 011 "-...-" 111 "-" 000 "
.. are sequentially and repeatedly output, each column line of the key switch matrix 240 and the light emitting diode matrix is sequentially and repeatedly selected. The update is performed about every 2 msec in this embodiment.

If the row line level of the key switch matrix 240 is read in synchronization with the update, the key switch matrix 24
The state of any switch in 0 can be read. Further, by outputting predetermined data to the row line of the light emitting diode matrix 250 in synchronization with the update, any light emitting diode included in the light emitting diode matrix 250 can be turned on and off.

In this embodiment, 0 is set in the key switch matrix 240.
Numeric keypad, clear key, recall key, preheat key, mode clear key, each key corresponding to each numeric value of ~ 9
Interrupt key, print key, AE key, light key, dark key, cassette key, original key, same size key, reduction key, enlargement key, zoom up key, zoom down key, auto zoom key, size uniform key, APS key , ADF / SADF
Key switch group consisting of key, stack / sort key, double-sided key, continuous page key, front right key, front left key, back right key and back left key, and 8-bit DIP (dual inline package) switch . The key switch group is arranged on an operation panel (not shown) of the copying machine. Eight switches of the DIP switch are used to adjust the copier,
It is used for tests.

The output port PF3 of the microcomputer 100 is connected to the buzzer BZ via the driver 170.

A schematic configuration of the microcomputer 100 is shown in FIG. 2d. Referring to FIG. 2d, the microcomputer includes an oscillation circuit OSC, a serial I / O circuit B1, an interrupt control circuit B2, a timer circuit B3, a timer / event counter circuit B4, an A / D conversion circuit B5, and a register B.
6, a program memory B7, a RAM memory B8, and various control blocks necessary for other processing.

Next, regarding the components used in the embodiment, the configuration and function of each block of the microcomputer 100 and the operation in the embodiment will be described.

Timer circuit B3: Two sets of 8-bit interval timers (TIMERO, TIMER
1) is equipped. Each timer is composed of an 8-bit up counter, an 8-bit digital comparator, and an 8-bit timer register (TM0, TM1). When an interval time is set in the timer register TM0 or TM1 and a predetermined setting is made in the timer mode register (TMM), the up counter starts counting. When the contents of the timer register TM0 or TM1 match the contents of the up counter, the up counter is cleared and an internal interrupt (timer interrupt) is generated. This sets the timer interrupt flag (FT0 or FT1). By setting the mask register (MKL),
The timer interrupt can be masked. Interrupts are prohibited by setting the registers MKT0 and MKT1 of the mask register, and interrupts are permitted by resetting.

In this embodiment, the timer is used for the frequency discrimination of the power supply, the phase angle timer of the exposure lamp applied voltage, and the like. To determine the frequency of the power supply, set 238 in the register TM0,
When the zero cross point is detected, the mode register TM
The input clock pulse (38.4 μsec) specified by M is given to the up counter. Then, at the next zero cross point, the interrupt flag FT0 is checked, and if it is set, it is determined to be 50 Hz, otherwise 60 Hz. That is, the interval of the zero cross points of the power supply waveform is 10 msec for 50 Hz and 8.3 msec for 60 Hz, while the timer counting time is 9.14 msec (38.4 μsec × 238), so the flag FT0 is set. , 50 Hz. In this case, interrupts are disabled.

In the case of the phase angle timer, the input clock pulse of the up counter of the timer TIMER0 is set to 1.2 μsec and 25 is set to the register TM0. In addition, the timer TIMER1 receives the input clock pulse of the up counter, a match signal between the up counter of the timer TIMER0 and the register TM0, that is, 3
Set to a pulse of 0 μsec. The register TM1 has a value (PHAN) obtained by a phase angle timer update routine described later.
GL) is set. Then, at the zero cross point, the up counters of the timers TIMER0 and TIMER1 start counting up from 0 (hereinafter referred to as timer start), and
When the up counter of TIMER1 and the contents of the register TM1 match and the timer interrupt flag FT1 is set, the microcomputer 100 jumps to a timer interrupt routine which will be described later and turns on the lamp drive signal.

Timer / event counter circuit B4: 16-bit up counter (ECNT), 16-bit register (ECPT) that holds the contents of ECNT, 16-bit register (ETM0, ETM) that sets the count value
1), a digital comparator for comparing the contents of ECNT and ETM0 or ETM1. When the digital comparator detects a match, the match signal (CP0, CP
1) is output.

In this embodiment, it is used as a display interval timer of the operation unit. That is, the key switch matrix 24
It is used to generate the update timing of the signal that controls the 0 and the column line of the light emitting diode matrix 250.

Specifically, the display interval time ISRT2M (1665: 2 msec) is set in the register ETM1, the interval timer mode is selected, and the up counter ECNT is set.
Start counting. Counter input clock is 1.2 μsec
Set to. When the counter ECNT and the register ETM1 match, ECNT is cleared, an internal interrupt occurs, and the flag FE1 is set. Counter ECNT
Starts counting from 0 again.

If MKE1 of the interrupt mask register (MKL) is reset, the process jumps to the timer / event counter interrupt routine and performs display processing. Interrupt plug FE
1 is reset when an interrupt is accepted.

Serial I / O circuit B1: This circuit is a serial data input R _x D, the serial data output T _x D, the three terminals of the serial clock input SCK, 8 bit serial registers, the buffer registers and reception control circuit It consists of a transmitter and receiver provided, and a mode register that specifies the operation mode.

The transmission buffer register generates an interrupt request INTST when the internal data becomes empty (empty), and the reception buffer register generates an interrupt request INTSR when the internal data is fully stored. The serial mode register includes two 8-bit registers, a serial mode high register SMH and a serial mode low register SM.
It is L.

In the embodiment, the asynchronous mode is used. The serial data consists of a total of 11 bits including a start bit, 8-bit data, a parity bit and a stop bit.
The transfer rate is 422 μsec. The serial mode registers SML and SMH have an asynchronous mode,
Receive enable, transmit enable and clock 2.4 μsec
The state of is set. Interrupt mask register MKH
After resetting MKSR, enable receive interrupt.

When serial data is sent from the sequence control unit 20 shown in FIG. 1a, the data is received at the reception terminal RXD.
It is received by (PC1) and transferred to the reception buffer register RXB. When the buffer register RXB becomes full buffer, an interrupt request is generated and the interrupt flag FSR is set. Thereby, the microcomputer 10
0 jumps to the receive interrupt routine. In that routine, the received data is stored in a predetermined memory, and the data to be transmitted is written in the transmission buffer register TXB. When the writing is completed, the serial I / O circuit B1 automatically transfers the contents of the transmission buffer register RXB to the serial register, and sequentially outputs each bit as serial data from the data transmission terminal TXD (PC0).

A / D conversion circuit B5: This circuit is composed of an input circuit, a series string, a voltage comparator, successive approximation logic, and registers CR0 to CR3. The eight analog inputs are multiplexed and selected by the A / D channel mode register ANM. The A / D converted data is stored in the registers CR0 to CR3. The operation mode of the A / D conversion circuit B5 is the A / D channel mode register A
Specified by NM.

In the embodiment, as shown in FIG. 2a, the ramp voltage target value setting signal (the output of VR202) is added to the analog input terminal channel 0 (AN0) of 8 channels, and the ramp voltage feedback signal is added to the channel 1 (AN1). And a fixing heater temperature detection signal is applied to channel 2 (AN2). Other channels are unused.

The converted digital data is stored in the registers CR0-CR1.
-Stored sequentially in CR2-CR3. When the four registers CR0 to CR3 have the same data, an internal interrupt occurs and the interrupt flag (FAD) is set. afterwards,
The A / D conversion circuit B5 continues the A / D conversion regardless of whether or not the interrupt is accepted. When an interrupt occurs, the microcomputer 100 jumps to the interrupt routine if the MKAD of the interrupt mask register (MKH) is reset. When the interrupt is accepted, the flag FAD is reset.

Interrupt control circuit B2: In this embodiment, the cause of the interrupt includes the timer interrupt, the timer / event counter interrupt, the serial reception interrupt and the A / D conversion interrupt, and the external interrupt. The external interrupt is generated by setting the interrupt request flag F1 by detecting the rising edge of the zero-cross signal applied to the interrupt request input terminal INT1 of the microcomputer 100. Microcomputer 100
Jumps to the interrupt routine if MK1 of the interrupt mask register MKL is set. Flag F1
Is automatically reset when an interrupt is accepted or its flag is checked.

The order of priority of interrupts is timer interrupt-external interrupt-timer / event counter interrupt-A / D conversion interrupt-serial reception interrupt (high-low).

Ports (PORT A-PORT F): All ports are input / output ports with output latch. Input / output of each port is specified by each mode register M
It is performed by setting A, MB, MC, MD and MF.

Next, the operation of the embodiment will be described. Before the detailed description is given, the general operation will be described with reference to the timing chart of FIG. 3 and the general flow chart of FIG.

The loop of steps S5-S6-S5 -... In FIG. 4 corresponds to the cycle 0 (CYCLE0) in FIG. 3, and similarly, steps S7-S8-S9-S11-S3-S4 -...・
.. and steps S7-S8-S9-S11-S12-
S3-S4 -... Corresponds to cycle 1 (CYCLE1).
In cycle 0, sampling of lamp voltage, display control, key switch scanning (reading), and communication control with the sequence control unit are performed. Step S7-S
In cycle 1 through 8-S9-S11-S3-S4,
The target value of the lamp voltage and the fixing heater temperature are sampled, and the lamp voltage phase angle timer is updated from the lamp voltage sampled in cycle 0 and the target value. Further, similarly to the cycle 0, the scanning control and display control of the key switch are performed. Steps S7-S8-S9-S11-S12
-Cycle 1 through S3-S4 (denoted as cycle 1b)
Then, in addition to the above control, the operation amount (duty) of the fixing heater is further obtained. Cycle 1b is executed at 1 second intervals. That is, the lamp voltage control is cycle 0-cycle 1
Two cycles (including cycle 1b) (one wave of the commercial AC power supply waveform) is the control cycle, and the fixing heater temperature control is one.
The second becomes the control cycle.

The detailed operation will be described below. In addition, symbols in parentheses in the following description are defined as follows.

(): Register, counter, flag []: Input / output signal <>: Jump destination address The symbols without parentheses indicate subroutines, immediate data, part names or port names.

When the power is turned on in step S1, the initialization in step S2 is performed. Details of the initial setting are shown in Figs. 5a and 5b.
Shown in Figures, 5c and 5d. In the initial setting, first, the stack pointer is set to FFFFH and the register V
Set FFH to (this is the FFO in the memory space)
It means setting a working area in OH-FFFFH). Next, the port is initialized. First, set port A (PA0-PA7) as the input port, and port B
(PB0-PB7) is set to the output port and all its bits are set to high level H. Port C (PC0-PC
7) sets PC0, PC1 and PC3 as control ports, PC2 as input ports, PC4, P4
C5, PC6 and PC7 are set as output ports, and a high level H (off level) is set at the output ports. Port D (PD0-PD7) and Port F (PF0-PF)
In 7), the output port is set, and all bits are set to the high level H.

From the ports PC4, PC5, and PC6, a lamp drive signal [LMPDVRV], a fixing heater drive signal [FUHDRV], and a main motor drive signal [M, respectively.
OTDRV] is output. PF4 to PF7 of the ports B, D and F are light emitting diode lighting data output ports of the operation unit, PF0 to PF2 of the port F are key scan signal output ports, and PF3 is a buzzer control signal output port.

Then, all the memory in the working area (address FF
00H-FFFFH). Further, the transmission synchronization character FFH is set in the transmission synchronization register (TXSYNC), and the off data is set in all the cassette data registers.

Then, the fixing heater temperature STBNDH (temperature data slightly higher than the target value) at the pseudo previous copying start is set in the fixing heater temperature register at the previous copying start (RREFUT), and the heater control counter (HETCNT) is set.
And the quaternary counter (QADCNT) is set to 1.
Next, set the timer / event counter (ETM1) to 2 msec.
Set to the interval mode of and start the counter. Furthermore, the asynchronous mode is set in the serial I / O circuit, the transfer clock cycle is set to 2.4 msec, and transmission / reception is permitted. Then, the interrupt mask for reception is released and the interrupt is permitted.

Next, in order to prohibit the display for 0.5 seconds, 255 and 51 are set in the timer registers TM0 and TM1, respectively, the interrupt request flags (FT0) and (FT1) are reset, and the timer mode is set. Start the timer.

The reception data decoding subroutine CTLISR is repeatedly executed until the flag (FT0) is set after the timer is started, that is, until 0.5 seconds elapses. After 0.5 seconds, timer TIMER0 and TI
Stop MER1 and cancel the interrupt mask of the timer / event counter. After that, the timer / event counter interrupt occurs every 2 msec.

Next, the falling interrupt flag (F2) of the zero-cross signal is reset.

When the above is completed, next, <STRTISR> (5c
(Figure) to jump. In the process starting from <STRTISR>, the received data decode subroutine CTLI
After executing SR, the flag (F2) is checked, and if it is "0", that is, zero cross is not detected, <STRTISR>
Return to. If the flag (F2) is "1", that is, if the zero crossing has arrived, the timer register TM waits for 0.5 second.
Set 255 and 51 to 0 and TM1, respectively,
The interrupt flag (FT0) of the timer TIMER0 is reset ((FT1) has been reset by the previous check), and the timers TIMER0 and TIMER1 are started. Then, it waits for 0.5 seconds until the flag (FT1) is set, that is, after the zero cross is detected, and during that time, the execution of the reception data decoding subroutine CTLISR is repeated. This is a process for preventing malfunction due to chattering when the power is turned on. After 0.5 seconds, timers TIMER0 and TIMER1 are stopped and <CHKFR
Jump to Q>.

In the process starting from <CHKFRQ>, the frequency of the commercial power supply is determined. First, the flag (F2) is reset, and the zero-cross missing counter (NOZCNT) is reset. This counter is incremented every 2 msec. Next, it waits until the flag (F2) is set. However, the counter (NOZCNT) is greater than 6, that is, 14
If the flag (F2) remains reset even after a lapse of msec, the process returns to <STRTISR>. When the flag (F2) is set, that is, the zero-cross timing comes, the frequency discrimination data 228 is set in the timer register TM0, the counter (NOZCNT) is reset, the flag (FT0) is reset, and the timer TIMER0 is started. . After that, if the flag (F2) is set,
Stop timer TIMER0 and check flag (FT0). If the flag (FT0) is "1", it is determined to be 50 Hz. However, if the counter (NOZCNT) is larger than 6, that is, if the flag (F2) is not set even after 14 msec or more, <ST
Return to RTISR>.

When the frequency discrimination is completed, the process proceeds to the next <INTMOD>, 25 is set in the timer register TM0, and the timer T
Specify the input clock of IMER0 to 1.2 μsec. As a result, the input clock cycle of the ramp voltage phase angle timer TIMER1 is set to 30 μsec.

Finally, the zero-cross rising interrupt flag (F1) is reset, and the zero-cross rising interrupt mask and the phase angle timer interrupt mask (MK1 and MKT1) are released (reset).

The above is the initialization operation shown as step S2 in FIG.

Next, step S3 and subsequent steps will be described. First, the zero cross counter (ZCPCNT) is checked, and if it is an odd number, the process proceeds to <CYCLE0>. If the counter (ZCPCNT) is an even number, the process proceeds to step S4, and the zero cross missing flag (NOZCP) is checked. Flag (NOZCP)
If is “0”, it returns to <START> and the flag (NOZ
If CP) is "1", that is, zero crossing is missing, <CHKISR
Jump to ＞. Where counter (ZCPCNT)
Is incremented at every zero-cross (the zero-cross interrupt is done routinely), the flag (NOZC
P) is a timer /
Event counter interrupt routine Set.

When you enter <CYCLE1>, the counter (ZC
Check (PCNT) and if it is even, <CYCLE
Go to 1>. If the counter (ZCPCNT) is odd, check the flag (NOZCP), and if it is "1"<
Jump to CHKISR> and if it is "0", then <CYCLE
Return to 0> and repeat the above operation. Normally, that is, if the zero-cross signal is normal, this operation is performed for 10 or 8.3 msec (50
/ 60Hz). During this period, a timer interrupt is generated by the phase angle timer (TM1) set and started by the zero-cross interrupt routine ZCINT. Thereby, the timer interrupt routine TMINT is executed, the exposure lamp is turned on, the A / D conversion circuit B5 is set to the sampling mode (select mode) of the lamp voltage from the port AN1, and the A / D conversion is started. To do. As a result, thereafter, an A / D conversion interrupt is generated every 460 μsec. When this interrupt occurs, the A / D conversion interrupt routine ADINT is executed. Thereby, the converted data is stored in the predetermined memory. The A / D conversion interrupt is performed until the rising edge of the zero cross is detected.

Also in <CYCLE1>, the timer interrupt is generated by the phase angle timer (TM1) set and started by ZCINT. When a timer interrupt occurs, the lamp is turned on by executing TMINT, and the A / D conversion circuit B5 is set to a mode (scan mode) for sampling the lamp voltage target value of the port AN0 and the fixing heater temperature data of the port AN2. , A / D conversion is started. This causes an A / D conversion interrupt. When an A / D conversion interrupt occurs, the conversion data is stored in a predetermined memory by executing ADINT, and the A / D conversion interrupt is masked.

In <CYCLE1>, the subroutine CALVSET is executed, and a new lamp voltage target value is set based on the previously sampled lamp voltage target value. Then, the subroutines SUMSQR, CALRMS, and PWM are sequentially executed, and the square integrated value calculation, execution value calculation, and phase angle timer value calculation of the instantaneous data of the lamp voltage sampled by <CYCLE0> are sequentially executed.

Next, the subroutine CHKPRT is executed to detect the state change of the print key of the operation unit. Then, the dimension conversion of the lamp voltage and the fixing heater temperature is performed by executing the subroutine CONDM. Next <CHKI
Proceed to SR> and execute the subroutine CTLISR to decode the received data from the sequence control unit 20. When CTLISR ends, flag (NOZCP)
Check, and if it is "0", proceed to <CHKCHT>. If the flag (NOZCP) is "1", subroutine C
Zero crossing error processing is performed by executing TLOFF,
Return to <CHKISR>.

In <CHKHCT>, the heater control counter (HETC
NT) and if it is not "0"<STA
Return to RT>. If the counter (HETCNT) is "0", the process proceeds to step S12. In addition, count (HETC
NT) is decremented once every four times in ZCINT, and its content becomes 0 every second. In step S12, the subroutine SETEM
By executing P, the target temperature of the fixing heater is set, and (H
Set ETCNT to 25 or 30 (50Hz / 60Hz).

Next, the heater control cycle flag (HTSPTM) is checked, and if it is "0", that is, the cycle is 1 second, <OPEFP
Jump to ID>. If the flag (HTSPTM) is "1", that is, the control period is 5 seconds, the quinary counter (PNT)
CNT) is decremented, and if the result is negative, 4 is set in the counter (PNTCNT), and <OPEFPID>
Proceed to. If the counter (PNTCNT) is not negative, <
Jump to CHKFIX>. Flag (HTSPT
The setting and resetting of M) will be described in detail later.

In <OPEFPID>, the operation amount (the number of on-cycles) for energizing the fixing heater is executed by executing the subroutine FUPID.
To update. Then, the flow proceeds to <CHKFIX>, the fixing heater duty fixed flag (FIXFUC) is checked, and if it is "1", that is, fixed, the subroutine RESF
By executing UC, the fixing heater energizing operation amount is set to 0 or 100.
Fixed to%. If the flag (FIXFUC) is "0",
The above operation is skipped.

Next, the fixing heater temperature is checked by executing the subroutine CHKTMP. This check includes pre-reload, reload, overheat and thermistor disconnection checks.

When the above is completed, the process returns to <START> and the above operation is repeated.

Next, each interrupt service routine and subroutine will be described in detail.

(1) ZCINT ... Fig. 6a This interrupt service routine is executed by the zero cross signal [ZC
P] is changed from the low level L to the high level H. When this routine is entered, the zero-cross signal [ZCP] is checked first, and if it is at low level L, the interrupt processing thereafter is skipped and the processing immediately exits. This is performed to prevent malfunction due to noise in the signal [ZCP].

If the signal [ZCP] is at high level H, it is regarded as a normal interrupt and the following processing is performed. First, the zero-cross interrupt and the A / D conversion interrupt are masked, and the phase angle timer is stopped. Next, the lamp lighting flag (REGU) is checked, and if it is "1", that is, the lamp is lighting, <REGACT>
Jump to. If the flag (REGU) is “0”, that is, the lamp is off, if the second lamp is on, jump to <REGACT>. If the flag (LMPON) is “0”, that is, the lamp is off, check the second lamp lighting flag (LMPON). , If it is “1”, that is, the lamp is on, <REGA
If the flag (LMPON) is "0", that is, the lamp is off, the process proceeds to <REGOFF>. here,
(REGU) is data received from the sequence control unit 20. The microcomputer 100 of the operation control unit 30 detects that the print key has been pressed in advance, and sends this information to the sequence control unit 20. In response to this, the sequence control unit 20 causes the operation control unit 30 to receive the information. Data to be sent back to.

The flag (REGU) is "1" in the copy mode, and is set to "0" in the standby mode. The flag (LMPON) is used when the microcomputer 100 independently lights the exposure lamp. Specifically, when bits 7 and 8 of the DIP switch included in the key switch matrix 240 are set to ON, the lamp test mode is set. In that mode, when the print key is pressed, the flag (LMPON) is set and printing is performed again. Pressing the key resets the flag (LMPON). In this case, the sequence control unit 20 is sent data indicating print key off. When bit 8 of the DIP switch is turned off, the above mode is released and the normal mode is restored.

In <REGOFF>, the fixing heater duty fixed flag (FUCFIX) is reset, and the lamp off flag (LMPOFF) and the soft start flag (SOF) are reset.
T) is set. The phase angle timer value OFFTIM when the lamp is off is set to the phase angle timer register (PHANG).
Store in L) and proceed to <SETHA>.

In <REGACT>, the flag (FIXFUC) is checked, and if it is “0”, (FIXFUC) is set to “1”, and the fixing heater control duty is fixed to 0 or 100% by executing the subroutine FUCFIX.
Then, the flag (LMPOFF) is reset, the initial phase angle timer value IPA50 (at 50 Hz) or IPA60 (at 60 Hz) is stored in the phase angle timer register (PHANGL), and the process proceeds to <SETHA>. Flag (F
If IXFUC) is "1", the above operation is skipped.
In <SETPHA>, the content of the register (PHANGL) is set in TM1 and the phase angle timer is started. That is, as described in the initial setting routine, the timer TIMERO outputs a signal every 30 μsec, the timer TIMERI sets the output signal to the count clock, and the timer TIMER1 starts.

Next, the lamp drive signal [LMPDRV], the fixing heater drive signal [FUHDRV], and the main mode drive signal [MOTDRV] are turned off. Next, if the fixing heater on counter (FUCNT) is not 0 due to the execution of the subroutine HTCNTL, the signal [FUHDR
V] is turned on. When the processing of the subroutine HTCNTL is completed, if the main motor flag (MOTOR) is "1", the signal [MOTDRV] is turned on. The flag (MOTOR) is received data from the sequence control unit 20.

Finally, the zero-cross counter (ZCPCNT) is incremented, and the zero-cross missing flag (NOZCP),
Reset the zero-cross missing counter (NOZCNT) and the zero-cross interrupt flag (INTZCFG).

(2) TMINT ... FIG. 6d This interrupt service routine is executed in response to the interrupt request of the phase angle timer that controls the exposure lamp. That is, in the zero-cross interrupt routine ZCINT, when the phase angle timer data (PHANGL) is set in the timer TM1, the predetermined data is set in the timer mode register (TMM) and the timers TIMER0 and TIMER1 are started, the timer TIMER1 and TM1 are updated. When the count value of the counter matches, a timer interrupt request is generated, and in response thereto, the interrupt service routine TMINT is entered.

When the routine is entered, the lamp off flag (LMPOFF) is checked first, and if it is "0", that is, the lamp lighting mode, the signal [LMPDRV] is turned on. If the flag (LMPOFF) is "1", that is, the lamp extinction mode, the above operation is skipped. Next, 191 μse
After waiting c hours, stop the phase angle timer (TIMER0 / 1). In addition, the counter (ZCPCNT) is even (CYCL
If E1), the A / D conversion circuit B5 is set to a mode (scan mode) for sampling the lamp voltage setting value and the fixing heater temperature, and if the counter (ZCPCNT) is an odd number, it is set to a mode (select mode) for sampling the lamp voltage. Set. And start A / D conversion,
Clear the A / D interrupt request flag (FAD), and
The interrupt mask is released, and the lamp voltage sampling valid flag (LMPADC) is set.

(3) ADINT ... FIG. 6e This routine is executed in response to all the data in the registers CR0-CR3 being stored and the interrupt request flag (FAD) being set. When this routine is entered, the timer / event counter interrupt (display processing) and the reception interrupt are masked first. Next, A /
Check D conversion mode register (ANM) and if it is scan mode, jump to <SMPSVFT>. If the register (ANM) is in select mode, check the flag (LMPADC), and if it is "1", A /
Of the D conversion data (lamp voltage sampling data),
The content of the register (CR3) is stored in a predetermined memory. When the number of A / D conversions is 21 or more, the A / D conversion interrupt is masked. If the flag (LMPADC) is "0", the above operation is skipped.

Next, the state of the flag (LMPADC) is inverted and <CH
Go to KIZC>. As a result, the A / D converted data is stored in the memory every other time.

In <SMPSVFT>, of the A / D conversion data, the contents of the register (CR0) and the first buffer register (SMPSV of the ramp voltage target value sampling data register).
1) and if they are equal, the A / D converted data is stored in the second buffer register (SMPSV2).
Also, regardless of whether or not they are equal (SMPSV
It is also stored in 1). Next, the contents of the register (CR1) are inverted and stored in the fixing heater temperature register (FUTEMP). Then, the A / D conversion interrupt is masked and <C
Go to HKIZC>. That is, when the A / D conversion circuit B5 is in the scan mode, that is, in cycle 1, the A / D conversion interrupt occurs only once.

In <CHKIZC>, the zero-cross interrupt flag (IN
TZCFG) is checked, and if it is “0”, the flag (INTZCFG) is set to “1” to reset the zero-cross interrupt request flag (F1), and the zero-cross interrupt mask is released. If the flag (INTZCFG) is "1", the above operation is skipped. That is, the A / D conversion interrupt routine is executed when it is called the first time in each cycle. Finally, the mask of the display interrupt and the serial data reception interrupt is released.

(4) DSPLY ... FIG. 6h This interrupt service routine is executed when an interrupt is generated from the timer / event counter. In this routine, the display of the operation unit is controlled. In addition, this routine is
As already described, it is executed every 2 msec.

When you enter this routine, first, subroutine F
Perform LASH. In the subroutine FLASH,
Generates a blinking display and a buzzer-on sync signal. Next, the counter (NOZCNT) is incremented, and when the result is greater than 50, that is, the zero-cross signal is 1
If it does not appear for more than 00msec, the counter (NOZCN
T) is reset and the flag (NOZCP) is set.

If the counter (NOZCNT) is 50 or less, the above operation is skipped.

Next, the data of the port A is read and stored in a predetermined memory, and all bits of the ports B and D and PF4 to PF7 of the port F are turned off so that all the light emitting diodes of the display section are turned off. Set high level H.
In this example, all the light emitting diodes light up at a low level L. Then, the state data of the key switch (port A data) stored previously is compared with the contents of the first key buffer register, and if they are equal, it is stored in the second key buffer register. Also store in key buffer register. As a result, the reading is performed twice. Next, the contents of the scan counter (SCNCNT) are updated, and the scan signal is output to PF0-PF2 of ports P and F according to the result.

Next, data indicating turning on / off of each light emitting diode is provided to all bits of ports B and D and PF4-P of port F.
Output to F7. In addition, AC test mode, that is, DIP
Bit 8 of the switch turns on and the flag (ACTEST)
Is “1”, the 3-digit 7-segment numeric display (included in the light-emitting diode matrix 250) of the display section,
The data required for adjustment (specifically, lamp voltage, fixing heater temperature, etc.) are displayed.

(5) RCVTR3 ... FIG. 6f, FIG. 6g This interrupt service routine receives the serial data sent by the sequence control unit 20 and completes storing one byte of data in the receive buffer register (RXB). It is executed in response to a receive interrupt that occurs. In this routine, when the data of the receive buffer (RXB) is stored in a predetermined memory, 1-byte data to be transmitted immediately is set in the transmit buffer register (TXB) and sent to the sequence control unit 20. This reception interrupt occurs about every 4 msec (the sequence control unit 20 generates this interval time). One interrupt process receives and transmits one byte of data.

In the embodiment, the data to be received is 14 (14 bytes) in total, and the data to be transmitted is 10 (10 bytes) in total. Data is identified by adding a predetermined synchronization code data FFH to the beginning of the data. That is, in the case of reception, when the reception data FFH is received, the reception counter (RXCNT) is reset to synchronize the reception counter, and when other data is received, the reception counter (RXCNT) is incremented and the reception counter (RCNT) is increased.
XCNT) to the memory address corresponding to the contents of 14
The received data is stored in any of the reception buffer memories. With this, predetermined reception data is sequentially stored in each of the 14 reception buffer memories whose addresses are predetermined.

Lamp test mode (DIP switch pit 7
If both 8 and 8 are off), the data indicating the state of the print key is always set to the print key off state (state where no key is pressed).

In the case of transmission, when the transmission counter (TXCNT) is 0, the synchronization code data FFH is transmitted, and if it is not 0, the contents (1 byte) of the buffer memory of the memory address corresponding to the value is transmitted and the transmission counter is transmitted. Is incremented. When the transmission counter (TXCNT) becomes greater than 10, it is considered that the transmission of one set of transmission data has ended, and the transmission counter (TXCNT) is cleared to 0. This allows
One synchronization code and ten pieces of transmission data are sequentially transmitted each time an interrupt occurs.

(6) CTLISR ... FIG. 5e In this subroutine, the coded data received from the sequence control unit 20 is decoded and the result is converted into a predetermined data array. Specifically, in order to perform display control of the light emitting diode matrix 250, each port P
Data to be set in B0-PB7, PD0-PD7 and PF4-PF7 and rearrangement.

(7) CALVSET ... FIG. 7a In this subroutine, the target value of the exposure lamp applied voltage is set.

Specifically, the following calculation is performed using the target value setting data (SMPSV2) obtained by sampling the output level of the variable resistor VR202 and A / D converting it.

(SETRMS) = (SMPSV2) × (61/183) +75 ... (1) (SETRMS) is the target value register. Next, notch data (BDENS) (data sent from the sequence control unit 20) indicating the values of the seven density steps specified by the density specifying key switch (included in the key switch matrix 240) on the operation panel of the copying machine. ) Is used to modify the contents of the target value register (SETRMS) as follows.

When (BDENS) = 0 or 1: (SETRMS) = (SETRMS) -3 x (BDENS) ... (2) When (BDENS) = 2 to 7: (SETRMS) = (SETRMS) + 5 x {(BDENS ) -2} ... (3) As a result of the above processing, the value of the register (SETRMS) is the target value upper limit value.
If it exceeds MAXRMS (136), set the upper limit to (SETRMS)
Set to.

Next, decrement the phase angle timer (DIFF) during soft start.
Calculate from the following formula based on (SETRMS).

At 50 Hz: (DIFF) = {(SETRMS) −72} × (1/3) +6 (4) At 60 Hz: (DIFF) = {(SETRMS) −72} × (13/64) +4 (5) However, (DIFF) is the lamp off flag (LMPOF
Calculated only when F) is "1" (lamp off mode).

(8) SUMSQR ... FIG. 7c In this subroutine, the square integrated value of the instantaneous value data of the exposure lamp applied voltage sampled in cycle 0 is obtained.

First, the actually sampled n pieces of data V ₁ , V ₂ , ...
From ‥ V data _{V n-1} of the previous last data V _n 1 one thereof _n, obtains the difference _{ΔV n (ΔV n = V n} -1 -V n). This value shows a voltage change at one sampling interval in the vicinity of zero cross. If the result is positive, the sampling count (SPVCNT) (n) is incremented to V
Store (V _n −ΔV _n ) in _{n + 1} . However, (V _n −Δ
If V _n ) is negative, store 0 instead. If V _{n + 1} is positive, (SPVCNT) is incremented and (V _n-1 −ΔV _n ) is stored in V _{n + 2} as described above. However, (V _n −ΔV
_{If n} ) is negative, then 0 is stored in V _{n + 2} . If positive, then
Is incremented (SPVCNT), to _{V n + 3 (V n +} 2 -ΔV n)
To store. However, if (V _{n + 2} −ΔV _n ) is negative, 0 is stored.

That is, in the above process, the slope of the voltage change at the end of sampling ΔV _n is obtained using the result of actual sampling, the theoretical instantaneous voltage value at the virtual sampling timing after the end of sampling is calculated, and the theoretical value Add sampling data until a zero cross is detected. In this embodiment, up to 3 data are added.

By performing this processing, it is possible to eliminate a sampling error based on the fact that the sampling ends before the actual zero-cross point due to the phase shift of the zero-cross detection circuit.

Then, m-number (m = n, n + 1 , n + 2 or n + 3) the sampling data V _1, V ₂ of the ‥‥ V _m is calculated each square,
The result is registered in the register (SUMSQH), (SUMSQ
M) and (SUMSQL). In addition, each average value of the neighbors of each sampling data V ₁ , V ₂ , ... V _m ,
That is, (V ₀ + V ₁ ) / 2, (V ₁ + V ₂ ) / 2, ...
(V _m-1 + V _m ) / 2 is obtained, each of these values is squared, and the result is registered in the registers (SUMSQH) and (SUMSQM).
And (SUMSQL). Now register (S
UMSQH), (SUMSQM) and (SUMSQL)
The calculated value of the squared value of each of the 2 · m instantaneous value data is stored in. Note that V ₀ is always set to 0.

(9) CALRMS ... FIG. 7d In this subroutine, the effective value of the lamp voltage is obtained.
Before executing this subroutine, the subroutine S
Registers (SUMSQH), (S
Since the square integrated value of the sampling data is stored in (UMSQM) and (SUMSQL), the effective value is obtained using it. That is, the register (SUMSQH),
The contents of (SUMSQM) and (SUMSQL) are set to the sampling frequency SPTIM50 or S depending on the power supply frequency.
Divide by PTIM60, find the average value, and calculate the square root of the result. The result is stored in the effective value register (RMS).

(10) ROOT ... FIG. 7e This subroutine is called from the subroutine CALRMS. It is a subroutine for calculating the square root. The calculation algorithm is publicly known.

(11) PWM ... FIG. 7i In this subroutine, the set value (PHANGL) of the phase angle timer that controls the voltage applied to the exposure lamp is updated.

First, check the soft start flag (SOFT), and if it is "0" (end of soft start), <RNW
Jump to PHA>. Flag (SOFT) is "1"
If (during soft start), the target value of the lamp voltage (SE
TRMS) and the effective value of the lamp applied voltage detected (RM
S) and the difference (A), the result is negative or (DIF
If it is smaller than F), the flag (SOFT) is reset, the process proceeds to <PNWPHA>, the calculation of the following formula (6) is performed, and the set value (PHANGL) of the phase angle timer is updated.

(PHANGL) = (PHANGL) − {(SETRMS) − (RMS)} (6) If (A) is positive and larger than (DIFF), the value from (PHANGL) to (DIFF) Reduce.

If the value of the register (PHANGL) updated as described above is smaller than the lower limit value MINT, the value of the register (PHAGL)
NGL) to the lower limit value MINT and the upper limit value MAXT
If it is larger than 50 or MAXT60 (determined according to the frequency), the upper limit value is set in the register (PHANGL).

(12) HTCNTL ... FIG. 6c In this subroutine, the drive signal [FUHDRV] of the fixing heater is turned on according to the value of the on-cycle counter (FUCNT) of the fixing heater. First, check the thermistor disconnection flag (THBRK), which is "1".
That is, if the thermistor is disconnected, jump to <DECQAD>. If the flag (THBRK) is "0", the counter (F
Check UCNT) and if it is not 0 [FUH
DRV] is turned on.

Next, the quaternary counter (QADCNT) is decremented, and if the result is negative, the counter is set to 3, and the fixing heater on-cycle counter (FUCNT) and the fixing heater control cycle counter (HETCNT) are decremented. However, each is not 0. If the counter (QADCNT) is positive or 0, the above operation is skipped. In other words, it decrements every four cycles.

Next, the preheat flag (PRHT) (data received from the sequence control unit 20) is checked, and it is "1".
That is, in the preheat mode, the preheat edge flag (TMPDN) is set. If the flag (PRHT) is "0", the flag (TMPDN) is checked, and if it is "1" (preheat release), the flag (TMPDN) and the fixing heater control cycle determination flag (HTSPTM) are reset, and the counter (HETCNT). To clear. Flag (TMPDN)
Is 0, the above operation is skipped. The fixing heater control cycle is 1 second when the flag (HTSPTM) is "0" and 5 seconds when it is "1".

(13) FUCFIX ... FIG. 6b In this subroutine, the duty (the number of on-cycles) of the fixing heater is fixed to 0 or 100%. This routine is executed only once when the lamp is turned on.

First, the fixing heater temperature (FUTEMP) and the reference value STB
Compare NDL (a value 3-5 ° C lower than the target value), and
If TEMP) ≦ STBNDL, jump to <FMAXST>.

If (FUTEMP)> STBNDL, then (FUTEM
P) and the reference value STBNDH (a value 3 to 5 ° C. higher than the target value), and if (FUTEMP) ≦ STBNDH, then <
Jump to FMAXRST>. (FUTEMP)>
If STBNDH, that is, STBNDL <(FUTEMP) <STBNDH, compare (FUTEMP) with the fixing heater temperature (PREFUT) at the start of the previous copy,
If (FUTEMP) ≤ (PREFUT), jump to <FMAXST> and click (FUT
If EMP)> (PREFUT), proceed to <FMAXRST>.

In <FMAXRST>, the duty discrimination flag (FUCMAX) is reset to fix the duty to 0%, and the counter (FUC
Clear NT). In <FMAXST>, the flag (FUCM
AX) is set to fix the duty to 100%, and SPTM61 (30) is set to the counter (FUCNT).

Finally, the contents of (FUTEMP) are stored in (PREFUT), and (PREFUT) is updated.

(14) CTLOFF ... Fig. 7h In this subroutine, the zero-cross signal [ZCP] is 10
It is executed when it is missing for 0 msec or more. In this routine, the fixing heater drive signal [FUHDRV], the lamp drive signal [LMPDRV] and the main motor drive signal [MOTDRV] are turned off and the counter (HETC
Set 1 to (NT) and (PNTCNT) and (HTS
PTM) reset and zero cross interrupt mask (MK
Cancel 1).

(15) CHKPRT ... Fig. 7g In this subroutine, in the lamp test mode,
This is for detecting the edge of the print key operation.

First, it is checked whether the lamp test mode (when both (ACTEST) and (LPTEST) are "1"). In the lamp test mode, the print key flag (KPRINT) is checked. If it is "1" (print key on),
The print key edge flag (PRTEDG) is checked, and if "0", the flag (PRTEDG) is set, and the state of the lamp-on flag (LMPON) is reversed. If the flag (KPRINT) is "0" (print key off), the flag (PRTEDG) is reset. Even when the lamp test mode is not set, the flag (PRT
EDG) is reset.

(16) SETEM ... FIG. 9 In this subroutine, the target value of the fixing heater temperature and the control cycle are set.

First, the fixing heater control cycle counter (HETCNT) is set to have a control cycle of 1 second, that is, SPTM51 is set to 25 for 50 Hz and SPTM61 is set to 30 for 60 Hz. Then, 3 is set in the quaternary counter (QADCNT). Next, check the flag (INITMP),
If it is "0", that is, immediately after the power is turned on, the sampled fixing heater temperature (FUTEMP) is stored in the initial fixing heater temperature register (IFUTMP), the previous fixing heater temperature register (FUTN1) and the pre-previous fixing heater temperature register (FUTN2). , Thermistor disconnection detection timer value THBTIM (10) is set in the register (THBCNT).

Next, the fixing heater temperature target value register (SETFUS)
The target value FUSET (185 ° C.) is set to, and when the preheating mode ((PRHT) is “1”, the target value FDNSET (175 ° C.) at the time of preheating is reset to (SETFUS).

Next, the temperature control cycle flag (HTSPTM) is checked, and if it is "0" (control cycle 1 second), (FUTEM
P) and pre-reload temperature PRTEMP (175 ° C.) are compared. If (FUTEMP) ≧ PRTEMP, flag (HTSPTM)
Set.

If (FUTEMP) <PRTEMP and preheat mode, (FUTEMP)
And FDNSET-5 (170 ℃) are compared, and (FUTEMP) ≧
If DCNSET-5, the flag (HTSPTM) is set.
If (FUTEMP) <DCNSET-5, the flag (PNTCNT) is reset.

If the flag (HTSPTM) is "1" (control cycle 5 seconds), the above operation is skipped.

(17) RESFUC ... FIG. 11 In this subroutine, the fixing heater on-cycle number 0 or 100% is set in the counter in the copy mode, that is, when the on-cycle number (duty) of the fixing heater is fixed.

0 if the flag (FUCMAX) in the fixing heater on-cycle counter (FUCNT) is "0" (duty 0%)
Flag (FUCMAX) is "1" (duty 10
If it is 0%, set SPTM61 (30). Then, the fixing heater on-cycle register (FUCYC) is reset.

(18) FUPID ... FIG. 10a In this subroutine, the number of on-cycles (duty) of the fixing heater is updated.

First, (FUTEMP) is stored in the current fixing heater temperature register (FUTN0). Then, the temperature target value (S
ETFUS) and each PID constant (proportional, integral, differential constant) are set, a subroutine PID is called, and a change (EM) in the number of fixing heater on-cycles is obtained. Next, a subroutine COLCYC is called based on the number of on-cycles and control cycle of the fixing heater at the previous time to update the number of on-cycles (FUCYC).

(19) PID ... 10b This subroutine is used in the subroutine FUPID.

In this routine, the following calculation is performed to obtain the change (EM) in the on-cycle of the fixing heater.

(PT) = (FUTN1) − (FUTNO) ・ ・ ・ ・ (7) (IT) ＝ (FUSET) − (FUTNO) ・ ・ ・ ・ (8) (DT) ＝ (PT) − [(TN2) − ( (TN1)] ··· (9) (EM) = Kp × (PT) + (KIM / KID) · (IT) + (KDM / KDD) · (DT) · · · (10) where Kp, KIM, KID, KDM, and KDD are constants determined by the characteristics of the fixing heater.

(20) CALEM ... 10c This subroutine is used in the subroutine PID.

In this routine, the multiplication result of each term in the equation (10) is added to obtain (EM).

(21) SUBT ... FIG. 13a This subroutine performs the subtraction processing of the following equation.

(A) = (A) − (B) (11) However, the calculation result is in the range of −255 to +255, and (A)
The value of is an absolute value, that is, 0 ≦ (A) ≦ 255. The code is the code register (S
It is identified by SD (bit 2) of IGN). SD is "0"
Then, it is positive or 0, and if SD is "1", it is negative.

(22) COLCYC ... FIG. 10d This subroutine is used in the subroutine FUPID. In this routine, (FUCYC) is updated.

(EM) is added to the number of fixing heater on cycles (FUCYC), and if the result is negative, 0 is set to (FUCYC), and if the result is larger than the control period, the control period data (B) is set.

That is, 0 ≦ (FUCYC) ≦ (B).

(23) CONVAD ... FIG. 7b In this subroutine, the following equation is calculated.

(A) = (A) · [(B) / (C)] + (D)
(12) However, the calculation result (A) is limited to the range of 0 to 255.

(24) CONVSUB ... FIG. 13b In this subroutine, the following equation is calculated.

(A) = (A). [(B) / (C)] + (E) ...
(13) However, the calculation result (A) is limited to the range of 0 to 255.

(25) CHKVLT ... Fig. 7f In this subroutine, the lighting state of the lamp is checked.

In the lamp test mode, that is, when both (ACTEST) and (LPTEST) are “1”, or the lamp detection voltage (RMS) is the lamp-on determination data ONRMS.
In the following cases, the lamp lighting state flag (LON) is reset (lamp off state).

If the lamp detection voltage (RMS) is higher than ONRMS when not in the lamp test mode, the flag (LO
N) is set (lamp is on).

Information of the flag (LON) is the sequence control unit 2
Sent to 0.

(26) CHKTMP ... Fig. 12 In this subroutine, the temperature of the fixing heater is checked.

First, overheat, thermistor disconnection, pre-reload temperature and reload temperature flags (OVRH), (T
HBRK), (PERRLD) and (RELOAD) are reset. Next, if (FUTEMP) is equal to or higher than the overheat discrimination data FUULT (288 ° C.), the flag (OVRH) is set. Next, (FUTEMP)
If is less than or equal to the thermistor disconnection discrimination data FUULT (30 ° C.), the subroutine BRKTIM is called. Then, the thermistor disconnection determination flag (BRKFLG) is checked, and if it is "1" (10 seconds have elapsed) (FUTE
MP) and (IFUTEMP) are compared, and (FUTEM
If P) ≦ (IFUTEMP), the flag (THBRK) is set.

When (FUTEMP) is larger than FULLLT, (FUTEMP) is compared with pre-reload temperature determination data PRTEMP (175 ° C) and reload temperature determination data RLTEMP (180 ° C), respectively, and (FUTEM
(P) ≧ PRTEMP, set the pre-reload flag (PRERLD) to (FUTEM
If P) ≧ RLTEMP, set the reload flags (RELOAD) to “1” respectively.

These flags (OVRH), (THBRK), (PR
The information of (ERLD) and (RELOAD) becomes transmission data sent to the sequence control unit 20.

(27) BRKTIM ... FIG. 12 This is a subroutine used in the above-mentioned subroutine CHKTMP.

This routine functions as a 10-second timer for determining the thermistor disconnection. Thermistor disconnection discrimination counter (THB
CNT) is set to 10 (10 seconds) when the power is turned on, and decremented every time this routine BRKTIM is executed. If this subroutine has a suspicion of a thermistor disconnection, that is, if (FUTEMP) ≦ FUUL,
It is executed once every second. And a counter (THBC
When NT) becomes 0, the flag (BRKFLG) is set.

(28) CONDM ... Fig. 8 In this subroutine, the internal processing data is converted into the numerical data to be displayed on the operation panel. In particular,
The internal processing data of voltage, phase angle, and temperature are V
Convert to numerical data of each unit of rms, msec and ° C.

Since there are four types of data to be converted, a quaternary counter (BR
KCNT), and when the contents are 0, 1, 2, and 3, (RMS), (SETRMS), (PHA
NGL) and (FUTEMP) to (VOLT), (S
TVOLT), (PHTIM), and (FUDEG). The conversion is performed according to the following equation.

(VOLT) = (5/8) × (RMS) ・ ・ ・ ・ (14) (STVOLT) ＝ (5/8) × (SETRMS) ・ ・ ・ ・ (15) (PHTIM) ＝ (1/26) × (PHANGL) ・ ・ ・ ・ (16) (FUDEG) ＝ (a / b) × (FUTEMP) ＋ c ・ ・ ・ ・ (17) The values of the fluctuations a, b, and c shown in the equation (17) are as follows. It is determined according to the contents of (FUTEMP) as shown in Table 1.

[Effect] As described above, according to the present invention, the status reading / scanning control of the input means such as a key switch, the dynamic display energizing control of the display means, the data transmission control, and the signal from the load status detecting means are read control and signal. Since the load energization switching control based on time is repeatedly performed in a time-division manner, various conventional control elements can be replaced by a single microcomputer, and even if the light quantity control of the exposure lamp is performed by digital control, the configuration becomes complicated. I won't.

[Brief description of drawings]

FIG. 1a is a block diagram showing an outline of a control circuit of a copying machine of one type for carrying out the present invention, and FIG. 1b is a block diagram showing an outline of the operation control unit 30 of FIG. 1a. 2a, 2b and 2c are electrical circuit diagrams showing the operation control unit of FIG. 1a. FIG. 2d is a block diagram showing the internal configuration of the microcomputer 100 shown in FIGS. 2a and 2b. FIG. 3 is a timing chart showing signal waveforms of respective parts of the operation control unit 20 and processing timings. FIG. 4 is a flowchart showing a schematic operation of the microcomputer 100 shown in FIGS. 2a and 2b. Figures 5a, 5b, 5c, 5d, 5e, 5e, 6a, 6b, 6c, 6d, 6e, 6f, 6g, 6h. Figure, Figure 7a, Figure 7b, Figure 7c, Figure 7d, Figure 7e, Figure 7f, Figure 7g, Figure 7h, Figure 7i, Figure 8, Figure 9, Figure 10a, 10b, 10c, 10d, 11, 11, 12, 13a and 1
FIG. 3b is a flowchart showing the detailed operation of each interrupt processing routine and subroutine of the microcomputer 100. FIG. 14 is a block diagram showing a conventional example of a control device for a copying machine. 4 ... Actuator, 5 ... Sensor 6 (MT) ... Main motor 7 (HT) ... Fixing heater 8 (LP) ... Exposure lamp (AC load means) 20 ... Sequence control unit 30 ... Operation control unit 40 ... Optical system control unit 100 ... Microcomputer (electronic control means) 110 ... Reset circuit 120 ... Three-state buffers 130, 131 ... Comparator 140 ... Timer circuit 150 ... Level conversion circuit (load state detection means) ) 160, 180, 190, 220 ... driver 170 ... decoder, 200 ... noise filter 210, 230 ... resistor array 240 ... key switch matrix (input means) 250 ... light emitting diode matrix (display means) TRC501, TRC502, TRC503 ... Triac (switching means) DB501-DB505 ... DA Eau bridge PC501, PC502, PC503 ...... photocouplers TR501, TR502 ...... trans RA501 ...... safety relay B1 ...... serial I / O circuit (data transmission means) TH: thermistor, VR202 ...... variable resistor

Continuation of front page (56) Reference JP-A-60-41065 (JP, A) JP-A-57-64749 (JP, A) JP-A-57-157258 (JP, A) JP-A-57-20748 (JP , A) JP 56-47052 (JP, A) JP 60-2963 (JP, A) JP 56-50424 (JP, A) JP 56-4157 (JP, A) JP 59-34552 (JP, A) JP 59-88728 (JP, A) JP 60-2964 (JP, A) JP 58-130349 (JP, A) JP 58-130350 (JP, A)

Claims (2)

[Claims] 1. A plurality of input means; a plurality of display means; a data transmission means for performing data transmission with another control device; an AC load means having at least an exposure lamp; and an ON / OFF control of energization of the AC load means. A switching means; a load state detecting means for outputting a signal according to the electric power applied to the AC load means; a zero cross detecting means for outputting a signal synchronized with a zero cross point of an AC power supply waveform; and a state reading scanning control of the input means. , Dynamic display energizing control of the display means, control of data transmission with another control device, read control of a signal from the load state detecting means, calculation based on the signal and control of the switching means according to the result , Are repeatedly performed at different timings, and the result of counting the synchronization signals output by the zero-cross detection means is displayed. Responsive to at least the 0th cycle and the 1st cycle, the signal is read from the load state detecting means in the 0th cycle in synchronization with the synchronizing signal, and in the 1st cycle. A control device for office equipment, comprising: an electronic control means for performing an operation based on a signal read in the 0th cycle and controlling the switching means in accordance with the result. 2. The control device for office equipment according to claim 1, wherein the AC load means includes a fixing heater, and the electronic control means independently controls the exposure lamp and the fixing heater. .