JPS5938759A - Image forming device - Google Patents

Abstract

PURPOSE:To enable the judgement of the abnormality in the transfer of data between plural microcomputers, by investigating whether diagnosis data is fed within a prescribed time or not. CONSTITUTION:A microcomputer A performs real time processing such as inputting of the number of copying sheets, checking of whether a copying button is pushed or not and displaying of the number of copying sheets. A microcomputer B controls the sequence of the stage for electrophotographic copying. When there is a request REQ for data transfer from the microcomputer A and the microcomputer B is ready to accept the data transfer, said microcomputer informs to the microcomputer A of the acceptable REQ.E and in synchronizing with a shift clock SCK, the data is serially transferred from an output port SO to an input SI between the microcomputers A and B. When the operator pushes a diagnosis switch SW1, the diagnosis data is fed and after a prescribed time, the diagnosis data is compared with the diagnosis data stored beforehand and if both data are not identical, the computer judges that the transfer is anomalous and lights an alarm lamp PL.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field The present invention relates to a control section having a program memory, for example, an apparatus for forming one image under the control of a one-chip microcomputer.

(11) Prior Art There has been remarkable progress in electronic technology in recent years. In particular, the integration of electrical and electronic circuits has progressed, and high-performance microcomputers have appeared, which are used to control various devices. Therefore, in recent years, control methods using microcomputers have become common even in the control of copying machines, and as copying machines are required to have higher performance, higher speed, and more functionality, multiple microcontrollers are used instead of one microcontroller. At present, it has become necessary to control the copying unit, AI) F, sorter, etc. for each function using the following. When controlling a plurality of microcomputers according to their respective functions, methods have been proposed in which each data is transferred in parallel using the output ports of each microcomputer, or by using serial transfer.

However, when it comes to errors between microcontrollers during data transfer, for example, errors such as poor contact between one interface and two peripheral devices and an interface, noise, etc., especially in the case of serial transfer, it is difficult to find the cause. The disadvantage was that it took time and slowed down the process.

(10 Objects) In order to improve the drawbacks of the above-mentioned conventional example, the present invention uses a timer means to perform data transfer diagnosis during data transfer between the microcomputers. The purpose is to detect abnormalities in the system.

Embodiment FIG. 1 is a block diagram of microcomputer control used in the control of the present invention. First, in Figure 1, two microcontrollers (
The control means of the present invention will be explained using 4) and (B).

In order to communicate with the operator, i.e., to inform the operator of the desired number of copies entered using a key or other means, the microcomputer displays the set number of copies, the number of copies, etc., and issues copy commands (start), stop, etc. , and other real-time control functions such as force set size selection and display. On the other hand, the microcomputer 03) performs various controls necessary for the copying process, such as band control, and controls the main motor (MI), paper feed timing (P F ), etc.
, exposure lamp (L), optical drive (p″Wl)), etc. In this example, serial transfer means is used as a means for exchanging information or exchanging data between the microcomputer and the microcomputer (IJ). .

In Figure 1, the serial output (SO
) to the serial input (SI) of the microcontroller (I3),
From the serial output (80) of the microcomputer (B) to the microcomputer (
5) to the serial input (SI), and the shift clock (5CK) is connected from the microcomputer to the microcomputer (B), and from the output port PE of the microcomputer,
A signal (REQ, 0) to notify the microcomputer Q3) of a data transfer command is output and connected to the input port PAO of the microcomputer (B), and if the acceptance system of the microcomputer (B) is set, then the signal (REQ, 0) is output to the microcomputer Q3). Output port PEo
The REQ input signal (REQ, E) is outputted and transmitted to the input port PAo of the microcomputer.

For example, the microcomputer (4) determines that the operator has pressed the copy button, and the sequence control microcomputer (6) determines that the operator has pressed the copy button.
) To transfer the copy start command data to the microcomputer (4), first output the copy command data from SO in the microcomputer (4), so set it in the shift register and send the signal REQ out( R.E.
Q, 0) is sent to the microcomputer (B). The microcomputer (B) receives the REQout signal (REQ, 0) and sets the status of the microcomputer (13), for example, data indicating whether the current copy cycle is in standby, to the shift register output from the data transfer SO. ≠41'h
Notify the microcomputer (4) that the data transfer state is complete. When the microcontroller (A) receives the REQ input signal (REQ, E), data transfer starts, and when the transfer is completed, an internal interrupt occurs in the microcontrollers (4) and (B). Data is determined within internal interrupt processing.

Further, SWI in FIG. 1 is a data transfer diagnosis switch, and lamp PL is an abnormality display as a result. Incidentally, a timer means is set to operate at the same time as the diagnostic switch is turned on.

FIG. 2 is a control block diagram of the shift register. The operation of the shift register can be controlled by controlling the register F/F by software, and internal interrupt processing is generated by interrupt Ii'/F. Interrupt F/
F is set by an interrupt enable signal (software) and a signal generated when the shift register stops operating.

Further, the shift register is connected to an accumulator (ACC) by an internal hash line of the microcomputer, and data can be transferred from the ACC to the shift register, and data can also be transferred from the shift register to the ACC.

FIG. 3 is a detailed diagram when a transfer means using a serial shift register is connected to microcomputers (4) and (B).

The shift register used in the present invention has 16 pits, each having 4 bits from STO to ST3. The shift register operates in synchronization with the shift clock (SCK), and the shift clock is generated from the microcomputer.

FIG. 4 is a timing diagram of serial data transfer.

As explained above, (B) sets the respective data to the shift register, sets the interrupt input, and sets the interrupt input to the shift register F. By setting /F, the shift clock (
SCK) and transfers mutually set data to each microcomputer along with a shift clock. Then, when the shift clock ends, the microcontrollers become prisoners of each other.

(B) When an internal interrupt occurs, each internal interrupt switch
When detecting that 1 is turned on, the microcomputer (13) sets data 15 to the transfer register ST3 as shown in the figure.

The above has described the control means using two microcomputers, but when the device is systemized, not only a copying machine but also an automatic document feeder (AI) and a sorter device are required.

Figure 7 ℃ is AI) F based on target transfer means.

FIG. 2 is a control block diagram including sorter control.

The microcontrollers (5) and (B) perform the above-mentioned role, and the serial shift register as a means of exchanging personal information is connected in series to #-1 = Fig. 1 for efficient transfer. be.

Figure 8 °C is ADF as shown in the example in Figure 7.

It is a control block diagram in which serial shift registers are connected in parallel when a sorter or the like is added. Compared to the case where the serial shift registers are transferred in series as shown in FIG. 7, the transfer speed (time required for the same decision) is faster when connected in parallel as shown in FIG. 8.

FIG. 9 shows two microcomputers (4) according to the present invention.

13 is a flowchart showing the data transfer operation according to (13). FIG. First, the microcomputer (5) will be explained.

1) Reset the OWERONN step 1 data memory I10 (click the button, and then in step 2, press the operation unit (not shown)
Perform key manual judgment and display processing, and check the register F/F in step 3.

This register F/Ii" determines whether the shift register is operating. Next, in step 4, it is determined whether the copy button was pressed in step 2. If the copy button was pressed, the process moves to step 5. As shown in Fig. 5, the copy start command sets ST3 to 13 as the data to be sent by the sequence microcomputer (B).In order to execute this, first the accumulator (Ac
e), and in step 11, add 13 to the accumulator (A
GC) is set in ST3 of the shift register.

Further, if the stop key is pressed, it is determined in step 6, and 14 is set in the accuno and lata in step 7.

After data is set in the shift register S13 in step 11, in step 12, the register F'/F that enables the shift register to be transferred and the interrupt enable that sets the interrupt F/F are set, and the REQout signal (REQ ,0
) is sent to the microcontroller (I3). In step 14, the REQ input signal (I(EQ,E
) and input the REQ input signal (REQ, E) manually, the process moves to step 15 and the REQout signal (REQ, E) is input manually.
0) and start data transfer starting at step 16.

The above is the data transfer means of the microcomputer (A), but as shown in Figure 1, the SW1 is the microcomputer (A) and (B), respectively.
) Since it is connected to PAI, the switch SW1 of the external command means is ON.
A timer activated by the timer allows data diagnostic operations to be performed at certain predetermined times.

First, the microcomputer (A) constantly checks the diagnostic switch at step 8 in Figure 9, so when SWl is turned on, the answer is YES at step 8, and the process moves to step 9. At step 9, the register is transferred to the accumulator as diagnostic data. Set the data 15 to be input to ST3, hit the F/diagnosis flag, and proceed to step 11.

Therefore, by turning on SW1, the microcontroller (A)
determines that it is in the diagnostic mode and transfers the diagnostic data to the microcomputer (B) in step 16 using the method described above. To cancel the diagnosis,
When the diagnostic switch is turned ON, a predetermined time of a timer that is activated has elapsed, and the diagnostic switch is turned Off.
It is automatically canceled when it becomes F.

Explain the microcomputer 03) to the doctor. POWEILO
Step 30 after N Step 30 (1, CAM) or Il
o is reset, the copy preparation cycle is checked in step 31, and the operation of the shift register, that is, the shift register F/F is checked in step 32. Next step 3
At step 3, it is checked whether there is a data transfer request from the microcomputer (4), and if there is a data transfer request from the microcomputer, the process moves to step 34. In step 34, it is determined whether the data diagnosis switch SWl has been pressed in the same way as the microcomputer prisoner. If it has not been pressed, the F/diagnosis flag is reset in step 35, and in the next steps 36 to 42, the microcomputer (B
) Preparations are made to set information to notify the microcomputer (5) of the operating state of the microcomputer (5) in the shift registers STO-3.

If it is determined in step 34 that the diagnostic switch is pressed, the process moves to step 38, where the diagnostic controller is set to 1/diagnosis, and the microcomputer (step 39C) is used as a diagnostic gator.
Similarly to step 4), data 15 is set in the accumulator to be set in the transfer register ST3, and in step 4
'1' Set the data to 3.The diagnostic switch is connected to the microcontrollers (5) and (B) as shown in Figure 1, so the diagnosis mode is mostly determined by the microcontrollers (5) and 03.
), and data diagnosis can be performed for each. Steps 35 to 42 are an example in which the microcomputer (B) sets standby state data to STO in STO. , the data contents from the microcomputer (B) to the microcomputer are as shown in Figure S6. After setting the data in the soft register, the register F/F interrupt enable is set, the output port PE is set, and a data transfer OK signal (IζEQ, E) is output in step 42. Then, in step 43, F/5TART is checked to confirm that the copy start command has been transferred by the interrupt routine.

Here, an interrupt routine that occurs when the data transfer is completed after the start of data transfer in the step of the microcomputer 03) will be explained. The interrupt generation timing by microcomputer (B) is almost simultaneous.0 We will explain from microcomputer (4). When an interrupt occurs, the data sent from the microcomputer (B) has been set in the shift register, so the contents of the shift register (here we will talk about STO and diagnosis) are set in the agitator (steps 18, 19, 21).

However, the contents of the accumulator are judged to determine what data has been sent. A in step 19
When CC=0, it indicates that the microcomputer (13) is in standby state, and the operation til! Controls processing flags that allow KEY input and display in (
Step 20).

Also, if ACC=8 is determined in step 21, the microcomputer (
It can be determined that 1() is in the process of copying)
The flame signal that enables prohibition of Y input, etc. is controlled (step 22). Then, in step 26, register F
/F and reset the interrupt enable pull.

At the time of data transfer diagnosis, since F/diagnosis is YES in step 17, the contents of the transfer register ST3 to be checked for diagnostic data from the microcomputer 03) are transferred to the accumulator in step 23, and the accumulator is judged in step 24 to confirm the contents. If it is 15, proceed directly to step 26, assuming that an abnormality occurs in the data transfer system or transfer mechanism.
If the abnormal data is inputted within the predetermined time of the timer and is not 15, the process moves to step 25, where the output port PE1 for abnormality display is set and the lamp is turned on.

Next, in the interrupt routine of the microcomputer (B), the contents of the shift register are transferred to the accumulator in the same way as in the case of the microcomputer (step 50). First, in step 51, it is determined whether ACC is diagnostic data 15, and if no, If the ACC is 213 in step 52, it is determined that it is a copy command, and in step 54, 7 lag F/S'l'ART is set. Also, if ACC=14 in step 53, it is regarded as a copy stop command, and in step 56, 7 lag F/5 is issued.
Set TOP. Then, in step 57, register F
/F, resets the interrupt enable and goes to step 58
Then R1 (resets the output of the Q input pull. Therefore, it is determined that it is a microcomputer, and in step 55 it is the same as the microcomputer (a)))
Set E. ``Two-in-one diagnosis'' to
Store Ohhiba A- no Nimai [Ushimoto]
The copying operation is performed in step 45 and step 4.
Reference numeral 6 relates to a data transfer means for determining whether or not F/5TOP has been sent in step 47. If there is a stop command, the process moves to step 49, a post-copy cycle. In this embodiment, an example of data diagnosis and copy start and stop is described, but in reality, data transfer contents are
As shown in the figure, there are many.

The case where there are two microcontrollers has been explained above, but the seventh and eighth
As shown in the figure, three or more microcomputers are used and the serial transfer means are connected in series and in parallel, and the subcommittee is explained. The data transfer method for each microcontroller is basically the same as the method for the two microcontrollers described above, but in order to ensure that the information is sent to each microcontroller as soon as it is transferred, assign a number to each microcontroller and send it to yourself. 1υ"Also, when transferring data, it is necessary to add the destination microcomputer number. Figure 10 is an implementation diagram when the transfer volume is determined for each microcomputer described above. .Distribute the transfer destination data of each microcomputer to S 'f' 3 of the shift register.In the actual JtN example, 8'r3 is oo
For ol (1), microcomputer (5), for 0010 (2), microcomputer (13), for no l 1 (3), microcomputer (C), for o 100 (4), microcomputer (D). ). That is, when each microcomputer sets transfer data to the microcomputer to which it wants to transfer, it sets the transfer destination microcomputer number in Sr1.

Then, data transfer is started, and the destination microcontroller checks ST3 after an interrupt occurs to determine whether the data has been sent to itself, and then sends Sr1
If the volume of is the data sent to you, STO~S
Read the data of T2 and judge the data content.

This is specifically shown in the flow chart of FIG. 11. FIG. 11 shows an interrupt routine caused by the occurrence of an interrupt after data transfer of each microcomputer. That is, each microcomputer first moves 81"3 of the shift register to the accumulator (ACC) in step 60, and checks the contents of the accumulator in step 61. If the content of the accumulator is 1, the microcomputer is locked.

In case of 2, microcomputer (B), in case of 3, microcomputer F
c) In the case of 4, it is the microcomputer (6), so if each microcomputer determines that it is its own data, the contents of the shift registers STO to ST2 are stored in the data memory (RAM) via the ayumulator in step 62, and in step 63 Determine the contents of the data stored in RAM with
Perform each process. If it is determined in step 61 that the data is not sent to you, step 6
Move on to 4. In step 64, preparations are made to immediately transfer the data sent as is to another microcomputer.

On the other hand, the method of preparing for transfer by storing 1-1 in the shift register to the transfer destination microcomputer is the same as steps 3 to 16 in Figure 9, but here you must be sure to
Must be set to 8T3. Therefore, by the above means, even when the serial transfer means of three or more microcomputers shown in FIGS. 7 and 8 are connected in series or in parallel, information can be easily exchanged between the microcomputers. However, if the serial transfer means are connected in parallel as shown in Figure 8, the microcontroller serves as the master microcontroller, and only the microcontroller (5) determines the transfer destination data of each microcontroller shown in Figure 11. (B).

(C), Q)) Each requires processing to determine the transfer destination data. Therefore, it is advantageous to connect the serial transfer means in parallel as shown in FIG. that's all,
Regardless of whether the connection is serial or parallel, it is possible to diagnose each data by providing a diagnostic switch.

Furthermore, in each microcomputer, when performing γ-data transfer, a diagnostic flag is set, and a timer is activated so that the diagnostic flag is reset when the transmission/reception system is completed or the transfer is performed. If the diagnostic flag remains set even after the predetermined time of the timer has elapsed, it may be determined that there is an abnormality, and the abnormality may be displayed.

As described above, whether the connection is serial or parallel, each data can be easily diagnosed by using a timer.

(V) Effects As detailed above, according to the present invention, by using a timer as a means for diagnosing data transfer between microcomputers, it is possible to investigate and deal with the causes of errors that occur from time to time. It is no longer necessary to spend a large amount of time on
Improved performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram of microcomputer control used for control of the present invention. FIG. 2 is a control block diagram of the shift register. FIG. 3 is a detailed diagram of a transfer means using a serial shift register connected to microcomputers (A) and (B). FIG. 4 is a timing diagram of serial data transfer. FIG. 5 shows the data contents for transferring information from the microcomputer to the microcomputer (B). Figure 6 shows data contents E, v'J, which transfer information from the microcomputer (B) to the microcomputer prisoner. FIG. 7 is a block diagram including AI)F, sorter control, etc. in FIG. 1. FIG. 8 is a control block diagram in which the serial shift registers in FIG. 7 are connected in parallel. FIG. 9 shows two microcontrollers according to the present invention. (J3) is a flowchart diagram showing the data transfer operation. FIG. 10 is an implementation diagram when a transfer number is determined in the microcomputer to ensure transfer. FIG. 11 is a flowchart for determining the transfer destination. Applicant: Gyanon Co., Ltd.

Claims (1)

[Scope of Claims] (1) In an image forming apparatus using a plurality of microcomputers, when data is transferred between each microcomputer, a timer means is operated to establish a transmission/reception system within a predetermined time. An image forming apparatus characterized in that if data transfer is not completed or data transfer is not activated, it is determined that there is an abnormality in data transfer, and the abnormality is displayed. (2. The image forming apparatus according to claim 1, wherein the timer means is activated when the diagnostic switch is turned on.) (3) An image forming apparatus according to claim 1, wherein the timer means is activated at the same time as the transmission/reception system of each of the microcomputers is set.