JPS594115A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS594115A
JPS594115A JP11317482A JP11317482A JPS594115A JP S594115 A JPS594115 A JP S594115A JP 11317482 A JP11317482 A JP 11317482A JP 11317482 A JP11317482 A JP 11317482A JP S594115 A JPS594115 A JP S594115A
Authority
JP
Japan
Prior art keywords
wafer
etching
oxide film
visible
covering oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11317482A
Other languages
Japanese (ja)
Inventor
Masashi Sasaki
政司 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11317482A priority Critical patent/JPS594115A/en
Publication of JPS594115A publication Critical patent/JPS594115A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54493Peripheral marks on wafers, e.g. orientation flats, notches, lot number

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To make it possible to write without developing silicon powder or protrusion that becomes an obstacle to wafer process by forming an covering oxide film on the whole surface of a wafer and making anisotropic etching advance by using etching liquid to the extent that visible steps are formed. CONSTITUTION:A covering oxide film 9 is grown on a wafer 1 by chemical vapor phase growth method or thermal oxidation. Next, a resist film is formed on the whole surface by painting and patterning that corresponds to desired numbering is applied to the film to open a window 10 in the covering oxide film 9. Then, etching is made on the wafer 1 by the ordinary ammonia boring to form a groove 11 with depth of 8-10mum. In the ordinary etching in the wafer process it is about 1mum and it can not be seen, but the steps given by the deep groove are visible and they make it easy to recognize wafers in the following processes, and contribute to high yield in the manufacture of semiconductors.

Description

【発明の詳細な説明】 (1)発明の技術分野 本発明は半導体装置の製造方法、詳しくは異方性エツチ
ングによるウェハのナンバリング(番号等の形成)の方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for numbering wafers (forming numbers, etc.) by anisotropic etching.

(2)技術の背景 半導体装置製造においてウェハに種々の処理(ウェハプ
ロセス)が実施されるが、その最初の段階でウェハに認
識のために番号等を形成するこ(1) とがなされる。
(2) Background of the Technology In the manufacture of semiconductor devices, wafers are subjected to various processes (wafer processes), and the first step is to form numbers, etc. on the wafers for identification (1).

かかるナンバリングを第1図(alの平面図を参照し゛
ζ説明すると、ウェハ1のファセットライン2(結晶方
位確認用の切断面に沿う線)または周縁近くの位置3に
掘り込みを形成することによって番号が付けられる。こ
の番号は通常ロフト番号とロフト内の通し番号その他か
ら成り、ロフト内にはウェハが50枚あるのが一般であ
るから、最小3桁、多いときは7桁もの数字が付けられ
る。かかるナンバリングによってウェハば1枚ずつ認識
可能になるものであり、ナンバリングは半導体装置の製
造において不可欠の工程である。
To explain such numbering with reference to the plan view of FIG. A number is assigned. This number usually consists of a loft number, a serial number within the loft, etc. Since there are generally 50 wafers in a loft, a minimum of 3 digits and as many as 7 digits are assigned. This numbering makes it possible to recognize each wafer one by one, and numbering is an essential step in the manufacture of semiconductor devices.

(3)従来技術と問題点 従来、ウェハプロセスにおけるナンバリングはダイヤモ
ンドペンシルを用いる方法とレーザによるナンバリング
との二つの方法によりなされている。
(3) Prior Art and Problems Conventionally, numbering in wafer processing has been performed by two methods: a method using a diamond pencil and a numbering method using a laser.

ダイヤモンドペンシルを用いる方法は、人がそれを用い
てウェハに認識可能な数字を書く (スクライブ)こと
によりなされ、第1図(blの断面図(2) に示される如く、ウェハ表面のシリコンを削り1■ンっ
でスクライブ部4を掘り込む。そうすると、シリコンの
細片または微粒粉5かウェハ全面−l−に飛び散って付
着し、それが以後のウェハプロセスにお6ノる障害とな
る。
The method using a diamond pencil involves a person using it to write recognizable numbers on the wafer (scribe), and as shown in Figure 1 (cross-sectional view (2) of BL), the silicon on the wafer surface is scraped. The scribe portion 4 is dug in one step. When this happens, silicon chips or fine particles 5 scatter and adhere to the entire surface of the wafer -l, which causes a hindrance to the subsequent wafer process.

他力、レーザを用いる方法においては、l/ −ザスボ
ソ(・をウェハ面に照射して点を掘り、この市の連続に
よって数字を構成する。この方法によっても、点のまわ
り大略5mm平方の範囲でシリコン粉が飛び散ることが
確認された。
In the method using a laser, a dot is dug by irradiating the wafer surface with l/-zasuboso(.), and a number is constructed by a series of these numbers. It was confirmed that silicon powder was scattered.

そこで、ウェハの裏面(デバイスが形成される表面の反
対面)にレーザで数字を掘ることが提案された。しかし
、ウェハにレーザ照射により点を掘ると、第1図(C1
の断面図に示される如く、掘られた点(レーザスポット
の当ったところ)6のまわりに隆起7力月O〜20μM
の高さに形成される。
Therefore, it was proposed to use a laser to engrave numbers on the back side of the wafer (the side opposite to the front side where the devices will be formed). However, when dots are dug on the wafer by laser irradiation, as shown in Figure 1 (C1
As shown in the cross-sectional view, there is a bulge 7 around the excavated point (where the laser spot hit) 6 with a diameter of ~20μM.
formed at a height of

レーザを用いたリーンハリングのなされたウェハ1を次
のプロセスのために例えばステージ8の−ににおいた場
合、第2図に示す如く隆起7によってウェハは傾いて蔽
密に平らに配置されない。な(3) お第2図において、隆起7はウェハ1にり=lL誇張し
4画かれ、同図以下において既に図示した部分と同じ部
分は同一符号を付して表示する。
When a wafer 1 that has been subjected to lean-haring using a laser is placed, for example, on a stage 8 for the next process, the wafer is tilted due to the bulges 7 as shown in FIG. 2, and is not arranged tightly and flatly. (3) In FIG. 2, the protuberance 7 is exaggerated by four strokes on the wafer 1, and in the following figures, the same parts as those already illustrated are denoted by the same reference numerals.

最近半導体装置の集積度を高めるために、パターンは微
細化される1す1向にある。そのため、シリコン粉の付
着およびウェハの傾いた載置番Jパターンを乱しまたは
ぼやけさせて、パターン微細化にり・jする障害となり
、製造歩留りと製品の信頼性を低下させるおそれがある
Recently, patterns are becoming increasingly finer in order to increase the degree of integration of semiconductor devices. Therefore, the adhesion of silicon powder and the tilted mounting number J pattern of the wafer are disturbed or blurred, which becomes an obstacle to pattern miniaturization, and there is a risk of lowering manufacturing yield and product reliability.

(4)発明の目的 本発明は上記従来の問題点に鑑み、ウェハプロセスの障
害となる原因を発生させることなく、容易な手段で確実
なナンバリングをなしうる方法を提供することを目的と
する。
(4) Purpose of the Invention In view of the above-mentioned conventional problems, it is an object of the present invention to provide a method that can perform reliable numbering by a simple means without causing any obstacles to the wafer process.

(5ノ発明の構成 そしてこの目的は本発明によれば、結晶方位(100)
、(211)等の主面をもつ結晶をアルカリ性エツチン
グ液によりエツチングする異方性エツチングを利用し、
ウェハの表面または裏面を深く掘って形成される段差に
より目視可能な番号を(4) 等を形成する方法を提供することによって達成される。
(5) Structure of the invention and this purpose is according to the invention, crystal orientation (100)
, (211), etc. using anisotropic etching, in which crystals with main faces such as (211) are etched with an alkaline etching solution.
This is achieved by providing a method of forming a visually visible number (4) etc. by a step formed by deeply digging the front or back surface of the wafer.

(6)発明の実施例 以下、本発明の実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

結晶方位(100) または(211)の主面をもつ結
晶はアルカリ性エツチング液を用いエツチングすると異
方性エツチングが進行する。本発明の方法においては、
かかる異方t’l:エンチングを深く進行させ、それに
よゲで形成される段差を利用して、顕微鏡等に異存する
ことなく目視可能な番号等を書き込む。それ故に、従来
技術において不可避であったシリコンわ)、隆起の発生
は皆無となる。
When a crystal having a principal plane with crystal orientation (100) or (211) is etched using an alkaline etching solution, anisotropic etching progresses. In the method of the present invention,
Such anisotropic t'l: Enching is progressed deeply, and by using the step formed by the etching, a number etc. that can be visually seen without appearing on a microscope etc. is written. Therefore, there is no occurrence of silicon bumps, which were unavoidable in the prior art.

本発明の方法を実施する]二程を第3図を参照し78Q
 明する。ウェハI上にカバー酸化膜9を化学気相成長
法(Cν1〕法)または熱酸化によって2000〜30
00人の厚さに成長する(同図(a))。次に、全面に
レジス日史(図示せず)を塗布形成し、それを所望の番
号等に対応してパターニングし、カバー酸化膜9に窓1
0を窓開けする(同図(h))。
Carrying out the method of the present invention] Step 2 with reference to Figure 3 78Q
I will clarify. A cover oxide film 9 is formed on the wafer I by chemical vapor deposition (Cv1) method or thermal oxidation to 2000 to 300%
It grows to a thickness of 0.00 people (Figure (a)). Next, a resist sheet (not shown) is applied and formed on the entire surface, and it is patterned in accordance with desired numbers, etc., and the window 1 is formed on the cover oxide film 9.
Open the window at 0 ((h) in the same figure).

(5) 次いで、通常のアンモニアボイルによってウェハ1のエ
ツチングをなし掘込み11を、例えば8〜10μmの深
さに形成する(同図(C))。ウェハプロセスにおける
通常のエツチングは1μm程度の深さになされ、それは
通常目視が可能でないが、本発明の方法においては前記
の如く深い掘込みによって得られる段差により目視可能
であり、そのことは以後のプロセスにおけるウェハ認識
を容易にし、半導体製造歩留り向上に寄与するところ大
である。また掘込み11の深さは、エツチング時間の調
蛯によって自在に制御しうる。
(5) Next, the wafer 1 is etched by ordinary ammonia boiling to form the recesses 11 to a depth of, for example, 8 to 10 μm (FIG. 3(C)). Normal etching in a wafer process is done to a depth of about 1 μm, which is usually not visible to the naked eye, but in the method of the present invention, it is visible due to the step obtained by deep digging as described above, and this will be explained in the following. It facilitates wafer recognition in the process and greatly contributes to improving semiconductor manufacturing yields. Further, the depth of the groove 11 can be freely controlled by adjusting the etching time.

ウェハに対しては、前処理(それはウェハをln浄にす
る目的でなされる)の段階でアルカリ性の液を用いるか
ら、本発明の方法はウェハ前処理と同時に実施可能であ
り、特に別途の工程を必要とするものでない。
Since an alkaline liquid is used for the wafer in the pre-treatment stage (which is done for the purpose of cleaning the wafer), the method of the present invention can be carried out simultaneously with the wafer pre-treatment, and in particular can be carried out in a separate step. does not require.

更に、ナンバリングは、ウェハの表面であれ裏面であれ
どの場所にでもなしうる。従来のナンバリングは、ウェ
ハの裏面で、かつファセットラインかまたは周縁の近く
でなされたが、このよう(6) な場所についての制約も全くない。
Additionally, numbering can be done anywhere on the wafer, either on the front or back side. Traditional numbering was done on the back side of the wafer and near the facet line or periphery, but there are also no restrictions on such location.

なお」−記においてはアルカリ液を用いるlνエソトエ
ソチングを例にとったが、本発明の異方性エツチングは
ドライエツチングによっても実施可能である。要は、異
方性エツチングを十分に進行させることによって、ウェ
ハに深い堀込みを形成してflられる段差により目視可
能な番号等を形成することである。
Although lv etching using an alkaline solution was used as an example in the above section, the anisotropic etching of the present invention can also be carried out by dry etching. The point is to allow the anisotropic etching to proceed sufficiently to form deep grooves in the wafer and to form numbers etc. that are visible by the stepped steps.

(7)発明の効果 以上、詳細に説明したように、本発明の方法によるとき
は、異方性エツチングを利用してウェハの任惹の場所に
目視可能な認識用の番号等を、以後のウニハブ1コセス
の障害となるシリコン粉または隆起を発生させることな
しに書込み可能となるので、半導体装置製造の歩留りと
、製品の信頼性向上に効果大である。
(7) Effects of the Invention As explained in detail above, when the method of the present invention is used, anisotropic etching is used to place a visible identification number etc. on a wafer at a designated location for subsequent use. Since it is possible to write without generating silicon powder or protuberances that would be a hindrance to the Unihub 1 process, it is highly effective in improving the yield of semiconductor device manufacturing and the reliability of products.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のナンバリング位置を実施する工程を説明
するための図で、その(alばウェハの平面図)(b)
と(C1とはウェハ要部の断面図、第2図は(7) ステージ−1−におかれたウェハの断面図、第3図は本
発明の方法を実施する工程におけるウェハ要部断面図で
ある。 1−ウェハ、2−ファセットライン、 3−ナンバリング位置、4−スクライブ部、5− シリ
コン粉、6− レーザスポット、7−隆起、8−ステー
ジ、9−カバー 酸化膜、10−窓、1】−堀込み (8) 第1図 (CI) Q) (b) (C)( 67 第2図 第3区
FIG. 1 is a diagram for explaining the process of performing conventional numbering positions, and its (al is a top view of a wafer) (b)
(C1 is a cross-sectional view of the main part of the wafer, FIG. 2 is a cross-sectional view of the wafer placed on stage-1- (7), and FIG. 3 is a cross-sectional view of the main part of the wafer in the process of carrying out the method of the present invention. 1-wafer, 2-facet line, 3-numbering position, 4-scribe portion, 5-silicon powder, 6-laser spot, 7-bump, 8-stage, 9-cover oxide film, 10-window, 1]-Drilling (8) Figure 1 (CI) Q) (b) (C) ( 67 Figure 2 Section 3

Claims (1)

【特許請求の範囲】[Claims] ウェハに認識番号等を記入する方法であって、ウェハの
全面にカバー酸化膜を形成し、該酸化膜を前記番号等の
パターンに対応して窓開げする工程、およびアルカリ性
エツチング液を用い目視可能な段差か形成される程度に
異方性エツチングを進行させる−[稈を含むことを特徴
とする半導体装置の製造方法。
A method of writing an identification number etc. on a wafer, which includes the steps of forming a cover oxide film on the entire surface of the wafer, opening a window in the oxide film corresponding to the pattern of the number, etc., and visual inspection using an alkaline etching solution. Anisotropic etching is progressed to such an extent that a possible step difference is formed.
JP11317482A 1982-06-30 1982-06-30 Manufacture of semiconductor device Pending JPS594115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11317482A JPS594115A (en) 1982-06-30 1982-06-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11317482A JPS594115A (en) 1982-06-30 1982-06-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS594115A true JPS594115A (en) 1984-01-10

Family

ID=14605423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11317482A Pending JPS594115A (en) 1982-06-30 1982-06-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS594115A (en)

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