JPS62166519A - Formation of pattern - Google Patents

Formation of pattern

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Publication number
JPS62166519A
JPS62166519A JP952186A JP952186A JPS62166519A JP S62166519 A JPS62166519 A JP S62166519A JP 952186 A JP952186 A JP 952186A JP 952186 A JP952186 A JP 952186A JP S62166519 A JPS62166519 A JP S62166519A
Authority
JP
Japan
Prior art keywords
resist
layer
pattern
substrate
positive resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP952186A
Other languages
Japanese (ja)
Inventor
Daishiyoku Shin
申 大▲水に是▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP952186A priority Critical patent/JPS62166519A/en
Publication of JPS62166519A publication Critical patent/JPS62166519A/en
Pending legal-status Critical Current

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  • Drying Of Semiconductors (AREA)
  • Electron Beam Exposure (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve the resolution by covering a substrate with a positive resist, emitting an ion beam to a pattern forming region on the resist to form a modified layer, and removing the resist except the region where the modified layer is formed. CONSTITUTION:A silicon substrate 1 is covered with a positive resist 2, and with a shielding plate 3 opened in a pattern as a mask P ion P<+> beam is emitted on the resist 2 to be implanted. Then, a modified layer 4 is formed by P<+> implanting, and the resist 2 except a region under the layer 4 is removed by a down flow type etching unit using O*. Then, the pattern of the resist having the same shape as the layer 4 is obtained. A part of the thickness of the resist 2 may be converted to the layer 4, or the entire thickness may be converted.

Description

【発明の詳細な説明】 〔概要〕 ポジレジストに、通常の半導体プロセスのドーパントと
して用いられる硼素(B) 、2(P)等のイオン注入
をして変質層のパターンを形成し、この後、酸素ラジカ
ル(0”)によるケミカルプラズマエツチング等を用い
て変質層のパターンを残してその他のポジレジストを除
去し、微細レジストパターンを形成する。
[Detailed Description of the Invention] [Summary] Ions of boron (B), 2 (P), etc., which are used as dopants in normal semiconductor processes, are implanted into a positive resist to form a pattern of an altered layer. Chemical plasma etching using oxygen radicals (0'') is used to remove the other positive resist, leaving a pattern of the altered layer, to form a fine resist pattern.

〔産業上の利用分野〕[Industrial application field]

本発明はイオン注入とドライ現像による新規な微細レジ
ストパターンの形成方法に関する。
The present invention relates to a novel method for forming fine resist patterns using ion implantation and dry development.

半導体集積回路の複雑化、微小化にともない、従来の単
層レジスト技術は精度上限界に近づき、2、または3層
レジスト技術が用いられるようになった。
As semiconductor integrated circuits become more complex and miniaturized, conventional single-layer resist technology approaches its accuracy limit, and two- or three-layer resist technology has come to be used.

しかしながら、多層レジスト技術は工程数が多く面倒で
、解像度も0.8μm程度のパターンが限度であるため
、さらに解像度を上げるためには新規な技術が必要とな
る。
However, multilayer resist technology requires a large number of steps and is troublesome, and the resolution is limited to a pattern of about 0.8 μm, so a new technology is required to further increase the resolution.

〔従来の技術〕[Conventional technology]

微細パターン形成のため、基板の平坦性(トポグラフィ
、ステップカバレージ)と表面反射率(解像度)を改善
するために、多層レジスト技術が数多く報告されている
Many multilayer resist techniques have been reported to improve substrate flatness (topography, step coverage) and surface reflectance (resolution) for fine pattern formation.

例えば、2層レジストプロセスとしては、厚い平坦化層
としてポリメチルメタクリレートI’HMAを被着し、
その上にノボラック−ナフトキノンジアゾポジレジスト
を被着したものがある。
For example, a two-layer resist process may include depositing polymethyl methacrylate I'HMA as a thick planarization layer;
A novolak-naphthoquinone diazo positive resist is deposited thereon.

また、3層レジストプロセスは、最初に最上層の薄い高
解像度のレジストにパターニングし、これを中間層の薄
い二酸化珪素(SiOz)層に転写し、最後にリアクテ
ィブイオンエツチング(RIE)法による異方性エツチ
ングを用いて、下地のレジストに再転写する方法である
In addition, the three-layer resist process first patterns a thin high-resolution resist as the top layer, transfers it to a thin silicon dioxide (SiOz) layer as an intermediate layer, and finally etches it using reactive ion etching (RIE). This method uses directional etching to retransfer onto the underlying resist.

以上の3層レジストプロセスを用いると、基板の平坦化
プロセスが行われるため、基板の凹凸に起因する多くの
問題が解決でき、また、異方性エンチングを使用するた
め解像度は向上する。
When the above three-layer resist process is used, many problems caused by unevenness of the substrate can be solved because the substrate is flattened, and the resolution is improved because anisotropic etching is used.

しかしながら、3層レジストプロセスは前記のように工
程が複雑化し、またそれに見合う装置も必要になる。
However, the three-layer resist process complicates the process as described above, and also requires corresponding equipment.

2層レジストプロセスは最上層と中間層の役割を併せも
つ材料を選んで工程の簡略化をはかったものである。
The two-layer resist process simplifies the process by selecting a material that has both the roles of the top layer and the middle layer.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の微細パターン形成技術では、解像度に限度があり
、0.5μmパターンの形成は困難である。
Conventional fine pattern forming techniques have a limited resolution and are difficult to form 0.5 μm patterns.

また、工程も複雑化する。Moreover, the process becomes complicated.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、基板上にポジレジストを被着し、
該ポジレジスト上のパターン形成領域にイオンビームを
照射し、該パターンに対応した変質層を該ポジレジスト
に形成し、該変質層が形成された領域下以外の該ポジレ
ジストを除去するパターン形成方法により達成される。
The solution to the above problem is to deposit a positive resist on the substrate,
A pattern forming method comprising: irradiating a pattern formation area on the positive resist with an ion beam, forming an altered layer corresponding to the pattern on the positive resist, and removing the positive resist other than under the area where the altered layer is formed. This is achieved by

例えば、イオンビームの照射はパターンを開口した遮蔽
板をマスクにして行ってもよい。
For example, ion beam irradiation may be performed using a shielding plate with a patterned opening as a mask.

〔作用〕[Effect]

ノボラック樹脂を主体とするポジレジストの除去(剥離
)は02によるケミカルプラズマエツチング等を用いて
行う。この際、側鎖のアジド基から反応が始まり、反応
が進んで最後に生還がくずれて゛ゆくという順序で行わ
れる。
The removal (peeling) of the positive resist mainly composed of novolac resin is performed using chemical plasma etching according to 02 or the like. At this time, the reaction starts from the azide group in the side chain, progresses, and finally the survival collapses.

本発明人は、この側鎖にB、P等をつけた変質層は、上
記の反応が起こり難いという現象を見出し、ポジレジス
トにパターニングされた変質層を形成して現像し、単層
レジストプロセスで、しかも解像度の向上した微細パタ
ーン形成技術を開発した。
The present inventor discovered the phenomenon that the above reaction is difficult to occur in a modified layer in which B, P, etc. are attached to the side chain, and formed a patterned modified layer on a positive resist, developed it, and processed a single layer resist. We have developed a fine pattern formation technology with improved resolution.

この場合の解像度は、遮蔽板の開口精度、さらにはイオ
ンビームによる直接描画の精度によって決まり、従来の
レジストパターニング精度に比し向上する。
The resolution in this case is determined by the aperture accuracy of the shielding plate and the accuracy of direct writing using an ion beam, and is improved compared to conventional resist patterning accuracy.

〔実施例〕〔Example〕

第1図(1)〜(3)は本発明による微細レジストパタ
ーンの形成方法を説明する断面図である。
FIGS. 1(1) to 1(3) are cross-sectional views illustrating a method for forming a fine resist pattern according to the present invention.

第1図(1)において、1は基板で珪素(Si)基板を
用い、この上にポジレジスト2として厚さ1μmの0F
PR(東京応化製)を被着する。
In FIG. 1 (1), 1 is a substrate, and a silicon (Si) substrate is used, and a positive resist 2 with a thickness of 1 μm is applied on this substrate.
Apply PR (manufactured by Tokyo Ohka).

つぎに、パターンを開口した遮蔽板3をマスクして、P
イオン(ヒ)ビームをポジレジスト2上に照射し、注入
する。
Next, mask the shielding plate 3 with the pattern opened, and
An ion beam is irradiated onto the positive resist 2 for implantation.

P1注入条件は、エネルギ60 KeV 、 ドーズ量
3X10”cm−”である。
The P1 implantation conditions are an energy of 60 KeV and a dose of 3×10"cm-".

第1図(2)において、P゛注入より、厚さ0.1μm
程度の変質層4を形成する。
In Figure 1 (2), the thickness is 0.1 μm due to P injection.
A deteriorated layer 4 is formed to a certain extent.

つぎに、0“を用いたダウンフロー型のエツチング装置
により、変質N4の下の領域以外のポジレジスト2を除
去する。
Next, the positive resist 2 other than the area under the altered N4 is removed by a downflow type etching device using 0''.

第1図(3)において、変質層4と同形のポジレジスト
2のパターンが得られる。
In FIG. 1(3), a pattern of the positive resist 2 having the same shape as the altered layer 4 is obtained.

この実施例では、ポジレジスト2の厚さの一部を変質層
4に変換したが、厚さ全体にわたって変換してもよい。
In this example, a part of the thickness of the positive resist 2 is converted into the altered layer 4, but the entire thickness may be converted.

また、イオンの注入角度を変えることにより、レジスト
パターン断面のプロファイルも制御できる可能性もある
Furthermore, by changing the ion implantation angle, it may be possible to control the cross-sectional profile of the resist pattern.

第2図は本発明の実施に使用したダウンフロー型のO“
エツチング装置の断面図である。
Figure 2 shows the downflow type O” used to implement the present invention.
FIG. 3 is a sectional view of the etching device.

図において、21は反応容器、22は排気口、23は酸
素導入口、24は基板ホルダー、25は基板、26、2
7は電極、28は高周波(RF)電源である。
In the figure, 21 is a reaction vessel, 22 is an exhaust port, 23 is an oxygen inlet, 24 is a substrate holder, 25 is a substrate, 26, 2
7 is an electrode, and 28 is a radio frequency (RF) power source.

変質層4を形成した基板25を基板ホルダー24に載せ
、反応容器21を排気口より排気し、酸素導入口23よ
り酸素を導入し、電極26.27間にRF電源28によ
りRF電力を印加して発生した01を基板25上にダウ
ンフローさせてエツチングを行う。
The substrate 25 with the altered layer 4 formed thereon is placed on the substrate holder 24, the reaction vessel 21 is evacuated from the exhaust port, oxygen is introduced from the oxygen introduction port 23, and RF power is applied between the electrodes 26 and 27 by the RF power source 28. Etching is performed by causing the 01 generated during etching to flow down onto the substrate 25.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明による微細パターン形
成技術では、解像度が向上し、0.8μmパターンの形
成は確実に行える。また、工程も単層レジスト技術に通
常のイオン注入を用いるだけで簡単である。
As described above in detail, the fine pattern forming technique according to the present invention improves resolution and can reliably form a 0.8 μm pattern. Furthermore, the process is simple, using single-layer resist technology and ordinary ion implantation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(1)〜(3)は本発明による微細レジストパタ
ーンの形成方法を説明する断面図、 第2図は本発明の実施に使用したダウンフロー型の0*
エツチング装置の断面図である。 図において、 1は基板でSi基板、 2はポジレジストで0FPR(東京応化型)、3はパタ
ーンを開口した遮蔽板、 4はP゛を注入した変質層、 21は反応容器、  22は排気口、 23は酸素導入口、 24は基板ホルダー、25は基板
、    26.27は電極、28はRF電源
Figures 1 (1) to (3) are cross-sectional views explaining the method of forming a fine resist pattern according to the present invention, and Figure 2 is a down-flow type 0* used in implementing the present invention.
FIG. 3 is a sectional view of the etching device. In the figure, 1 is a substrate (Si substrate), 2 is a positive resist (0FPR) (Tokyo Ohka type), 3 is a shielding plate with an opening pattern, 4 is a modified layer injected with P, 21 is a reaction vessel, and 22 is an exhaust port. , 23 is an oxygen inlet, 24 is a substrate holder, 25 is a substrate, 26.27 is an electrode, and 28 is an RF power source.

Claims (1)

【特許請求の範囲】[Claims] 基板上にポジレジストを被着し、該ポジレジスト上のパ
ターン形成領域にイオンビームを照射し、該パターンに
対応した変質層を該ポジレジストに形成し、該変質層が
形成された領域下以外の該ポジレジストを除去すること
を特徴とするパターン形成方法。
A positive resist is deposited on a substrate, a pattern formation area on the positive resist is irradiated with an ion beam, an altered layer corresponding to the pattern is formed on the positive resist, and a layer other than the area under the altered layer is formed. A pattern forming method characterized by removing the positive resist.
JP952186A 1986-01-20 1986-01-20 Formation of pattern Pending JPS62166519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP952186A JPS62166519A (en) 1986-01-20 1986-01-20 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP952186A JPS62166519A (en) 1986-01-20 1986-01-20 Formation of pattern

Publications (1)

Publication Number Publication Date
JPS62166519A true JPS62166519A (en) 1987-07-23

Family

ID=11722569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP952186A Pending JPS62166519A (en) 1986-01-20 1986-01-20 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS62166519A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02241034A (en) * 1989-03-15 1990-09-25 Matsushita Electric Ind Co Ltd Plasma processing equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02241034A (en) * 1989-03-15 1990-09-25 Matsushita Electric Ind Co Ltd Plasma processing equipment

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