CN113808938A - Multiple patterning method - Google Patents
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- CN113808938A CN113808938A CN202010530623.5A CN202010530623A CN113808938A CN 113808938 A CN113808938 A CN 113808938A CN 202010530623 A CN202010530623 A CN 202010530623A CN 113808938 A CN113808938 A CN 113808938A
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- 238000000034 method Methods 0.000 title claims abstract description 62
- 238000000059 patterning Methods 0.000 title abstract description 23
- 230000008569 process Effects 0.000 claims abstract description 41
- 238000005530 etching Methods 0.000 claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000007789 gas Substances 0.000 claims description 28
- 239000002243 precursor Substances 0.000 claims description 18
- 238000010926 purge Methods 0.000 claims description 18
- 238000001179 sorption measurement Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 12
- 239000011261 inert gas Substances 0.000 claims description 11
- 230000004913 activation Effects 0.000 claims description 9
- 238000005086 pumping Methods 0.000 claims description 7
- 229910052736 halogen Inorganic materials 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 150000002367 halogens Chemical class 0.000 claims description 2
- 229910015844 BCl3 Inorganic materials 0.000 claims 1
- 238000007664 blowing Methods 0.000 claims 1
- 238000010408 sweeping Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 12
- 238000001994 activation Methods 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 230000008901 benefit Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000002156 adsorbate Substances 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 2
- BWSIKGOGLDNQBZ-LURJTMIESA-N (2s)-2-(methoxymethyl)pyrrolidin-1-amine Chemical compound COC[C@@H]1CCCN1N BWSIKGOGLDNQBZ-LURJTMIESA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005315 distribution function Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
Abstract
The application relates to a manufacturing method of a semiconductor structure and a multiple patterning method, wherein in the side wall structure manufacturing process of the multiple patterning method, an atomic layer etching process is adopted when a side wall layer is etched, so that the problems of side wall collapse and deformation, size offset and the like are effectively solved.
Description
Technical Field
The application relates to a manufacturing method of a semiconductor device, in particular to a multiple patterning method, and especially relates to an etching method of a side wall in a multiple patterning process.
Background
In a semiconductor manufacturing process, photolithography (photolithography) is a commonly used patterning method. However, the photolithographic process limits the minimum pitch (pitch) of the formed pattern, and thus limits the development of integrated circuits to smaller size and higher density.
Multiple Patterning techniques, including Double Patterning (DPT), quad Patterning (quad Patterning Technology), etc., are one method that enables a lithography process to overcome the resolution limit of lithography. For example, multiple patterning mainly includes two conventional methods: lithography-Etch-lithography-Etch (LELE) and Self-aligned double Patterning (SAMP).
Among them, the self-aligned multi-pattern technology is widely applied in the semiconductor field because of better controllability for the coincidence degree of the patterns. However, the patterns formed by the existing self-aligned multi-pattern technology are easy to deform, and particularly when the side wall is etched, the problem that the side wall has obvious shape collapse is difficult to avoid, and the shape and the depth of the hard mask layer at the lower part of the side wall have size deviation (Pitch Walking) at the two sides of the side wall, so that the accuracy of the etched patterns formed by the subsequent etching target layer is influenced.
Disclosure of Invention
The purpose of the application is realized by the following technical scheme:
in accordance with one or more embodiments, a method of fabricating a semiconductor structure is disclosed, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first hard mask layer;
forming a mandrel pattern and an upper second hard mask layer;
forming a side wall layer;
and etching the side wall layer by adopting an atomic layer etching process to form side walls on two sides of the mandrel.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application, or may be learned by the practice of the embodiments. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1a to fig. 1e are schematic diagrams illustrating a method for manufacturing a sidewall in an embodiment of the present application;
FIGS. 2a to 2d are schematic diagrams of a process of any period before a process of a last period of an atomic layer etching process of a sidewall in an embodiment of the present application;
fig. 3a to fig. 3d are schematic diagrams of the last cycle of the atomic layer etching process of the sidewall in the embodiment of the present application.
Detailed Description
The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. However, the present application is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" and the like include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit of the present application.
Moreover, relative terms, such as "lower" or "bottom" and "upper" or "top," are used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the lower side of another element would then be turned over to be on the upper side of the other element. The exemplary term "lower" therefore includes both "lower" and "upper" directions, depending on the particular orientation of the figure. Likewise, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented above the other elements. Thus, the exemplary term "below" or "beneath.
Embodiments of the present application are described herein with reference to cross-sectional (and/or plan) views that schematically illustrate idealized embodiments of the present application. Likewise, deviations from the schematic shape due to, for example, manufacturing processes and/or tolerances, can be expected. Thus, embodiments of the present application are not to be considered as limiting the particular shapes of regions illustrated herein, but to include deviations in shapes that result, for example, from manufacturing. For example, etched areas illustrated or described as rectangles typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present application.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It will be understood by those skilled in the art that references to a structural or functional component disposed adjacent to another component may have portions that overlap or underlie the other component.
The present application discloses a method for fabricating a semiconductor structure, which can be applied to any suitable multiple patterning method, such as a dual patterning method, a quad patterning method, etc., and is not limited to the multiple patterning method, as long as the spacers are formed and utilized therein, and thus can be applied to the fabrication method disclosed herein. In the following embodiments, a method for forming a sidewall structure in a double patterning manufacturing method is taken as an example, but as mentioned above, the present application is not limited thereto, and in one of the embodiments of the present application, a specific sidewall structure manufacturing process is as follows:
as shown in fig. 1a, in the present embodiment, a semiconductor substrate 100 may be provided, and the semiconductor substrate 100 may have a first mask layer 200, for example. The semiconductor substrate 100 may be any suitable substrate, such as a substrate of Si, SiGe, or the like, or a semiconductor substrate including circuit elements of mos (metal Oxide semiconductor) transistors, in which functional components (not shown) such as gates, source/drains, bit lines, and the like are formed on the semiconductor substrate. In this embodiment, the material of the first hard mask layer 200 may be selected from commonly used mask materials such as silicon oxynitride (SiON).
Subsequently, a sacrificial layer 300 may be provided on the surface of the first hard mask layer 200, wherein the sacrificial layer may be used to form a Mandrel (Mandrel) which may be used to support the function of depositing sidewall layers, and typically, the sacrificial layer may be selected from a material such as Spin-on Carbon (SOC). Subsequently, a second hard mask layer 400 may be provided on the surface of the sacrificial layer 300. The second hard mask layer 400 in this embodiment may use a commonly used mask material such as silicon oxynitride (SiON).
As shown in fig. 1b, a surface of the sacrificial layer 300 may then be exposed by patterning the second hard mask layer 400 to remove portions of the second hard mask layer 400, the exposed surface of the sacrificial layer 300 corresponding in location to where the mandrels are to be formed.
As shown in fig. 1c, the sacrificial layer 300 may then be etched to pattern the mandrel 500 and cover the second hard mask layer 400 over the mandrel.
As shown in fig. 1d, sidewall layers 600 may then be formed on the sidewall surfaces of the mandrel 500, on top of the remaining second hard mask layer 400, and on the first hard mask layer 200. The sidewall layer 600 may be formed, for example, by an existing Atomic Layer Deposition (ALD) process. The material of the sidewall layer may be, for example, titanium oxide (TiO)2)。
As shown in fig. 1e, the sidewall layer 600 may be etched to form a sidewall spacer 700, and the surfaces of the first hard mask layer 200 and the second hard mask layer 400 are exposed. Based on a common sidewall layer etching method, in this embodiment, an anisotropic dry etching process may be used to etch the sidewall layer 600, where the anisotropic etching mainly refers to etching the sidewall layer 600 in a vertical direction without performing etching in a horizontal direction, so that sidewalls 700 that are vertically and independently located at two sides of the mandrel 500 at an interval can be formed, and surfaces of the first hard mask layer 200 and the second hard mask layer 400 are exposed.
Different from the process in the prior art, the Atomic Layer Etching process (ALE) may be adopted for Etching the sidewall Layer in the embodiment of the present application, and specifically, as shown in fig. 2, the Atomic Layer Etching process in the embodiment of the present application may include the following steps:
first, as shown in fig. 2a, a precursor adsorption step may be performed, and in the present embodiment, titanium oxide may be used as the material for the sidewall layer, and boron trichloride (BCl) may be used3) Precursor gas of equal boron-containing halogen gas and N2Inert gases such as He and/or Ar are supplied into the etch chamber and pulses of RF power may be applied to generate a plasma to adsorb a precursor adsorbed film layer on the surface of the sidewall layer. In other alternatives, for example, the material of the sidewall layer may be silicon oxide, and in this case, the material containing C may be usedxFyAnd N2An inert gas such as He and/or Ar is supplied to the process chamber and a pulse of RF power can be applied to generate a plasma to adsorb a precursor adsorbed film layer on the surface of the sidewall layer. In other alternatives, for example, the material of the sidewall layer may also be silicon nitride, and in this case, the material containing C may be usedxHyFzAnd N2Inert gases such as He and/or Ar are supplied to the process chamber and pulses of RF power may be applied to generate plasma to adsorb the precursor adsorption film layer on the surface of the sidewall layer. Different precursor gases can be supplied for different side wall material layers, and the precursor adsorption film layer can be better formed on the surface of the side wall material layer by matching with the RF power pulse with corresponding frequency, so that subsequent activation etching is facilitated. In the present embodiment, the treatment time in the precursor adsorption step may be within 10 seconds.
Subsequently, as shown in fig. 2b, a post-adsorption purge process may be performed, and in this embodiment, after the adsorption process, a purge gas may be supplied through the pumping valve at a predetermined opening degree, and then the purge gas may be withdrawn through the pumping valve, and when the purge gas is withdrawn, the state of the pumping valve may be set to a fully opened opening degree to sufficiently withdraw the precursor gas out of the etching chamber along with the purge gas as much as possible. In the present embodiment, the purge gas may be Ar gas. In the present embodiment, the treatment time in the post-adsorption purging step may be within 10 seconds.
Subsequently, as shown in FIG. 2c, an activation step may be performed, and in the present embodiment, the activation step may be to supply N2Inert gases such as He and/or Ar to the etch chamber and applying a Low Bias (Low Bias) power RF power pulse to generate N2And He and/or Ar, to activate the precursor adsorbate, and then to perform a chemical reaction to etch the sidewall layer. In other alternatives, N is supplied2And a reactive gas may be added to the inert gas such as He and/or Ar, for example, oxygen may be added, and the reactive gas such as oxygen may directly participate in the chemical reaction in the subsequent activation reaction to facilitate etching. In the present embodiment, the treatment time in the activation step may be within 10 seconds.
Subsequently, as shown in fig. 2d, a post-activation purge process may be performed, and in this embodiment, after the activation process, a purge gas may be supplied through the pumping valve at a predetermined opening degree, and then the purge gas may be withdrawn through the pumping valve, and when the purge gas is withdrawn, the state of the pumping valve may be set to a fully opened opening degree to sufficiently withdraw the activated etching reaction products of the precursor adsorbate out of the etching chamber with the purge gas as much as possible. In the present embodiment, the purge gas may be Ar gas. In the present embodiment, the treatment time in the post-adsorption purging step may be within 10 seconds.
As shown in fig. 2a to 2d, the atomic layer etching process of one cycle in this embodiment is completed, that is, the etching of one atomic layer is completed. In the present embodiment, the above-mentioned process conditions of only one cycle are described, and in an actual process, the above-mentioned processes may be repeated for more than one cycle, specifically, the cycle number of the atomic layer etching process is set according to the requirement of the etching thickness on the sidewall layer, for example, the above-mentioned processes of 1-100 cycles may be repeated according to the requirement of the etching thickness until the sidewall layer with a specified thickness is etched, the sidewall layer in the horizontal direction is etched to expose the surfaces of the first and second mask layers, and finally, the sidewall structures on both sides of the mandrel are formed, as shown in fig. 3 a-3 d, that is, the schematic diagram of the etching process in the last cycle in the present embodiment.
Through the implementation mode of the application, even if can also implement the atomic layer etching process on 300 mm's equipment, and adopt the atomic layer etching process, weak ion energy also can make the surface of treating the sculpture easily to react and by effective sculpture, consequently, can take place even atomic level's sculpture, in order to guarantee that the lateral wall layer is by even, equal thickness ground is etched and is got rid of in the horizontal direction, can avoid the fillet to appear in the at utmost like this, also avoided the first mask layer between the lateral wall to be undesirably etched and cause the height of the first mask layer of lateral wall both sides to produce the difference. In the conventional Reactive Ion Etching (RIE) process, due to Ion Energy dispersion generated during the Etching process, thermal tail ions (hot tail ions) with high-Energy Ion Energy Distribution Functions (IEDF) make the shape of the head of the sidewall difficult to avoid forming a fillet, thereby increasing the density of incident ions between adjacent sidewalls and generating more Etching between the sidewalls, so that the sidewall layer at the bottom between the sidewalls is etched before the sidewall at the top of the sidewalls to expose the surface of the first mask layer, thereby causing undesirable Etching.
The above processes in the embodiment of the application and the processes for preparing the side wall structure in the existing multiple patterning manufacturing method mainly adopt the atomic layer etching process to etch the side wall layer, and other processes are not obviously different and can adopt other conventional alternative modes for processing.
In addition to the above embodiments, the manufacturing method of the present application is also applicable to other multiple patterning methods such as quad patterning, etc. to solve the technical problems of side wall collapse deformation, size deviation (Pitch Walking), etc. that are easily generated in the process of manufacturing the side wall structure.
The present application may be used for fine stripe etching in logic device or memory, such as DRAM fabrication.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (9)
1. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first hard mask layer;
forming a mandrel pattern and an upper second hard mask layer;
forming a side wall layer;
and etching the side wall layer by adopting an atomic layer etching process to form side walls on two sides of the mandrel.
2. The manufacturing method according to claim 1, characterized in that:
the atomic layer etching process comprises the following steps of,
a precursor adsorption step;
a post-adsorption blowing process;
an activation step;
a blowing-sweeping process after the activation,
and repeating the above steps for more than one time.
3. The manufacturing method according to claim 2, characterized in that:
repeating the above steps for 1-100 times.
4. The manufacturing method according to any one of claims 2 to 3, characterized in that:
in the precursor adsorption step, a precursor gas containing a boron-containing halogen gas and an inert gas are supplied to a processing chamber; further, the boron-halogen-containing gas comprises BCl3The inert gas contains N2And Ar and He, or a combination of two or more thereof.
5. The manufacturing method according to any one of claims 2 to 3, characterized in that:
in the precursor adsorption step, C is includedxFyThe precursor gas and the inert gas of (a) are supplied to the process chamber; further, the inert gas contains N2And Ar and He, or a combination of two or more thereof.
6. The manufacturing method according to any one of claims 2 to 3, characterized in that:
in the precursor adsorption step, C is includedxHyFzThe precursor gas and the inert gas of (a) are supplied to the process chamber; further, the inert gas contains N2And Ar and He, or a combination of two or more thereof.
7. The manufacturing method according to any one of claims 2 to 3, characterized in that:
the post-adsorption purge step and/or the post-activation purge step may include,
supplying a purge gas;
and in the state that the pumping valve is fully opened, the purging gas is extracted.
8. The manufacturing method according to any one of claims 2 to 3, characterized in that:
in the activation step, a reactive gas is added to the activation treatment gas; further, the reactive gas comprises O2。
9. The manufacturing method according to any one of claims 2 to 3, characterized in that:
the processing time of each step is within 10 seconds.
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| US20080070165A1 (en) * | 2006-09-14 | 2008-03-20 | Mark Fischer | Efficient pitch multiplication process |
| US20100075503A1 (en) * | 2008-09-19 | 2010-03-25 | Applied Materials, Inc. | Integral patterning of large features along with array using spacer mask patterning process flow |
| US20130143372A1 (en) * | 2011-12-06 | 2013-06-06 | Samsung Electronics Co., Ltd. | Methods of forming patterns of a semiconductor device |
| US20170236719A1 (en) * | 2016-02-12 | 2017-08-17 | Tokyo Electron Limited | Method and apparatus for multi-film deposition and etching in a batch processing system |
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2020
- 2020-06-11 CN CN202010530623.5A patent/CN113808938A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080070165A1 (en) * | 2006-09-14 | 2008-03-20 | Mark Fischer | Efficient pitch multiplication process |
| US20100075503A1 (en) * | 2008-09-19 | 2010-03-25 | Applied Materials, Inc. | Integral patterning of large features along with array using spacer mask patterning process flow |
| US20130143372A1 (en) * | 2011-12-06 | 2013-06-06 | Samsung Electronics Co., Ltd. | Methods of forming patterns of a semiconductor device |
| US20170236719A1 (en) * | 2016-02-12 | 2017-08-17 | Tokyo Electron Limited | Method and apparatus for multi-film deposition and etching in a batch processing system |
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