JPS5940574A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPS5940574A JPS5940574A JP15220682A JP15220682A JPS5940574A JP S5940574 A JPS5940574 A JP S5940574A JP 15220682 A JP15220682 A JP 15220682A JP 15220682 A JP15220682 A JP 15220682A JP S5940574 A JPS5940574 A JP S5940574A
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor substrate
- substrate
- recess
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052759 nickel Inorganic materials 0.000 abstract description 6
- 238000007747 plating Methods 0.000 abstract description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 abstract description 2
- 229910017604 nitric acid Inorganic materials 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000011259 mixed solution Substances 0.000 abstract 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【発明の詳細な説明】
この発明はパワートランジスタなどの電力用の半導体素
子に係り、特にその半導体基板の熱抵抗゛に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to power semiconductor devices such as power transistors, and particularly to thermal resistance of semiconductor substrates thereof.
以下 パワートランジスタを例にとり説明する。A description will be given below using a power transistor as an example.
パワートランジスタでは、その性能を規制する畏累の一
つに、半導体基板のｐｎ接合部を通って流れるコレクタ
電流によって発生する熱を半導体基板からこれがろう付
けされたパンケージの金属板を通して外部へ放散させる
径路における熱抵抗がある。この熱抵抗が大きい場合に
は、半導体基板のｐｎ接合部に発生する熱によるｐＨ接
−８部の温度上昇が大きくなるので、許容コレクタ電流
が規制される。従って、従来のパワートジンジスタでは
、熱抵抗を小さくするだめの改良がパッケージの金属板
については種々行わｊｔでいる。しかし、半導体基板に
ついてはほとんど行われていない。In a power transistor, one of the factors that regulates its performance is to dissipate the heat generated by the collector current flowing through the pn junction of the semiconductor substrate from the semiconductor substrate to the outside through the metal plate of the pancage to which it is brazed. There is thermal resistance in the path. If this thermal resistance is large, the temperature rise at the pH junction section due to the heat generated at the pn junction section of the semiconductor substrate becomes large, so that the allowable collector current is regulated. Therefore, in the conventional power transistor, various improvements have been made to the metal plate of the package to reduce the thermal resistance. However, this has hardly been done for semiconductor substrates.
その理由は、半導体基板の熱伝導率が・）λ端板の熱体
２！ト率よシ小でい（例えばシリコンの熱伝導率は１．
１３ Ｗ ｃ ｍ ・°Ｃ、金の熱伝導率（ｌま３．
コＯ〜Ｖｅｎｔ ＋＋”Ｃである）ので、半導体基板
の厚？を薄くすればする程、熱抵抗を小ざくすることが
できるが、その反面学導体基板が破損しやすくなり、そ
の取扱いが困難になる。従って、半導体基板の厚では１
００〜３００μｍ以下にはできなかつグζ。The reason is that the thermal conductivity of the semiconductor substrate is...) Thermal body 2 of the λ end plate! (For example, the thermal conductivity of silicon is 1.
13 W cm ·°C, thermal conductivity of gold (l ~ 3.
Therefore, the thinner the semiconductor substrate is, the smaller the thermal resistance can be, but on the other hand, the conductor substrate is more likely to be damaged and difficult to handle. Therefore, the thickness of the semiconductor substrate is 1
It cannot be made smaller than 00 to 300 μm.
この発明は、上述の点に鑑シ、てなされたもので、半導
体基板の取扱いを困難にすることなく、半導体基板の熱
抵抗を小さくすることができるよう如した半導体素子を
提供することを目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor element that can reduce the thermal resistance of a semiconductor substrate without making handling of the semiconductor substrate difficult. shall be.
第１図はこの発明の一実施例のパワートランジスタを示
す断面図である。FIG. 1 is a sectional view showing a power transistor according to an embodiment of the present invention.
図において、（１）はコレクタ領域を構成する第１伝導
形の半導体基板、（２）は半導体基板（１）の第１の主
面部の一部に形成された第２伝導形のペース領域、（３
）はベース領域（２）の表面部の一部に形成された第１
伝導形のエミッタ領域、（４）は半導体基板（１）。In the figure, (1) is a semiconductor substrate of a first conductivity type constituting a collector region, (2) is a pace region of a second conductivity type formed in a part of the first main surface of the semiconductor substrate (1), (3
) is a first region formed on a part of the surface of the base region (2).
A conductive emitter region (4) is a semiconductor substrate (1).
ベース領域（２）およびエミッタ領域（３）の各表面上
にわたって形成された二酸化ケイ素（ｓ１０２）膜、（
５）はＳｉＯ２膜（４〕のベース領域（２）の表面上の
部分に選択［ＲＪに形成された開口部を通してベース領
域（２）にオーミンク接続されたペース電極、（６）は
５１ｏ２膜（４）のエミッタ領域（３）の表面上の部分
に選択的に形成されたし１１口部を通してエミッタ領域
（３）にオーミック接続されたエミッタ電極、（７）は
半導体基板（１）の第２の主面中央部に１例えばフン化
水素醒２ｏ係・硝酸５０チ・酢酸３０条（厘量比）のエ
ンチング液を用いた選択エツチングによってベース領域
（２）に達しないように形成された凹部、（８）は凹部
（７）を埋めるよ′）Ｋ１例えばブルーシューマー（日
本刀＝ センＫＫ社商品名）による無電解ニッケルメッ
キ法およびテンペレックス４０１（ｂＪ木エレクトロブ
レーテイングエンジニアスｘＪ１曲品名）による金メツ
キ法によって順次形成きれたニッケル層と金層とから々
る金属層、一点鎖線で示す（９）は半導体基板（１）の
第２の主面および金属層（８）の表面がろう付けされる
パッケージの金属板である。A silicon dioxide (S102) film formed over each surface of the base region (2) and emitter region (3), (
5) is selected on the surface of the base region (2) of the SiO2 film (4) [the pace electrode is ohmink connected to the base region (2) through the opening formed in the RJ, (6) is the 51o2 film ( 4) an emitter electrode selectively formed on the surface of the emitter region (3) and ohmically connected to the emitter region (3) through the opening 1; A recess is formed in the central part of the main surface of the etching layer by selective etching using an etching solution containing, for example, 2 parts of hydrogen fluoride, 50 parts of nitric acid, and 30 parts of acetic acid (in volume ratio) so as not to reach the base region (2). , (8) fills the recess (7)') K1 For example, the electroless nickel plating method by Blue Schumer (Japanese sword = Sen KK company product name) and Temperex 401 (bJ Wood Electroblating Engineers x J1 song product name) A metal layer consisting of a nickel layer and a gold layer successively formed by the gold plating method, (9) indicated by a dashed dotted line shows that the second main surface of the semiconductor substrate (1) and the surface of the metal layer (8) are waxed. This is the metal plate of the package that is attached.
このように構成されたこの実施例では、半導体基板（１
）の周縁部の厚さが厚く、かつ第２の主面中央部に金属
層（８）が設けであるので、半導体基板（１）に所要の
機械的強度をもたせることができ、半導体基板（１）の
取扱いが内部になることがない。しかも、凹部（７）内
に半導体基板（１）の熱伝導率より大きい熱伝導率を有
する金属層（８）が形成芒れているので、熱発生源であ
るｐｎ接合部から金属ＰＩ（８）を通ってパック゛−ジ
の金属板（９）に達する径路における熱抵抗を小さくす
ることができる。In this embodiment configured in this way, a semiconductor substrate (1
) is thick at the peripheral edge, and the metal layer (8) is provided at the center of the second main surface, so the semiconductor substrate (1) can have the required mechanical strength, and the semiconductor substrate ( 1) will not be handled internally. Moreover, since a metal layer (8) having a thermal conductivity higher than that of the semiconductor substrate (1) is formed in the recess (7), the metal layer (8) is formed from the pn junction, which is a heat generation source, to the metal PI (8). ) to reach the metal plate (9) of the package.
第２図はこの発明の他の実施例のパワートランジスタを
示す断面図である。FIG. 2 is a sectional view showing a power transistor according to another embodiment of the invention.
図において、第１図に示した実施例の符号と同一符号は
同等部分を示す。（８ａ）は金およびニッケルからなり
凹部（７）を埋め半導体基板（１）の主面を被覆するよ
うにメッキ法、蒸着法、スパッタリング法などのメタラ
イゼーションによって形成された金属層である。In the figure, the same reference numerals as those in the embodiment shown in FIG. 1 indicate equivalent parts. (8a) is a metal layer made of gold and nickel and formed by metallization such as plating, vapor deposition, or sputtering so as to fill the recess (7) and cover the main surface of the semiconductor substrate (1).
この実施例においても、第１図に示した￥流側と同様の
効果がある。This embodiment also has the same effect as the flow side shown in FIG.
上記各実施例では、金およびニッケルからなる金属層（
８） 、 （８ａ）を用いたが、必ずしもこれは金およ
び、ニッケルに限定する必要はなく、チタン、銀。In each of the above embodiments, the metal layer consisting of gold and nickel (
8), (8a) was used, but it is not necessarily limited to gold and nickel, but titanium and silver.
白金などのその他の金属からなる金属層を用いてもよい
。Metal layers made of other metals such as platinum may also be used.
なお、これまで、パワートランジスタを例にと９述べた
が、この発明はこれに限らず、電界効果形トランジスタ
などのその半導体素子にも適用することができる。Although the present invention has been described above using a power transistor as an example, the present invention is not limited to this, but can also be applied to such semiconductor elements such as field effect transistors.
以上、説明したように、この発明の半導体素子では、一
方の主面部に機能領域が形成され他方の主面中央１１１
５に上記機能領域に達しなり深さの凹部が形成された半
導体基板と、少なくとも上記凹部を埋めるように形成き
れた金属層とを備えているので、上記半導体基板の厚さ
の厚い周縁部と上記金属層とによって上記半導体基板に
所要の機械強度をもだせることができ、上記半導体基板
の取扱いが困難になることがない。（〜かも、上記半導
体基板の熱伝導率より大きい熱伝導率を有する上記金属
層が形成されているので、上記半導体基板に発生する熱
を外部へ放散ζせる径路の゛熱抵抗を小さくすることが
できる。As described above, in the semiconductor device of the present invention, a functional region is formed on one main surface, and a functional region is formed in the center 111 of the other main surface.
5 includes a semiconductor substrate in which a recess is formed with a depth that reaches the functional area, and a metal layer that has been formed to fill at least the recess, so that the thick peripheral portion of the semiconductor substrate and The metal layer can provide the semiconductor substrate with the required mechanical strength, and the semiconductor substrate does not become difficult to handle. (Maybe, since the metal layer is formed with a thermal conductivity higher than that of the semiconductor substrate, the thermal resistance of the path for dissipating the heat generated in the semiconductor substrate to the outside can be reduced. Can be done.
第１図および第２図はそれぞれこの発明の一実施例およ
び他の実施例を示す断面図である。
図において、（１）は半導体基板、（２）および（３）
はそれぞれベース領域およびエミッタ領域（機能領域）
、（７）は四部、（３）および（８ａ）は金属層である
。
なお、図中同一符号はそれぞれ同一または相当部分を示
す。
代理人 為野信−（外１名）
５、補正の対象
明細書の発明の詳細な説明の欄
６、補正の内容
（１） 明細淋の第２頁第１１行にｒ ］、、 １３
Ｗｃｍ ・’ＣＪとあるのｆ ｒｌ、１３Ｗ＊ｃｍ−
’ｅｄｅｇ−１Ｊと訂正する。
（２） 同、第２頁第１１行にｒ３．１０Ｗｃｍ−’
ｓ°ｃ−’Ｊとあるのｆ ｒ３．１０Ｗ＊ｃｍ−’ａｄ
θｇ−１」と訂正する０以上FIG. 1 and FIG. 2 are cross-sectional views showing one embodiment and another embodiment of the present invention, respectively. In the figure, (1) is a semiconductor substrate, (2) and (3)
are the base region and emitter region (functional region), respectively.
, (7) are four parts, (3) and (8a) are metal layers. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Tameno (1 other person) 5. Column 6 for detailed explanation of the invention in the specification to be amended, Contents of the amendment (1) R on page 2, line 11 of the specification.], 13
Wcm ・'CJ and Aru no f rl, 13W*cm-
Corrected to 'edeg-1J. (2) Same, page 2, line 11 r3.10Wcm-'
s°c-'J and f r3.10W*cm-'ad
0 or more corrected as “θg−1”
Claims (1)
央部に上記機能領域に達しない深さの凹部が形成された
半導体基板、および少なくとも上記凹部を埋めるように
形成された金属層を備え、上記半導体基板に発生する熱
を外部へ放散させる径路の熱抵抗が小さくなるようにし
たことを特徴とする半導体素子。(1) A semiconductor substrate in which a functional region is formed on one main surface and a recess with a depth that does not reach the functional region in the center of the other main surface, and a metal layer formed to fill at least the recess. What is claimed is: 1. A semiconductor device characterized in that the thermal resistance of a path through which heat generated in the semiconductor substrate is dissipated to the outside is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15220682A JPS5940574A (en) | 1982-08-30 | 1982-08-30 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15220682A JPS5940574A (en) | 1982-08-30 | 1982-08-30 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5940574A true JPS5940574A (en) | 1984-03-06 |
Family
ID=15535380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15220682A Pending JPS5940574A (en) | 1982-08-30 | 1982-08-30 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5940574A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000040825A (en) * | 1998-06-30 | 2000-02-08 | Harris Corp | Semiconductor device having reduced effective resistivity of substrate and manufacture thereof |
| US7504707B2 (en) | 2003-06-05 | 2009-03-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS561566A (en) * | 1979-06-19 | 1981-01-09 | Nec Corp | Semiconductor element |
-
1982
- 1982-08-30 JP JP15220682A patent/JPS5940574A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS561566A (en) * | 1979-06-19 | 1981-01-09 | Nec Corp | Semiconductor element |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000040825A (en) * | 1998-06-30 | 2000-02-08 | Harris Corp | Semiconductor device having reduced effective resistivity of substrate and manufacture thereof |
| US7504707B2 (en) | 2003-06-05 | 2009-03-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
| US7629226B2 (en) | 2003-06-05 | 2009-12-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
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