JPS5939911B2 - Manufacturing method of PN junction element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a PN junction element, and in particular,
The present invention relates to a method for forming a high breakdown voltage PN junction between a single crystal silicon layer and a polycrystalline silicon layer.

The PN junction plays an important role in semiconductor devices, and it can be said that the characteristics of the device or element are influenced by the PN junction.

When a voltage in the opposite direction is applied to this PN junction, only a small amount of saturation current flows, but when a certain voltage is exceeded, the current suddenly begins to flow.

This phenomenon is called breakdown or breakdown, and this voltage is called breakdown voltage or breakdown voltage. If a voltage higher than the breakdown voltage is applied, the PN junction will be mechanically destroyed. Therefore, the characteristics of a semiconductor device are determined by this breakdown voltage. The causes of the above-mentioned breakdown include those caused by excessive current density and those caused by current concentration occurring locally in the junction. Therefore, if such causes of breakdown are eliminated, the breakdown voltage of the semiconductor device can be increased, which is especially advantageous for devices that use large currents. Conventionally, it has been considered to increase the breakdown voltage by adjusting the conductivity of the PN junction or improving the shape of the PN junction. The present invention provides P as described above.
The purpose is to increase the breakdown voltage of the N junction and obtain a PN junction with high breakdown voltage. In the method for manufacturing a PN junction element according to the present invention, the above object is achieved by improving the shape of the PN junction, increasing the area of the junction, and preventing current from being concentrated in one part. It is something.

In the method of manufacturing a PN junction device according to the present invention, not only a layer of single crystal silicon but also a layer of polycrystalline silicon is used,
It is characterized by forming a PN junction therein. The present invention provides a method suitable for use in a semiconductor integrated circuit device using dielectric isolation technology used to obtain a high breakdown voltage element. The diffusion coefficients of single crystal silicon and polycrystalline silicon are significantly different, with polycrystalline silicon being about an order of magnitude larger.

This can be expressed in a table as follows. The unit is c7il/
sec By utilizing this difference in diffusion coefficient and the structure of the boundary between single crystal silicon and polycrystalline silicon, a PN junction with a large area can be obtained.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a front sectional view showing the steps of an embodiment of the present invention.

Silicon dioxide film 11 on the surface of single crystal silicon substrate 10
(A). In this case, the single crystal silicon substrate 10
has N-type conductivity. A portion of the silicon dioxide film 11 is removed according to a pattern to form a V-shaped groove (B). As a result, the surface of the single-crystal silicon substrate 10 in the portion where the letter-shaped groove is to be formed is exposed. The crystal axis is selected so that this surface is, for example, a (100) plane.
When this is etched using the silicon dioxide film 11 as a mask, a V-shaped groove 12 is formed on the surface of the single crystal silicon substrate 10 due to the anisotropy of the etching (CL(
100), the angle of the groove 12 of the letter is 721
becomes. Next, on this surface including this V-shaped groove 12,
In this case, a polycrystalline silicon layer 13 having N-type conductivity
form a)). At this time, no silicon dioxide film is formed on the surface of the single crystal silicon substrate 10 in the V-shaped groove 12, and the polycrystalline silicon layer 13 comes into direct contact with the surface. For this purpose, it is necessary to grow crystals at low temperatures. Once polycrystalline silicon is formed in the base layer, a polycrystalline silicon layer can be formed even if it is grown at a high temperature thereafter. After the polycrystalline silicon layer 13 is formed to a thickness sufficient to support the single-crystal silicon substrate 10, the amount of polishing (g) for polishing the single-crystal silicon substrate 10 is as follows:
This is done until the bottom of the V-shaped groove 12 appears or is close to it. A silicon dioxide film 14 is formed on the surface of a single crystal silicon substrate 10, and a V-shaped groove 12 is formed.
Using this as a diffusion window, a P-type impurity, such as boron, is diffused into the single crystal silicon substrate 10 and the polycrystalline silicon layer 13 (QO). Thus, a PN junction 15 is formed between the single crystal silicon substrate 10 and the polycrystalline silicon layer 13.
As mentioned above, single crystal silicon and polycrystalline silicon have significantly different diffusion rates.

Therefore, when the P-type impurity is diffused through the above process, it will be diffused slowly in the single crystal silicon substrate and quickly in the polycrystalline silicon layer. Since the diffusion occurs from the bottom side of the V-shaped groove, the depth of diffusion in the direction perpendicular to the surface increases in the polycrystalline silicon layer on the bottom of the V-shaped groove, and gradually decreases as the distance from there increases. Become. Diffusion in single-crystal silicon is much smaller than in polycrystalline silicon. The PN junction thus formed has a rounded shape within the polycrystalline silicon layer.

Therefore, the area becomes larger and there is no part in the shape where the current is concentrated. Second
The figure shows a front sectional view of an example in which a PN junction element manufactured according to the present invention is formed in the same substrate as other semiconductor integrated circuit elements.

Single crystal silicon island 20 formed by dielectric separation
An NPN transistor is formed therein, and a diode is formed using another island 30 and a polycrystalline silicon layer 23. As described above, the present invention is particularly suitable when using dielectric isolation technology, and the PN junction element can be formed simultaneously when other elements are formed. Moreover, FIG. 3 shows a front sectional view of another example of a PN junction element manufactured according to the present invention.

The P-type impurity is diffused while the polycrystalline silicon layer 33 is exposed, and the shape of the PN junction is similar to the above example. It's summery. In this way, by changing the amount of polishing of single crystal silicon, the shape of the PN junction can also be changed. According to the present invention, since the shape of the PN junction can be arbitrarily obtained, the breakdown voltage of the PN junction can be arbitrarily controlled.

In particular, since the area of the PN junction can be large, it is suitable for high-voltage elements. In addition, it can be used not only for diodes but also for forming other active elements or resistors, and it can also be used to form P
There is also the advantage that an N-junction element can be formed.

[Brief explanation of drawings]

Figure 1 is a front sectional view showing the process of the present invention, Figures 2 and 3.
The figure is a front sectional view of an example of a PN junction element manufactured according to the present invention. 10,20,30... Single crystal silicon, 13,
23,33...polycrystalline silicon, 12...
. . . shaped groove, 11, 14 . . . silicon dioxide film, 15 . . . PN junction.

Claims (1)

[Claims] 1 A V-shaped groove is formed on one surface of a single-crystal silicon substrate of one conductivity type, a silicon dioxide film is formed on a surface other than the surface of the V-shaped groove, and a silicon dioxide film is formed on the surface of the V-shaped groove and the silicon dioxide film. After forming a polycrystalline silicon layer on the surface of the single-crystal silicon substrate and polishing the single-crystal silicon substrate, impurities of the opposite conductivity type are added to the portion of the single-crystal silicon substrate where the V-shaped groove is formed from the single-crystal silicon substrate side. A method for manufacturing a PN junction element, comprising diffusing into the single crystal silicon substrate and the polycrystalline silicon layer.