JPH0653313A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent facetting and crystal defects by selectively growing a silicon single-crystal film inside a slit in an insulating film pattern on a silicon substrate within a specified temperature range and thereafter flattening the single-crystal film. CONSTITUTION:An N<+> buried layer 4 as well as a 1.5mum thickness isolation insulating oxide film pattern 2 having a slit are formed on a p-type silicon substrate 1. Inside the slit is then cleaned, and an n type silicon single-crystal film 3 is selectively grown there to, for example, 3mum in thickness so that its surface is higher than that of the oxide film 2. The substrate 1 is polished under a pressure of 100g/cm<2> by a polyurethane polishing pad soaked with solution containing ethylenediamenepyrocatechol and fine powder of silica, and the single-crystal silicon film 3, including a facet, above the isolation oxide film 2 is shaved. Subsequently, a p type base region 6, n type emitter region 7 and polycrystalline silicon electrode are formed to obtain an n-p-n transistor of so-called walled base structure wherein the base region 6 having a very small cb junction leakage current is in contact with the oxide film 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for selective epitaxial growth of a single crystal silicon film.

[0002]

2. Description of the Related Art Conventionally, for manufacturing a semiconductor device having a dielectric isolation region by using a selective epitaxial growth method, for example, an academic journal "An International Journal of Semiconducer Manufacturing Technology (An. International
Journal of SemiconductorM
anufacturing Technology, V
olume 4, No. 1 May 1986, PP3 ~
33) ”, the single crystal silicon film has a temperature of 9
Selective growth is performed under the condition of 50 ° C. or higher.

FIG. 5 shows a cross-sectional view of an N-type single crystal silicon film manufactured by a conventional selective epitaxial method. That is, the N-type single crystal silicon film 3 is the P-type silicon substrate 1
A film having the same thickness as the insulating film is deposited so as to fill the opening of the insulating film pattern 2 formed above.

[0004]

However, in the above-described conventional method for manufacturing a semiconductor device, many crystal defects are generated in the vicinity of the isolation insulating oxide film of the single crystal silicon film selectively epitaxially grown, or the growth film is grown. Since different crystal planes, that is, facets 5 are formed at the corners of the pits, a step is formed, so that the PN is contacted with the isolation insulating oxide film.
When a junction is formed, the leak current of this junction increases. Here, this state will be specifically described with reference to the drawings.

The diagrams (a) and (b) of FIG.
A plan view and a cross-sectional view taken along line AA ′ of the base region of the NPN transistor formed on the type single crystal silicon film are shown. That is, on the surface of the P-type silicon substrate 1, arsenic (A
s) is implanted to form an N ⁺ buried layer 4, and this surface is selectively oxidized to form an insulating film pattern 2 of 1.5 μm. Next, after performing an appropriate pretreatment, so-called selective epitaxial growth is performed on this surface, in which silicon is not deposited on the insulating film but silicon is deposited only on the exposed surface of the silicon substrate.

The typical conventional growth conditions are as follows.

[0007]

[Table 1]

Under the above conditions, phosphine gas (P
H ₃ ) is grown with appropriate addition, the resistivity of 0.
The 8 Ωcm N-type single crystal silicon film 3 is epitaxially grown. Then, boron (B) is ion-implanted into the surface of the epitaxial layer to perform activation heat treatment, and an area of 15
A P-type base region 6 having a size of μm × 19 μm and a depth of 0.4 μm was formed. Then, electrodes are drawn out from the P-type base region 6 and the N-type single crystal silicon film 3 to serve as a collector, and a reverse bias voltage of 10 V is applied to the electrodes to reverse the collector / base junction (hereinafter referred to as CB junction). When the characteristics were examined, it was confirmed that the leak current of the junction sharply increased when the distance x (μm) between the junction and the insulating film was smaller than 1.5 μm. That is, as the junction is formed in the vicinity of the insulating film, the leak current is from 10 ⁻¹⁴ to 10
^{-Experimental} results have revealed that the number will increase by more than two digits to ¹² units. Further analysis of the experimental results shows that the temperature of 100
Although the growth of facets is suppressed to a very low level in the single crystal silicon film grown at 0 ° C., many crystal defects are generated in the vicinity of the isolation insulating oxide film 2, and the CB junction is separated with many crystal defects. It became clear that the leak current drastically increases when the vicinity of the insulating oxide film 2 is approached.
It has been found that when the growth temperature is lowered to 900 ° C., for example, the degree of facet growth is increased instead of the reduction of crystal defects. That is, the crystal defects and the facet growth are deeply dependent on the selective growth temperature of the single crystal silicon film, respectively, and crystal defects occur at a high temperature of 1000 ° C. or higher, and facet growth occurs more at a low temperature near 900 ° C. However, it was confirmed that they are deeply related to the increase of the leak current of the junction.

In view of the above situation, an object of the present invention is to provide a selective epitaxial growth step of a single crystal silicon film capable of extremely effectively suppressing the production of crystal defects and facets in the region near the isolation insulating oxide film. A method of manufacturing a semiconductor device is provided.

[0010]

According to the method of manufacturing a semiconductor device of the present invention, a pattern of an insulating film is formed on a silicon substrate, and a selective epitaxial growth method is used to selectively and selectively form the insulating film pattern in the opening. In a method of manufacturing a semiconductor device for depositing a crystalline silicon film, a step of selectively growing the single crystalline silicon film at a temperature of 880 ° C. or higher and 980 ° C. or lower to a thickness exceeding the surface of an insulating film pattern in the opening, And a step of polishing the single crystal silicon film for flattening the selectively grown film of the single crystal silicon film to the height of the insulating film pattern.

In the present invention, the growth temperature of the single crystal silicon film is preferably set in the range of 880 ° C. or higher and 980 ° C. or lower. At a growth temperature exceeding 980 ° C., crystal defects are likely to occur inside the single crystal silicon film 3 due to the high growth rate of the single crystal silicon film 3, and the surface thereof becomes rough. Again 880
At a growth temperature of less than ℃, crystal defects are few, but facets are likely to occur near the inner wall of the isolation insulating oxide film 2,
If a PN junction is formed here and a reverse bias is applied, the leak current will increase.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.

1 and 2 are process sequence diagrams showing an embodiment of the present invention. According to this embodiment, the N ⁺ buried layer 4 is first formed on the P-type silicon substrate 1, and then the film thickness of 1.5 is formed.
A μm isolation insulating oxide film pattern 2 is formed by providing an opening on the N ⁺ buried layer 4 [see FIG. 1 (a)]. Next, the silicon surface in the opening is cleaned by an appropriate pretreatment to selectively grow the N-type silicon single crystal film 3. The growth conditions at 900 ° C. as an example of the growth temperature are as follows.

[0014]

[Table 2]

At this time, in the single crystal silicon film 3, the facets 5 generated at the corners are located above the surface of the isolation insulating oxide film 3 having a film thickness of 1.5 μm as shown in FIG. 1B. So that it is grown to a thickness of, for example, 3 μm. At this time, phosphine gas (PH ₃ ) is added so that the resistivity becomes 0.8 Ωcm. Then, using an aqueous solution containing ethylene / diamine / pyrocatechol [NH (CH ₂ ) ₄ NH] and fine silica powder as a polishing liquid, the wafer surface is pressed against a polyurethane-based polishing pad at a pressure of 100 g / cm ² , and the wafer is rotated. Meanwhile, polishing is performed to scrape off the portion of the single crystal silicon film 3 including the facet 5 which is located above the isolation insulating oxide film 2 (see the partial diagram (a) of FIG. 2). No crystal defects and facets are generated in the single crystal silicon film 3 which has undergone the above steps for the reasons already described. Therefore, the P type base region 6 and the N type emitter region 7 are formed in this region, respectively. By further forming polycrystalline silicon electrodes, the base region 6 as shown in FIG.
It is possible to obtain an NPN transistor having a so-called walled base structure in which the element is in contact with the isolation insulating oxide film 2.

FIG. 3 is an actual measurement diagram of the CB junction leakage current of the NPN transistor in the above embodiment showing the effect of the present invention. FIG. 3 shows the measurement data A of the above embodiment in comparison with the measurement data B and C of the conventional method.
Here, the data B is the measured value by the conventional method at the growth temperature of 1000 ° C., and the data C is the measured value by the conventional method at the growth temperature of 900 ° C. As can be seen, the single crystal silicon film selectively grown by the conventional method is affected by crystal defects (data B) or facets (data C),
When the junction is formed in the vicinity of the isolation insulating oxide film, the leak current of the junction is rapidly increased. Conversely,
It can be seen that the device according to the present invention does not depend on the separation distance from the isolation insulating oxide film at all. That is, even when the bonding surface is in close contact with the insulating oxide film, the leakage current of the bonding is always constant and extremely small as shown by the data A.

FIG. 4 shows an N-ch manufactured according to the present invention.
A sectional view of a MOS transistor is shown. The isolation insulating oxide film 2 is grown to a thickness of 1.5 μm on the N-type silicon substrate 1 ′, and after opening a window, the P-type single crystal silicon film 8 is grown to a thickness of 3 μm at the growth temperature of 900 ° C. in this opening. Selectively epitaxially grown. Then, the P-type single crystal silicon film 8 is polished and flattened to form a flat P-type single crystal silicon film having no crystal defects and facets in the opening. Therefore, the polycrystalline silicon gate electrode 9 and the source / drain 1 are formed on the gate oxide film according to the usual technique.
By forming the N ⁺ diffusion regions of 0 and 11, respectively, an N-ch MOS transistor with an extremely small leak current can be obtained.

In the above embodiment, the single crystal silicon film 3 was grown by twice the thickness of the isolation insulating film 2.
After growing to a thickness between 5 and 2.5 times,
Even if the portion protruding over the insulating film 2 is scraped off, an increase in leak current can be suppressed.

[0019]

As described in detail above, according to the present invention, a single crystal silicon film is formed in the opening of the isolation insulating oxide film and the PN junction has the isolation insulating oxide film without increasing the leak current of the PN junction. Since the selective epitaxial growth can be performed so as to be in contact with, it is possible to exert a remarkable effect in the production of a highly reliable semiconductor device.

[Brief description of drawings]

FIG. 1 is a process sequence chart showing an embodiment of the present invention.

FIG. 2 is a process flow chart showing an embodiment of the present invention.

FIG. 3 is an actual measurement diagram of a CB junction current.

FIG. 4 is an N-ch MOS manufactured by applying the present invention.
It is sectional drawing of a transistor.

FIG. 5 is a cross-sectional view of an N-type single crystal silicon film manufactured by a conventional selective epitaxial method.

FIG. 6 is a plan view and a cross-sectional view taken along the line AA ′ of the semiconductor device in which the base region of the NPN transistor is formed.

[Explanation of symbols]

1 P-type silicon substrate 1'N-type silicon substrate 2 Isolation insulating oxide film pattern 3 N-type single crystal silicon film 4 N ⁺ buried layer 5 Facet 6 P-type base region 7 Emitter region 8 P-type single-crystal silicon film 9 Polycrystal Silicon gate electrode 10 Source region 11 Drain region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display area H01L 21/331 29/73

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device, comprising forming a pattern of an insulating film on a silicon substrate and selectively depositing a single crystal silicon film in an opening of the insulating film pattern by using a selective epitaxial growth method. A step of selectively growing a single crystal silicon film at a temperature of 880 ° C. or more and 980 ° C. or less to a thickness exceeding the surface of the insulating film pattern in the opening; and a selective growth film of the single crystal silicon film of the insulating film pattern. And a step of polishing a single crystal silicon film to be flattened to a height, a method of manufacturing a semiconductor device.