JPS5939758B2 - chime sound generator - Google Patents

chime sound generator

Info

Publication number
JPS5939758B2
JPS5939758B2 JP52131350A JP13135077A JPS5939758B2 JP S5939758 B2 JPS5939758 B2 JP S5939758B2 JP 52131350 A JP52131350 A JP 52131350A JP 13135077 A JP13135077 A JP 13135077A JP S5939758 B2 JPS5939758 B2 JP S5939758B2
Authority
JP
Japan
Prior art keywords
switch
capacitor
turned
chime sound
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP52131350A
Other languages
Japanese (ja)
Other versions
JPS5464450A (en
Inventor
宏志 鬼頭
和男 高萩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP52131350A priority Critical patent/JPS5939758B2/en
Publication of JPS5464450A publication Critical patent/JPS5464450A/en
Publication of JPS5939758B2 publication Critical patent/JPS5939758B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K4/00Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape

Description

【発明の詳細な説明】 本発明はスイッチのオン時、オフ時にそれぞれ余韻のあ
るチヤイム音を発生させるチヤイム音発生装置に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a chime sound generating device that generates a chime sound with a lingering sound when a switch is turned on and off.

一般に、スイッチのオン時、オフ時にそれぞれ余韻のあ
るチヤイム音を発生させる場合には、スイッチをオンし
たときに動作する第1の時定数回路とスイッチをオフし
たときに動作する第2の時定数回路をそれぞれ別々に設
け、これらの時定数回路でそれぞれ余韻のあるチヤイム
音となる減衰信号を得るように構成している。
Generally, when a chime sound with a lingering sound is generated when a switch is turned on and off, a first time constant circuit operates when the switch is turned on, and a second time constant circuit operates when the switch is turned off. The circuits are provided separately, and each of these time constant circuits is configured to obtain a decay signal that produces a chime sound with a lingering sound.

しかしながら、この種のものではスイッチのオン時に動
作する時定数回路とスイッチのオフ時に動作する時定数
回路をそれぞれ別々に構成しているため、これらの時定
数回路を構成する各電気部品のバラツキにより、両時定
数回路の特性を完全に一致させることがほとんど不可能
であり、スイッチのオン時に発生するチヤイム音とスイ
ッチのオフ時に発生するチヤイム音が必ず異なつたもの
になるという問題があつた。本発明は以上のような従来
の欠点を除去するものであり、簡単な構成でスイッチの
オン時、オフ時いずれの場合でも同一の減衰特性をもつ
優れたチヤイム音発生装置を提供することを目的とする
ものである。
However, in this type of device, the time constant circuit that operates when the switch is on and the time constant circuit that operates when the switch is off are configured separately, so variations in the electrical components that make up these time constant circuits may cause However, there was a problem in that it was almost impossible to completely match the characteristics of both time constant circuits, and the chime sound generated when the switch was turned on and the chime sound generated when the switch was turned off were always different. The present invention eliminates the above-mentioned conventional drawbacks, and aims to provide an excellent chime sound generating device that has a simple configuration and has the same attenuation characteristics whether the switch is on or off. That is.

以下、本発明のチヤイム音発生装置について一実施例の
図面とともに説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The chime sound generating device of the present invention will be described below with reference to drawings of an embodiment.

第1図において、1はチヤイム音等を発生させる時に操
作するスイッチ、2はトランジスタTiのオンにともな
つて動作を開始する定電流回路、3は端子3a、3bに
加わる信号を互に比較し、その出力を端子3cに出力す
る第1のコンパレータ、4は端子4a、4bに加わる信
号を互に比較し、その出力を端子4cに出力する第2の
コンパレータ、5,6はそれぞれ第1、第2のコンパレ
ータ3,4の比較電圧を設定するための定電流回路、7
は直流電源Vccを供給するための電源線、8は出力端
子、9は変調信号が印加される入力端子、T1〜T8は
それぞれトランジスタ、R1〜R9はそれぞれ抵抗、C
l,C2はコンデンサである。
In Fig. 1, 1 is a switch that is operated when generating a chime sound, etc., 2 is a constant current circuit that starts operating when transistor Ti is turned on, and 3 is a circuit that compares signals applied to terminals 3a and 3b. , a first comparator that outputs its output to the terminal 3c; 4 a second comparator that compares the signals applied to the terminals 4a and 4b with each other and outputs its output to the terminal 4c; 5 and 6, the first, constant current circuit for setting comparison voltages of second comparators 3 and 4, 7
is a power supply line for supplying DC power Vcc, 8 is an output terminal, 9 is an input terminal to which a modulation signal is applied, T1 to T8 are transistors, R1 to R9 are resistors, C
1 and C2 are capacitors.

第2図は上記実施例の各部の信号波形を示すものであり
、aはスイツチ1と抵抗R1間のライン1aにおける電
圧波形、bはコンデンサC,の両端に現われる電圧波形
、Va,Vbはそれぞれコンパレータ3,4の端子3a
,4bに加えられる第1、第2の比較電圧レベル、cは
トランジスタT4のコレクタに現われる電圧波形、D,
eは入力端子9に変調信号を加えない時と加えた時にそ
れぞれ出力端子8に現われる出力波形である。次にこの
実施例の動作について説明する。今、スイツチ1を押す
とライン1aに第2図aに示すようにVccの電圧が加
わり、トランジスタT1が0Nし、定電流回路2を動作
させる。
FIG. 2 shows the signal waveforms of each part of the above embodiment, where a is the voltage waveform on the line 1a between the switch 1 and the resistor R1, b is the voltage waveform appearing at both ends of the capacitor C, and Va and Vb are respectively Terminal 3a of comparators 3 and 4
, 4b, c is the voltage waveform appearing at the collector of transistor T4, D,
e is an output waveform that appears at the output terminal 8 when no modulation signal is applied to the input terminal 9 and when it is applied to the input terminal 9. Next, the operation of this embodiment will be explained. Now, when switch 1 is pressed, a voltage of Vcc is applied to line 1a as shown in FIG. 2a, transistor T1 is turned ON, and constant current circuit 2 is operated.

定電流回路2はコンデンサC1を一定の速度で充電し、
第2図bに示すようにコンデンサC1の両端電圧を徐々
に土昇させていく。ところでコンパレータ3は端子3b
に加わる電圧が第1の比較電圧レベルVaをこえると、
一定の出力を発生しトランジスタT3をオンにする。ま
たコンパレータ4は端子4aに加わる電圧が第2の比較
電圧レベルVbをこえると出力を発生し、トランジスタ
T2をオフにする。この2つのコンパレータ3,4の端
子3b,4aは共通にコンデンサC,に接続されている
ため、このコンデンサC1が充電中にトランジスタT3
はオフからオンに変り、トランジスタT2はオンからオ
フに変る。すなわち、直列に接続したトランジスタT3
,T2はAND回路を構成しており、抵抗R5を通じて
ゲート回路を構成するトランジスタT4,T5を第2図
cに示すようにオン状態にすることができる。トランジ
スタT4,T5がオンになるとトランジスタT5、過電
流保護用の低抵抗R6を通して電源線7からコンデンサ
C2に非常に短い時間で充電され、充電中および充電完
了と同時に放電時定数用の抵抗R7トランジスタT6,
T7を通して第2図dに示すように減衰信号が出力端子
8に出力される。したがつて、この時にトランジスタT
6のベース電流を変調信号入力端子9に印加される変調
,町の信号で0N一0FF匍脚されるトランジスタT8
を介して分流することにより、出力端子8に減衰しなが
ら入力端子9に印加された変調信号に応じてオンオフす
る第2図eに示すような周波数の信号が得られる。次に
、スイツチ1を離すとコンデンサ1は徐々に放電し、そ
の両端電圧を第2図bの町こ示すように降下させる。従
つて、この時にコンパレータ3,4が前述と同様の動作
をし、第2図c(7)叱こ示すように再びトランジスタ
T4,T5を動作させ、再び減衰信号を発生させる。と
ころで上記実施例においては、ゲート回路を構成するト
ランジスタT4,T5を電源側に接続したPnpトラン
ジスタ、Npnトランジスタによつて構成しているため
、わずかの電圧降下のみでコンデンサC2を充電でき、
コンデンサC2の充電時間を著しく短くすることができ
る。
Constant current circuit 2 charges capacitor C1 at a constant rate,
As shown in FIG. 2b, the voltage across the capacitor C1 is gradually increased. By the way, comparator 3 is connected to terminal 3b.
When the voltage applied to exceeds the first comparison voltage level Va,
Generates a constant output and turns on transistor T3. Further, the comparator 4 generates an output when the voltage applied to the terminal 4a exceeds the second comparison voltage level Vb, turning off the transistor T2. Since the terminals 3b and 4a of these two comparators 3 and 4 are commonly connected to the capacitor C, the capacitor C1 is connected to the transistor T3 during charging.
changes from off to on, and transistor T2 changes from on to off. That is, the transistor T3 connected in series
, T2 constitute an AND circuit, and the transistors T4 and T5 constituting the gate circuit can be turned on through the resistor R5 as shown in FIG. 2c. When transistors T4 and T5 are turned on, capacitor C2 is charged from power supply line 7 through transistor T5 and low resistance R6 for overcurrent protection in a very short time, and during charging and at the same time as charging is completed, resistor R7 for discharging time constant is charged. T6,
Through T7, the attenuated signal is outputted to the output terminal 8 as shown in FIG. 2d. Therefore, at this time, the transistor T
The base current of 6 is modulated and applied to the signal input terminal 9, and the transistor T8 is connected to 0N-0FF by the town signal.
By dividing the current through the output terminal 8, a signal having a frequency as shown in FIG. Next, when switch 1 is released, capacitor 1 gradually discharges, causing the voltage across it to drop as shown in FIG. 2b. Therefore, at this time, the comparators 3 and 4 operate in the same manner as described above, causing the transistors T4 and T5 to operate again as shown in FIG. By the way, in the above embodiment, since the transistors T4 and T5 constituting the gate circuit are composed of Pnp transistors and Npn transistors connected to the power supply side, the capacitor C2 can be charged with only a slight voltage drop.
The charging time of capacitor C2 can be significantly shortened.

以上、実施例より明らかなように、本発明のチヤイム音
発生装置は第1のコンデンサでスイツチをオンしたとき
、徐々に土昇し、スイツチをオフしたとき徐々に下降す
る電圧を得、この電圧が予め定められた第1、第2のレ
ベル間にあるときに第2のコンデンサを素早く充電し、
第1、第2のレベル間よりはずれたときに、上記第2の
コンデンサに蓄積された電荷を予め定められた時定数に
従つて徐々に放電して減衰信号を得るように構成してお
り、したがつて、スイツチのオン時、オフ時にそれぞれ
同一の減衰特性を得ることができ、実用上きわめて有利
である。
As is clear from the above embodiments, the chime sound generating device of the present invention obtains a voltage that gradually rises when the switch is turned on using the first capacitor and gradually decreases when the switch is turned off. quickly charging the second capacitor when is between predetermined first and second levels;
It is configured to gradually discharge the charge accumulated in the second capacitor according to a predetermined time constant to obtain an attenuation signal when the level deviates from between the first and second levels, Therefore, it is possible to obtain the same attenuation characteristics when the switch is on and off, which is extremely advantageous in practice.

すなわち、本発明によれば減衰特性そのものを第2のコ
ンデンサとその放電回路のみによつて得るように構成し
ており、これらの回路を構成する各種電気部品にばらつ
きが生じたとしても、スイツチオン時の減衰特性とスイ
ツチオフ時の減衰特性が互に異なるようなことは全くな
く、常に両者同一の減衰特性のチヤイム音発生装置を得
ることができるという利点を有する。また、本発明によ
れば、スイツチオン時の減衰特性を得るための時定数回
路と、スイツチオフ時の減衰特性を得るための時定数回
路が共に同一であるため、これらを別々に設けた従来の
もののように、それぞれの時定数回路をそれぞれ別々に
設計し、調整する必要がなく、製造、組立、その他にお
いても著しく有利である。
That is, according to the present invention, the attenuation characteristic itself is obtained only by the second capacitor and its discharge circuit, and even if there are variations in the various electrical components that make up these circuits, the attenuation characteristic itself is obtained at the time of switch-on. There is no difference between the attenuation characteristics during switch-off and the attenuation characteristics during switch-off, and there is an advantage that a chime sound generating device having the same attenuation characteristics can be obtained at all times. Furthermore, according to the present invention, the time constant circuit for obtaining the attenuation characteristic at switch-on and the time constant circuit for obtaining the attenuation characteristic at switch-off are both the same, which eliminates the need for conventional systems in which these are provided separately. As such, there is no need to separately design and adjust each time constant circuit, which is extremely advantageous in manufacturing, assembly, and other aspects.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のチヤイム音発生装置における一実施例
の概略電気的結線図、第2図は同実施例の各部の出力波
形図である。 1 ・・・・・・スイツチ、3,4・・・・・・コンパ
レータ、Cl,C2・・・・・・コンデンサ、T1〜T
7・・・・・・トランジスタ。
FIG. 1 is a schematic electrical connection diagram of an embodiment of the chime sound generating device of the present invention, and FIG. 2 is an output waveform diagram of each part of the embodiment. 1...Switch, 3, 4...Comparator, Cl, C2...Capacitor, T1~T
7...Transistor.

Claims (1)

【特許請求の範囲】[Claims] 1 スイッチをオンしたときに徐々に充電されたスイッ
チをオフしたときに徐々に放電される第1のコンデンサ
と、この第1のコンデンサの両端電圧が予め定められた
第1のレベル以上であるときに所定の出力を発生する第
1のコンパレータと、上記第1のコンデンサの両端電圧
が予め定められた上記第1のレベルと異なる第2のレベ
ル以上になつたとき所定の出力を発生する第2のコンパ
レータと、上記第1、第2のコンパレータの出力を入力
とし、上記スイッチのオン時、オフ時にそれぞれ所定の
ゲート信号を発生するゲート回路と、このゲート回路が
上記ゲート信号を発生している期間に充電され、上記期
間が経過すると徐々に放電される第2のコンデンサと、
この第2のコンデンサの両端電圧と別に設けた変調信号
とによつてオンオフ制御されるトランジスタ回路を備え
、上記スイッチのオン時、オフ時の両方でそれぞれ同一
の減衰特性をもつたチヤイム音が得られるように構成し
たチヤイム音発生装置。
1. When the first capacitor is gradually charged when the switch is turned on and gradually discharged when the switch is turned off, and the voltage across this first capacitor is equal to or higher than a predetermined first level. a first comparator that generates a predetermined output, and a second comparator that generates a predetermined output when the voltage across the first capacitor reaches or exceeds a second level different from the predetermined first level. a comparator, a gate circuit which takes the outputs of the first and second comparators as input and generates a predetermined gate signal when the switch is turned on and off, respectively, and this gate circuit generates the gate signal. a second capacitor that is charged for a period of time and gradually discharged after the period;
Equipped with a transistor circuit that is turned on and off by the voltage across the second capacitor and a separately provided modulation signal, a chime sound with the same attenuation characteristics can be obtained both when the switch is on and when the switch is off. A chime sound generating device configured to
JP52131350A 1977-10-31 1977-10-31 chime sound generator Expired JPS5939758B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52131350A JPS5939758B2 (en) 1977-10-31 1977-10-31 chime sound generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52131350A JPS5939758B2 (en) 1977-10-31 1977-10-31 chime sound generator

Publications (2)

Publication Number Publication Date
JPS5464450A JPS5464450A (en) 1979-05-24
JPS5939758B2 true JPS5939758B2 (en) 1984-09-26

Family

ID=15055869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52131350A Expired JPS5939758B2 (en) 1977-10-31 1977-10-31 chime sound generator

Country Status (1)

Country Link
JP (1) JPS5939758B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55159181A (en) * 1979-05-31 1980-12-11 Rhythm Watch Co Ltd Announcing sound generator of watch

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5194737A (en) * 1975-02-18 1976-08-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5194737A (en) * 1975-02-18 1976-08-19

Also Published As

Publication number Publication date
JPS5464450A (en) 1979-05-24

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