JPH0923640A - Pulse width modulation circuit for dc/dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent fluctuation of gain due to the input voltage. SOLUTION: An error voltage VEA of output voltage from a DC/DC converter is compared through a comparator 14 with the voltage VC of triangular or saw-tooth wave to generate a pulse signal for driving a switch Q having pulse width corresponding to the comparison results. In such a pulse width modulation circuit for DC/DC converter, the interval of rising or falling gradient in a predetermined period of triangular or saw-tooth wave is set as a maximum on- interval and the rising or falling gradient is set to be proportional substantially to an input voltage VIN. Since the maximum on-interval is approximately in inverse proportional to the input voltage VIN, fluctuation of gain due to the input voltage VIN can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width modulation circuit of a DC / DC converter for pulse width modulation of an input DC voltage by comparing an error voltage of an output voltage of a DC / DC converter with a voltage of a triangular wave or a sawtooth wave. Regarding

[0002]

2. Description of the Related Art Generally, when an error voltage of an output voltage of a DC / DC converter is compared with a voltage of a triangular wave or a sawtooth wave, and an input DC voltage is switched with a pulse width according to the comparison result, an ON period is predetermined. It is controlled to be within the maximum value range. FIG. 5 shows a conventional DC / DC converter, and FIG. 6 shows its main signals. In FIGS. 5 and 6, the DC input voltage V _IN is turned on and off based on the pulse control signal d having a variable pulse width (duty ratio) by the switch Q formed of the MOSFET, and then the diode D, the inductance L, and Capacitor C1
Is smoothed by an output smoothing circuit (filter) configured by

This output voltage is divided by resistors R1 and R2, and the error voltage c between this divided voltage and the reference voltage V _ref.
Is generated by the error amplifier (EA) 1 and the comparator (C
OMP) 2 is output. Also, the reference oscillator (OSC)
In order to determine the maximum value t _{M of the} section in which the switch Q is turned on, 3 applies the pulse signal b of the constant period T to the NAND gate d.
Output to a capacitor C with a constant period T and a constant current.
By driving 2 for charging and discharging, a triangular wave (or sawtooth wave) a having a constant frequency and a constant waveform is generated.

In the comparator 2, the error voltage c is the voltage V of the triangular wave a.
_A signal that becomes high level in a section higher than _P is output to the NAND gate d, and the NAND gate d outputs both when the input voltage from the comparator 2 and the pulse signal b from the reference oscillator 3 are high level (section t _on ). The switch Q is turned on by outputting the low-level pulse control signal d. Therefore, in this circuit, the interval t in which the switch Q is turned on is
the maximum value of the _on (maximum on period), constant frequency, is determined by the triangular wave a constant waveform.

[0005]

By the way, the conventional DC
In the / DC converter, the relationship between the input voltage V _IN and the control loop gain is expressed by the following equation (1). G _L = G _EA × V _IN × (t _M / T) / _VP × R2 / (R1 + R2) × G _F (1) where G _L : loop loop gain G _EA : error amplifier gain G _F : output Gain of filter T: One cycle of reference oscillator t _M : Maximum on-time V _P : Voltage of triangular wave R1, R2: Voltage dividing resistance Therefore, as is apparent from the equation (1), the period T and the maximum on-time t _M are since the round loop gain G _L if constant proportional to the input voltage V _iN, the loop gain G _L are determined so that stable operation under the condition where a high input voltage V _iN, the low input voltage V _iN In case of loop gain G _L
There is a problem that is low.

Further, in order to stably operate when the input voltage V _IN is high, necessary to increase the attenuation of the output filter (L, C) in accordance with the loop gain G _L when high input voltages V _IN Output filter (L,
There is a problem that C) becomes large. The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a pulse width modulation circuit of a DC / DC converter capable of preventing a gain from changing due to an input voltage.

[0007]

In order to achieve this object, the present invention compares an error voltage of an output voltage of a DC / DC converter with a voltage of a triangular wave or a sawtooth wave, and a pulse having a width corresponding to the comparison result. In a pulse width modulation circuit of a DC / DC converter that generates a pulse signal for driving a switch with, a rising or falling gradient period in a constant cycle of a triangular wave or a sawtooth wave is set as a maximum ON period, and this rising or falling gradient is It is characterized in that a circuit for making the maximum ON period substantially inversely proportional to the input voltage is provided by making it substantially proportional to the input voltage.

This circuit compares, for example, the error voltage of the output voltage of the DC / DC converter with the amplitude of the triangular wave or sawtooth wave, and generates a first pulse signal having a width corresponding to the comparison result. A second pulse generation circuit that generates a second pulse signal that limits the maximum value of the ON period of the first pulse signal so that its duty ratio is approximately inversely proportional to the input DC voltage; It is composed of switching means for turning on and off the input DC voltage with the first pulse signal whose width is limited by the pulse signal.

When the input voltage is equal to or lower than the predetermined voltage, the rising slope or falling slope of the triangular wave or the sawtooth wave in a constant cycle is fixed to a predetermined value without being substantially proportional to the input voltage. According to the pulse modulation circuit of the present invention as described above, the period of the rising or falling slope in a constant cycle of the triangular wave or the sawtooth wave is set as the maximum ON period, and the rising or falling slope is made substantially proportional to the input voltage. , By making the maximum ON period approximately inversely proportional to the input voltage, the dependence of the loop gain on the input voltage can be eliminated, and therefore, the gain can be prevented from changing due to the input voltage.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a DC according to the present invention.
It is a circuit diagram which shows one Example of a / DC converter. FIG.
In the above, the DC input voltage V _IN is turned on and off based on the pulse control signal V _d having a variable pulse width (duty ratio) by the switch Q configured by the MOSFET
Then, the output is smoothed by an output smoothing circuit (filter) composed of the diode D, the inductance L and the capacitor C1.

This output voltage is divided by resistors R1 and R2, and the error voltage c between this divided voltage and the reference voltage V _ref.
From error amplifier (EA) 1 to comparator (COMP1) 1
4 is output. The reference oscillator (OSC) 11 outputs a pulse signal having a constant period T to the Q terminal and the (/ Q) terminal (hereinafter, the symbol “/” is used for inversion except division), and the Q terminal signal is output from the transistor 12. Applied to the base (/
The Q) terminal signal is applied to the NAND gate 16.

One end of the capacitor C1 is connected to the collector of the transistor 12, and the reference voltage source V _g is connected to the emitter.
Is connected. A current I _I (= KV _IN , which is proportional to the DC input voltage V _IN , is supplied to the capacitor C1 via the current source 13.
(K is a constant) is applied, the capacitor C1 is gradually charged when the Q terminal signal of the reference oscillator 11 is low level, and when the Q terminal signal is high level, the transistor 12 is turned on and the charging voltage of the capacitor C1 is changed. It flows to the emitter side, and therefore the collector potential V of the transistor 12
_c (= charge voltage of the capacitor C1) becomes a sawtooth wave. Here, the reference voltage V _g is used to determine the minimum value of the sawtooth wave.

This collector potential V _c is determined by the comparator (COMP
1) 14 and the comparator (COMP2) 15 are applied. The comparator 14 compares the collector potential V _c with the error voltage V _EA from the error amplifier 1, and outputs a signal V _e that becomes a high level to the NAND gate 16 when V _c <V _EA . Further, the comparator 15 has a collector potential V _c and a reference voltage V _h (<
V _EA ) is compared, and a signal V _f which becomes high level when V _c <V _h is output to the NAND gate 16. Here, the reference voltage V _h is used to determine the maximum value P of the sawtooth wave.

The NAND gate 16 turns on the switch Q by applying a low level signal V _d to the switch Q when these three input voltages (/ Q) and V _e V _f are both at high level. Next, the operation of the above embodiment will be described with reference to FIG. First, when the Q terminal signal of the reference oscillator 11 becomes high level [(/ Q) terminal signal is low level], the transistor 12 is turned on, the charging voltage of the capacitor C1 is discharged and flows to the emitter side, and the transistor 1
The collector potential V _{c of} 2 drops to the reference voltage V _g .

Next, the Q terminal signal is at a low level [(/
Q) terminal signal becomes high level]
Is turned off, the capacitor C1 is charged by the current I ₁ proportional to the DC input voltage V _IN, and the collector potential V _c of the transistor 12 gradually rises. Next, when the Q terminal signal becomes high level, the charging voltage of the capacitor C1 is discharged, and the collector potential V _c becomes a sawtooth wave.

When the collector potential V _c of the transistor 12 gradually rises in this way, the output voltage V _e of the comparator 14 becomes high level during the period of V _c <V _EA , and V _c
The output voltage V _f of the comparator 15 becomes high level during the period of _c <V _h . Further, the voltages V _e and V _f and the reference oscillator 11
The output signal V _d of the NAND gate 16 becomes low level during the period t _{on in} which both (/ Q) terminal signals of the same are high level, and therefore the switch Q is turned on. in this case,
The period t _M1 in which the switch Q is turned on at maximum is from the time when the (/ Q) terminal signal becomes high level to the time when the charging voltage V _{c of the} capacitor C1 rises to the reference voltage V _h , and therefore t _M1 ≧ t _on .

Next, the sawtooth waveform of the charging voltage V _c of the capacitor C1 will be described. Charging voltage V _{c of the} capacitor C1
Is generated by a current I ₁ proportional to the input voltage V _IN ,
Further, the maximum ON period t _M1 is the charging voltage V of the capacitor C1.
It is generated by comparing _c with the reference voltage V _h . Therefore, the maximum on period t _M1 from when the Q terminal signal becomes low level until the charging voltage V _c reaches the reference voltage V _h
Is inversely proportional to the input voltage V _IN .

T _M1 = (V _h −V _g ) × C 1 / I ₁ = V _h × C 1 / KVIN (2) where C 1 is the capacitance of the capacitor C _{1, that} is, the current I ₁ in the equation (2) is Input voltage V _IN
Since the reference voltage V _h and the capacitor C1 are constant, the maximum ON period t _M1 is inversely proportional to the input voltage V _IN .

When the loop loop gain G _L1 is obtained from the equation (2), it can be expressed by the following equation (3). G _L1 = G _EA × V _IN × (t _M1 / T) / (V _h −V _G ) × R2 / (R1 + R2) × G _F (3) As is apparent from the formula (3), the maximum on-period t is t. _{Since M1} is inversely proportional to the input voltage V _IN , the loop loop gain G _L1 has a constant value irrespective of the input voltage V _IN , and therefore it is not necessary to reduce the gain G _L1 even when the input voltage V _IN is high. It is also possible to prevent the output filters (L, C) from becoming large.

Here, the sawtooth wave V when charging the capacitor C1
_Since the rising slope V _c / dt of _c is proportional to the charging current I _1, that is, the input voltage V _IN , when the input voltage V _IN is relatively high and the rising slope V _c / dt is relatively large, the solid line in FIG. As shown by, the voltage of the sawtooth wave V _c becomes higher than the reference voltage V _h immediately before the discharge at the end of the constant period T, and therefore the duty ratio of the output signal V _f of the comparator 15 becomes less than 60%, for example, and the normal Operate.

However, when the input voltage V _IN is relatively low and the rising slope V _c / dt is relatively small, as shown by the alternate long and short dash line in FIG. The voltage of _c is the reference voltage V _h
Lower and therefore the output signal V _{f of the} comparator 15
The duty ratio of is, for example, 80% or more, and does not operate normally.

Therefore, as shown in FIG. 4, when the duty ratio of the output signal V _f of the comparator 15 is, for example, 70% or more, when the input voltage V _IN is less than a certain value V _IN ′, the charging current is Without making I ₁ proportional to the input voltage V _IN , a constant value I
By fixing to ₁ ', the rising slope V _c / dt
Can be operated normally without reducing.

[0023]

As described above, according to the present invention, the period of the rising or falling slope in a constant cycle of the triangular wave or the sawtooth wave is set as the maximum ON period, and this rising or falling slope is approximately proportional to the input voltage. By making the maximum ON period substantially inversely proportional to the input voltage, the dependence of the input voltage on the loop gain disappears, and thus the gain can be prevented from changing due to the input voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a DC / DC converter according to the present invention.

FIG. 2 is a waveform diagram showing main signals of the circuit of FIG.

FIG. 3 is an explanatory diagram showing a relationship between an input DC voltage and a rising slope of a sawtooth wave.

FIG. 4 is an explanatory diagram showing a relationship between an input DC voltage and a charging current for generating a sawtooth wave.

FIG. 5 is a circuit diagram showing a conventional DC / DC converter.

6 is a waveform diagram showing the main signals of the circuit of FIG.

[Explanation of symbols]

1: Error amplifier (EA) 11: Reference oscillator (OSC) 12: Transistor 13: Current source 14, 15: Comparator 16: NAND gate Q: Switch D: Diode L: Inductance C, C1: Capacitor R1, R2: Min Piezoresistors V _ref , V _g , V _h : reference voltage

Claims (3)

[Claims] 1. A DC / DC converter which compares an error voltage of an output voltage of a DC / DC converter with a voltage of a triangular wave or a sawtooth wave and generates a pulse signal for driving a switch with a pulse having a width corresponding to the comparison result. In the pulse width modulation circuit of, the maximum ON period is defined by setting the rising or falling slope period in a constant cycle of a triangular wave or sawtooth wave as the maximum ON period, and making the rising or falling slope approximately proportional to the input voltage. A pulse width modulation circuit for a DC / DC converter, which is provided with a circuit for making the voltage substantially inversely proportional to the input voltage. 2. A pulse width modulation circuit for a DC / DC converter according to claim 1, wherein said circuit compares the error voltage of the output voltage of the DC / DC converter with the amplitude of a triangular wave or sawtooth wave and compares them. The first width depending on the result
And a second pulse signal that limits the maximum value of the ON period of the first pulse signal so that its duty ratio is approximately inversely proportional to the input DC voltage. A DC / DC converter comprising: a second pulse generation circuit; and a switching means for turning on / off an input DC voltage with a first pulse signal whose width is limited by the second pulse signal. Pulse width modulation circuit. 3. The pulse width modulation circuit for a DC / DC converter according to claim 1, wherein when the input voltage is equal to or lower than a predetermined voltage, a rising slope or a falling slope in a constant cycle of a triangular wave or a sawtooth wave is used as the input voltage. Not roughly proportional,
A pulse width modulation circuit for a DC / DC converter, which is fixed to a predetermined value.