JP2003299356A - Dc-dc converter control method - Google Patents

Dc-dc converter control method

Info

Publication number
JP2003299356A
JP2003299356A JP2002098482A JP2002098482A JP2003299356A JP 2003299356 A JP2003299356 A JP 2003299356A JP 2002098482 A JP2002098482 A JP 2002098482A JP 2002098482 A JP2002098482 A JP 2002098482A JP 2003299356 A JP2003299356 A JP 2003299356A
Authority
JP
Japan
Prior art keywords
voltage
output
circuit
converter
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002098482A
Other languages
Japanese (ja)
Inventor
Takashi Sonoda
崇 園田
Kiyoshi Moriya
清志 森谷
Kesanobu Kuwabara
今朝信 桑原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Nanao Corp
Original Assignee
Fuji Electric Co Ltd
Nanao Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Nanao Corp filed Critical Fuji Electric Co Ltd
Priority to JP2002098482A priority Critical patent/JP2003299356A/en
Publication of JP2003299356A publication Critical patent/JP2003299356A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method that attenuates the abnormal noise of a transformer without causing power consumption at a light load, because, if a DC power source voltage is higher than usual when switching elements are changed over in a DC-DC (direct current-direct current) converter, a rush current that flows into the transformer causes harsh grating noise. <P>SOLUTION: This DC-DC converter is the one that converts a DC power source voltage into a DC output of a constant voltage by on-off operations of switching elements, and that oscillates the switching elements intermittently by providing an oscillating period and a forced stop period at the time of a light load including no load. In this converter, by controlling the output of a comparator that compares the output of a function voltage generating circuit including a triangular-wave voltage with a command value according to the DC power source voltage, the on-range width of the switching elements is made to change so that the current that flows into the transformer does not increase as the DC power source voltage increases. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、直流電源の出力
を、変圧器を介して任意の直流出力に変換するDC/D
Cコンバータの制御方法、特に無負荷を含む軽負荷時に
おける制御方法の改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC / D for converting the output of a DC power supply into an arbitrary DC output via a transformer.
The present invention relates to an improvement of a control method of a C converter, particularly a control method at a light load including no load.

【0002】[0002]

【従来の技術】図8に従来例の回路接続図を示す。図8
の回路はフライバックコンバータの例で、直流電源1、
スイッチ素子2、フライバックトランス3、整流器4及
びコンデンサ5から電力回路が構成される。コンデンサ
5の出力電圧Voは、出力電圧検出調整回路6の入力段
である差動増幅器61に設定電圧Vrefと共に与えら
れ、その偏差に相当する信号がフォトカプラ62を介し
て指令値Vcとして出力される。この指令値Vcは、コ
ンパレータ7において関数電圧発生回路8の出力Vtと
比較され、PWM(パルス幅変調)信号Vmを発生す
る。関数電圧発生回路8は、三角波(鋸歯状波を含む)
出力電圧を発生するものである。
2. Description of the Related Art FIG. 8 shows a circuit connection diagram of a conventional example. Figure 8
The circuit is an example of flyback converter, DC power supply 1,
A power circuit is composed of the switch element 2, the flyback transformer 3, the rectifier 4, and the capacitor 5. The output voltage Vo of the capacitor 5 is given to the differential amplifier 61, which is the input stage of the output voltage detection adjustment circuit 6, together with the set voltage Vref, and a signal corresponding to the deviation is output as the command value Vc via the photocoupler 62. It This command value Vc is compared with the output Vt of the function voltage generation circuit 8 in the comparator 7, and a PWM (pulse width modulation) signal Vm is generated. The function voltage generation circuit 8 has a triangular wave (including a sawtooth wave)
It produces an output voltage.

【0003】このPWM信号Vmと、固定周波数かつ固
定デューティ比の矩形波信号発生回路10の出力Vsと
は、アンドゲート11において論理積をとられ,ゲート
信号Vgとなってゲートドライブ回路9を介してスイッ
チ素子2をオンオフさせる。
The PWM signal Vm and the output Vs of the rectangular wave signal generating circuit 10 having a fixed frequency and a fixed duty ratio are logically ANDed in the AND gate 11 and become a gate signal Vg via the gate drive circuit 9. Switch element 2 is turned on and off.

【0004】図9は図8の従来回路の動作波形を示すも
ので、(1)は出力指令値Vcと関数電圧発生回路8の
出力Vtとの関係を示しており、(2)は矩形波信号発
生回路10の出力VsのLレベル領域を中心に描いたも
のである。(3)に示すように、コンパレータ7の出力
であるPWM信号Vmは、(1)の波形図で指令値Vc
が関数電圧発生回路8の出力電圧Vtを上回っている期
間中、Hレベルとなるが、PWM信号Vmは矩形波信号
発生回路10の出力VsがHレベルのときにのみアンド
ゲート11を通過できるので、アンドゲート11の出力
信号Vgは(4)で示すような波形となる。
FIG. 9 shows the operation waveforms of the conventional circuit of FIG. 8. (1) shows the relationship between the output command value Vc and the output Vt of the function voltage generating circuit 8, and (2) shows the rectangular wave. The drawing is centered on the L level region of the output Vs of the signal generation circuit 10. As shown in (3), the PWM signal Vm output from the comparator 7 is the command value Vc in the waveform diagram of (1).
Is at the H level while the output voltage Vt of the function voltage generating circuit 8 is higher than the output voltage Vt, the PWM signal Vm can pass through the AND gate 11 only when the output Vs of the rectangular wave signal generating circuit 10 is at the H level. The output signal Vg of the AND gate 11 has a waveform as shown in (4).

【0005】このように、図9に示す従来回路は、矩形
波信号発生回路10の出力VsがHレベルのときにスイ
ッチ素子2がスイッチングを繰り返す発振期間となり、
出力VsがLレベルのときにスイッチ素子2がスイッチ
ングを強制停止される強制停止期間となるようにして、
ゲートドライブ回路9を介してスイッチ素子2を間欠発
振動作させるものである。
As described above, in the conventional circuit shown in FIG. 9, when the output Vs of the rectangular wave signal generation circuit 10 is at the H level, the switching element 2 repeats switching, and the oscillation period is reached.
When the output Vs is at the L level, the switch element 2 is forced to stop switching, and the forced stop period is set.
The switch element 2 is intermittently oscillated through the gate drive circuit 9.

【0006】そして、上述の従来回路によれば、強制停
止期間を設けることで単位時間当りのスイッチング回数
を減少させ、スイッチング損失や導通損失を低減させる
ことができる。ただし、強制停止期間にはフライバック
コンバータの出力にエネルギが供給されないことから、
出力電圧が多少脈動するため、軽負荷時に想定した最大
負荷時における出力電圧の脈動を許容値内に抑えるよ
う、発振期間と強制停止期間を最適に設定することが必
要である。
According to the above-mentioned conventional circuit, the number of times of switching per unit time can be reduced by providing the forced stop period, and the switching loss and the conduction loss can be reduced. However, since energy is not supplied to the output of the flyback converter during the forced stop period,
Since the output voltage pulsates a little, it is necessary to optimally set the oscillation period and the forced stop period so that the pulsation of the output voltage at the time of the maximum load, which is assumed at the time of light load, is suppressed within the allowable value.

【0007】[0007]

【発明が解決しようとする課題】ところで、図8に示す
従来例では、強制停止期間と発振期間の切り替わりのタ
イミングに、スイッチ素子のオン幅が急激に変化し、直
流電源1の電圧が高い場合にはトランスに大電流が急激
に流れて電気的なストレスが加わるため、矩形波信号発
生回路10の発振周波数が可聴帯域内である場合には、
トランスから非常に耳障りな異常音が発生するという問
題がある。
By the way, in the prior art example shown in FIG. 8, when the ON width of the switching element changes abruptly at the timing of switching between the forced stop period and the oscillation period and the voltage of the DC power supply 1 is high. Since a large current rapidly flows through the transformer and electrical stress is applied to the transformer, if the oscillation frequency of the rectangular wave signal generation circuit 10 is within the audible band,
There is a problem that an abnormal sound that is very offensive to the ear is generated from the transformer.

【0008】すなわち、図9において、強制停止期間か
ら発振期間に切り替わる時点toに着目すると、直流電
源電圧が低い場合(A)にはトランスの1次電流Ipが
同図の(5)に示すようにそれほど急峻でない勾配で立
ちあがり、出力電圧も(6)に示すように緩やかな増減
を繰り返すのであるが、直流電源電圧が高い場合(B)
には、(7)に示すように電流が急激に流れ込み、出力
電圧も急峻な立ちあがりを呈するため、トランスの巻線
や鉄心には間欠的な強い電磁力が働き、結果として耳障
りなノイズが発生することになる。
That is, in FIG. 9, paying attention to the time point to when the forced stop period is switched to the oscillation period, when the DC power supply voltage is low (A), the primary current Ip of the transformer is as shown in (5) of FIG. When the DC power supply voltage is high (B), the output voltage rises at a not so steep gradient and the output voltage repeats a gentle increase and decrease as shown in (6).
As shown in (7), the current suddenly flows in and the output voltage rises steeply, so intermittent strong electromagnetic force acts on the transformer windings and iron core, resulting in annoying noise. Will be done.

【0009】したがって、この発明の課題は、軽負荷時
に間欠発振動作をさせて消費電力の低減を図るコンバー
タにおいて、如何なる入力電圧に対してもトランスから
の異常音が発生しないようなDC/DCコンバータの制
御方法を提供することにある。
Therefore, an object of the present invention is to provide a DC / DC converter in which no abnormal sound is generated from the transformer for any input voltage in a converter which is designed to perform an intermittent oscillation operation at a light load to reduce power consumption. It is to provide a control method of.

【0010】[0010]

【課題を解決するための手段】この発明によれば、前記
課題は、直流電源電圧をスイッチ素子のオンオフ動作に
より一定電圧の直流出力に変換するものであって、無負
荷を含む軽負荷時に発振期間と強制停止期間を設けてス
イッチ素子を間欠発振動作させるDC/DCコンバータ
において、PWM信号の生成のために出力指令値と比較
される三角波電圧の波高値を直流電源電圧の高低に応じ
て制御することにより、スイッチ素子のオン幅を変化さ
せることによって達成できる。
According to the present invention, the above object is to convert a DC power supply voltage into a DC output of a constant voltage by an ON / OFF operation of a switch element, and to oscillate at a light load including no load. In a DC / DC converter that intermittently oscillates a switch element by providing a period and a forced stop period, the crest value of a triangular wave voltage that is compared with an output command value for generating a PWM signal is controlled according to the level of a DC power supply voltage. This can be achieved by changing the ON width of the switch element.

【0011】三角波電圧の波高値を定めるためには、定
電流で充放電されるコンデンサの容量を切り替えるのが
簡便である(請求項2記載の発明)。
In order to determine the peak value of the triangular wave voltage, it is easy to switch the capacity of the capacitor charged and discharged with a constant current (the invention according to claim 2).

【0012】また、三角波電圧の波高値を定めるため
に、三角波電圧を生成するコンデンサへの充電電流を切
り替えるようにすることも目的にかなっている(請求項
3記載の発明)。
Further, in order to determine the peak value of the triangular wave voltage, it is also an object to switch the charging current to the capacitor for generating the triangular wave voltage (the invention according to claim 3).

【0013】[0013]

【発明の実施の形態】図1は請求項1記載の発明におけ
る実施の形態を示す回路接続図で、この回路の動作波形
を示す図2および図3を参照しつつ動作態様を説明す
る。この実施例は、フライバックコンバータを例にとっ
たもので、図の上半部は図8と同様の構成であるので、
図8と同じ素子ないし回路には同一の符号を付してあ
る。図8との相違は関数電圧発生回路の構成にある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit connection diagram showing an embodiment of the invention described in claim 1. The operation mode will be described with reference to FIG. 2 and FIG. 3 showing operation waveforms of this circuit. In this embodiment, a flyback converter is taken as an example, and the upper half of the figure has the same structure as that of FIG.
The same elements or circuits as those in FIG. 8 are designated by the same reference numerals. The difference from FIG. 8 lies in the configuration of the function voltage generation circuit.

【0014】図1における関数電圧発生回路18におい
ては、コンパレータ7において出力電圧検出調整回路6
の出力指令値Vcと比較されるべき出力電圧Vtは、コ
ンデンサ20と21の並列接続回路の端子電圧となって
いる。より正確にいえば、コンデンサ20は直接に、そ
してコンデンサ21はスイッチ回路22を介して大地電
位に接続されている。これらの二つのコンデンサは、矩
形波信号発生回路23の出力によりオンオフされるスイ
ッチ回路24および25ならびに定電流回路26および
27により、一定電圧Vccから充放電される。したが
って、コンデンサ20および21の端子電圧は三角波状
に変化する。
In the function voltage generation circuit 18 shown in FIG. 1, the output voltage detection adjustment circuit 6 is provided in the comparator 7.
The output voltage Vt to be compared with the output command value Vc of is the terminal voltage of the parallel connection circuit of the capacitors 20 and 21. More precisely, the capacitor 20 is connected directly and the capacitor 21 is connected to ground potential via the switch circuit 22. These two capacitors are charged and discharged from the constant voltage Vcc by the switch circuits 24 and 25 and the constant current circuits 26 and 27 which are turned on and off by the output of the rectangular wave signal generation circuit 23. Therefore, the terminal voltages of the capacitors 20 and 21 change in a triangular waveform.

【0015】コンデンサ21に直列接続されたスイッチ
回路22は、次のようにオンオフされる。すなわち、直
流電源1の電圧を抵抗28と抵抗29とで分圧した電圧
Vdと基準電圧Vbとをコンパレータ30で比較し、分
圧電圧Vdが基準電圧Vbより小さいと、コンパレータ
30の出力によりコンデンサ21に直列接続されたスイ
ッチ22がオンする。この結果、三角波電圧を形成する
ためのコンデンサはコンデンサ20とコンデンサ21の
並列接続となり、容量が増加するため三角波電圧の波高
値は低くなる。したがってコンパレータ7の出力による
スイッチ素子2のオン時間は長くなる。
The switch circuit 22 connected in series with the capacitor 21 is turned on and off as follows. That is, the voltage Vd obtained by dividing the voltage of the DC power supply 1 by the resistors 28 and 29 is compared with the reference voltage Vb by the comparator 30, and if the divided voltage Vd is smaller than the reference voltage Vb, the output of the comparator 30 causes the capacitor The switch 22 connected in series with 21 is turned on. As a result, the capacitor for forming the triangular wave voltage is the capacitor 20 and the capacitor 21 connected in parallel, and the capacitance increases, so that the peak value of the triangular wave voltage decreases. Therefore, the ON time of the switch element 2 due to the output of the comparator 7 becomes long.

【0016】逆に、分圧電圧Vdが基準電圧Vbを超え
ると、コンパレータ30の出力によりコンデンサ21に
直列接続されたスイッチ22がオフして、三角波を生成
するコンデンサはコンデンサ20だけとなり、三角波電
圧の波高値は高くなる。この結果、コンパレータ7の出
力によるスイッチ素子2のオン時間は短くなる。なお、
コンデンサ20とコンデンサ21の容量は1:2程度
に選ぶのがよい。
On the contrary, when the divided voltage Vd exceeds the reference voltage Vb, the switch 22 connected in series with the capacitor 21 is turned off by the output of the comparator 30, and only the capacitor 20 generates a triangular wave, and the triangular wave voltage is generated. Has a high peak value. As a result, the ON time of the switch element 2 due to the output of the comparator 7 becomes shorter. In addition,
It is preferable that the capacitors 20 and 21 have a capacitance of about 1: 2.

【0017】これを、図2および図3を参照して説明す
ると、直流電源電圧が低く、従って図1に示す分圧電圧
Vdが基準電圧Vbを超えないような場合には、三角波
電圧Vtも相応して図2の(1)で示すように波高値が
低く、出力指令値Vcが三角波電圧Vtを超える時間も
長くなるので、図2の(3)に示すPWM信号Vm、し
たがって(4)に示すゲート信号Vgもある程度の幅を
持つことになり、スイッチ素子2のオン時間も長くな
る。トランスの1次電流Ipも(5)に示すように低い
波形となり、出力電圧Voも緩やかに変化する。
This will be described with reference to FIGS. 2 and 3. When the DC power supply voltage is low and therefore the divided voltage Vd shown in FIG. 1 does not exceed the reference voltage Vb, the triangular wave voltage Vt is also reduced. Correspondingly, as shown in (1) of FIG. 2, the crest value is low, and the time when the output command value Vc exceeds the triangular wave voltage Vt also becomes long, so that the PWM signal Vm shown in (3) of FIG. Since the gate signal Vg shown in (3) also has a certain width, the ON time of the switch element 2 also becomes long. The primary current Ip of the transformer also has a low waveform as shown in (5), and the output voltage Vo also changes gently.

【0018】これに対して直流電源電圧が高く、したが
って図1の分圧電圧Vdが基準電圧Vbを超えるような
場合には、三角波電圧Vtも相応して図3の(1)で示
すように波高値が高く、出力指令値Vcが三角波電圧V
tを超える時間は短くなるので、図3の(3)に示すP
WM信号Vm、したがって(4)に示すゲート信号Vg
も相対的に幅が狭くなり、スイッチ素子2のオン時間は
それに応じて短くなる。この結果、トランスの1次電流
Ipも(5)に示すように従来のような大きな値とはな
らず、出力電圧Vpも緩やかな変化を見せる。
On the other hand, when the DC power supply voltage is high and therefore the divided voltage Vd in FIG. 1 exceeds the reference voltage Vb, the triangular wave voltage Vt is also correspondingly shown in (1) of FIG. The peak value is high and the output command value Vc is the triangular wave voltage V.
Since the time over t is shortened, P shown in (3) of FIG.
WM signal Vm, and therefore gate signal Vg shown in (4)
Also has a relatively narrow width, and the ON time of the switch element 2 correspondingly shortens. As a result, the primary current Ip of the transformer does not have a large value as in the conventional case as shown in (5), and the output voltage Vp also shows a gradual change.

【0019】かくして、図1の実施例によれば、直流電
源の電圧が変化してもトランスに流入する電流の変化は
従来よりも軽減されることになり、したがってトランス
の異常音の発生も少なくなるかレベルが低くなる。
Thus, according to the embodiment of FIG. 1, even if the voltage of the DC power supply changes, the change in the current flowing into the transformer is reduced as compared with the conventional case, and therefore the abnormal noise of the transformer is reduced. Will or the level will be lower.

【0020】図4は、この発明の異なる実施例を示すも
ので、図5および図6はその動作波形図である。図4に
おいて、ブロック18で簡単に示されている回路は、図
1の関数電圧発生器18と同様のものである。図4の実
施例ではさらに図1の定電流充放電回路と同様な回路構
成からなる回路素子33〜38を含む回路と、インピー
ダンス変換素子39とダイオード40とを備えている。
FIG. 4 shows a different embodiment of the present invention, and FIGS. 5 and 6 are operation waveform diagrams thereof. In FIG. 4, the circuit briefly indicated by block 18 is similar to the functional voltage generator 18 of FIG. The embodiment of FIG. 4 further includes a circuit including circuit elements 33 to 38 having the same circuit configuration as the constant current charge / discharge circuit of FIG. 1, an impedance conversion element 39 and a diode 40.

【0021】図4の回路においては、スイッチ素子2の
発振期間と強制停止期間とを制御する矩形波信号発生回
路33の出力Vsを用い、強制停止期間から発振期間に
切り替わるタイミングでは、定電流回路36を介してコ
ンデンサ38を定電流充電するようにスイッチ回路34
をオンさせ、コンデンサ38の電圧が徐々に増加するよ
うにする。コンデンサ38はスイッチ回路34に接続さ
れた電源電圧Vccまで充電される。
In the circuit of FIG. 4, the output Vs of the rectangular wave signal generating circuit 33 for controlling the oscillation period of the switching element 2 and the forced stop period is used, and the constant current circuit is used at the timing of switching from the forced stop period to the oscillation period. Switch circuit 34 so that capacitor 38 is charged with a constant current via 36
Is turned on so that the voltage of the capacitor 38 gradually increases. The capacitor 38 is charged to the power supply voltage Vcc connected to the switch circuit 34.

【0022】また、発振期間から強制停止期間に切り替
わるタイミングでは、定電流回路37を介してコンデン
サ38を定電流放電するようにスイッチ回路35をオン
させ、コンデンサ38の電圧が徐々に減少するようにす
る。コンデンサ38の電圧は、ゼロになるまで放電され
る。
At the timing of switching from the oscillation period to the forced stop period, the switch circuit 35 is turned on so that the capacitor 38 is discharged with a constant current through the constant current circuit 37, and the voltage of the capacitor 38 is gradually decreased. To do. The voltage on capacitor 38 is discharged until it reaches zero.

【0023】さらに、コンデンサ38の電圧Vcsをイ
ンピーダンス変換素子39でインピーダンス変換した信
号と、出力電圧検出調整回路6の出力信号Vcとを比較
して、小さい方の値をコンパレータ7の入力信号とする
ために、ダイオード40が接続されている。これによ
り、強制停止期間から発振期間に切り替わったタイミン
グ以後は、コンデンサ38の充電スピードでスイッチ素
子2のオンパルス幅が徐々に増加し、コンデンサ38の
電圧よりも出力電圧検出調整回路6の出力Vcの方が小
さくなると、出力電圧が一定となるようにスイッチ素子
2のオンオフのタイミングがPWM制御される。また、
発振期間から強制停止期間に切り替わったタイミング以
後は、コンデンサ38の放電スピードでスイッチ素子2
のオンパルス幅が叙叙に減少し、コンデンサ38の電圧
がゼロになった時点で、スイッチ素子2が完全にオフ状
態となる。
Further, the signal obtained by impedance-converting the voltage Vcs of the capacitor 38 by the impedance conversion element 39 and the output signal Vc of the output voltage detection adjustment circuit 6 are compared, and the smaller value is used as the input signal of the comparator 7. Therefore, the diode 40 is connected. As a result, after the timing at which the forced stop period is switched to the oscillation period, the ON pulse width of the switch element 2 gradually increases at the charging speed of the capacitor 38, and the output Vc of the output voltage detection adjustment circuit 6 becomes higher than the voltage of the capacitor 38. When it becomes smaller, the on / off timing of the switch element 2 is PWM-controlled so that the output voltage becomes constant. Also,
After the timing of switching from the oscillation period to the forced stop period, the switching element 2 is driven at the discharge speed of the capacitor 38.
When the on-pulse width of is reduced to zero and the voltage of the capacitor 38 becomes zero, the switch element 2 is completely turned off.

【0024】この時、図1の実施例と同様に、関数電圧
発生回路18は直流電源の電圧にしたがって波高値が切
り替わり、直流電源1の電圧が変化してもトランス3に
流入する電流の変化が軽減し、トランスの異常音の発生
が低減される。
At this time, similarly to the embodiment of FIG. 1, the peak value of the function voltage generating circuit 18 is switched according to the voltage of the DC power supply, and even if the voltage of the DC power supply 1 is changed, the current flowing into the transformer 3 is changed. Is reduced and the generation of abnormal noise of the transformer is reduced.

【0025】図5は直流電源電圧が高いときの動作波
形、図6は直流電源電圧が低いときの操作波形を示す。
両図において、(1)は矩形波信号発生回路Vsの出力
信号Vs、(2)はコンデンサ38の端子電圧Vcs、
(3)は三角波電圧Vtと出力指令値Vcとの関係、
(4)は出力電圧Voと設定電圧Vref、(5)は三
角波電圧Vtと出力指令値との関係、(6)はPWM信
号Vm、(7)はトランス1次電流Ipをそれぞれ示
す。
FIG. 5 shows operation waveforms when the DC power supply voltage is high, and FIG. 6 shows operation waveforms when the DC power supply voltage is low.
In both figures, (1) is the output signal Vs of the rectangular wave signal generation circuit Vs, (2) is the terminal voltage Vcs of the capacitor 38,
(3) is the relationship between the triangular wave voltage Vt and the output command value Vc,
(4) shows the output voltage Vo and the set voltage Vref, (5) shows the relationship between the triangular wave voltage Vt and the output command value, (6) shows the PWM signal Vm, and (7) shows the transformer primary current Ip.

【0026】図5と図6を比較すれば明らかなように、
直流電源電圧が低い場合には、図5に示すように三角波
電圧Vtも低く、このため出力指令値Vcが三角波電圧
Vtを超えている期間が相対的に長くなり、したがって
PWM信号Vmの幅が長くなるので、スイッチ素子2の
オン時間も相応して長くなる。
As is clear from a comparison between FIG. 5 and FIG.
When the DC power supply voltage is low, the triangular wave voltage Vt is also low as shown in FIG. 5, so that the period during which the output command value Vc exceeds the triangular wave voltage Vt is relatively long, and therefore the width of the PWM signal Vm is small. Since it becomes longer, the ON time of the switch element 2 also becomes longer accordingly.

【0027】これに対して直流電源電圧が高い場合に
は、図6に示すように三角波電圧Vtも高く、このため
出力指令値Vcが三角波電圧Vtを超えている期間が相
対的に短くなり、したがってPWM信号Vmの幅が短く
なるので、スイッチ素子2のオン時間も相応して短くな
る。
On the other hand, when the DC power supply voltage is high, the triangular wave voltage Vt is also high as shown in FIG. 6, so that the period during which the output command value Vc exceeds the triangular wave voltage Vt becomes relatively short, Therefore, since the width of the PWM signal Vm is shortened, the ON time of the switch element 2 is correspondingly shortened.

【0028】かくして、図4の実施例によれば、図1の
実施例と同様に直流電源の電圧が変化してもトランスに
流入する電流の変化は従来よりも軽減されることにな
り、したがってトランスの異常音の発生も少なくなるか
レベルが低くなる。
Thus, according to the embodiment shown in FIG. 4, even if the voltage of the DC power supply changes, the change in the current flowing into the transformer is reduced as compared with the prior art, as in the embodiment shown in FIG. The abnormal noise of the transformer is reduced or the level is lowered.

【0029】図7は、本発明の実施の際に用いられる関
数電圧発生回路の異なる実施例を示す。直流電源1の電
圧を、抵抗41と抵抗42とで分圧し、分圧電圧Vdと
基準電圧Vbとをコンパレータ43で比較し、インバー
タ43Nを介してアンドゲート44の一方の入力に印加
する。アンドゲート44の他方の入力には矩形波信号発
生回路45の出力が与えられる。この矩形波信号発生回
路45の出力は、定電流回路48又は49と直列接続さ
れたスイッチ回路46又は47に与えられ、これらのス
イッチ回路を交互にオンオフし、コンデンサ52を所定
の定電流で充電もしくは放電する。前述のアンドゲート
44の出力はスイッチ回路50に与えられ、このスイッ
チ回路50がオンすると、付加的な定電流回路51がコ
ンデンサ52の充電に参加する。定電流回路48と51
の供給電流比は1:2程度に選ぶのが良い。
FIG. 7 shows a different embodiment of the function voltage generating circuit used when implementing the present invention. The voltage of the DC power supply 1 is divided by the resistors 41 and 42, the divided voltage Vd and the reference voltage Vb are compared by the comparator 43, and the result is applied to one input of the AND gate 44 via the inverter 43N. The output of the rectangular wave signal generation circuit 45 is given to the other input of the AND gate 44. The output of the rectangular wave signal generation circuit 45 is given to a switch circuit 46 or 47 connected in series with a constant current circuit 48 or 49, and these switch circuits are alternately turned on / off to charge the capacitor 52 with a predetermined constant current. Or discharge. The output of the aforementioned AND gate 44 is given to the switch circuit 50, and when the switch circuit 50 is turned on, the additional constant current circuit 51 participates in the charging of the capacitor 52. Constant current circuits 48 and 51
It is better to select the supply current ratio of about 1: 2.

【0030】かかる構成の下で装置を運転した場合、矩
形波信号発生回路45の出力により、コンデンサ52は
定電流充電または定電流放電を繰り返し、三角波電圧V
tを生成するが、直流電源電圧が低く、分圧電圧Vdが
基準電圧Vbより小さいと、コンパレータ43の反転出
力により、定電流回路51に直列接続されたスイッチ5
0はオンせず、三角波形を生成するコンデンサへの充電
電流は定電流回路48のみが貢献することになるので、
三角波電圧の波高値は低くなる。このとき、コンパレー
タ7の出力によるスイッチ素子2のオン時間は長くな
る。
When the apparatus is operated under such a structure, the capacitor 52 repeats constant current charging or constant current discharging by the output of the rectangular wave signal generating circuit 45, and the triangular wave voltage V
However, when the DC power supply voltage is low and the divided voltage Vd is lower than the reference voltage Vb, the switch 5 connected in series to the constant current circuit 51 is generated by the inverted output of the comparator 43.
0 does not turn on, and only the constant current circuit 48 contributes to the charging current to the capacitor that generates the triangular waveform.
The peak value of the triangular wave voltage becomes low. At this time, the ON time of the switch element 2 due to the output of the comparator 7 becomes long.

【0031】直流電源電圧が高くなり、分圧電圧Vdが
基準電圧Vbを超えると、コンパレータ43の反転出力
により定電流回路45に直列接続されたスイッチ44が
オンして、新たな定電流回路51がコンデンサ52の充
電のために投入されるので、三角波電圧の波高値は高く
なる。この時コンパレータ7の出力によるスイッチ素子
2のオン時間は短くなる。
When the DC power supply voltage rises and the divided voltage Vd exceeds the reference voltage Vb, the switch 44 connected in series with the constant current circuit 45 is turned on by the inverted output of the comparator 43, and a new constant current circuit 51. Is charged for charging the capacitor 52, the peak value of the triangular wave voltage becomes high. At this time, the ON time of the switch element 2 due to the output of the comparator 7 becomes short.

【0032】ここで、上記実施の形態において、コンデ
ンサ20とコンデンサ21の容量比あるいは定電流回路
48と定電流回路51の供給電流比の例として1:2を
あげたが、これは直流電源1の電圧の想定される最低値
と最大値の比が1:3程度の場合を例示したものであ
り、前記電圧の想定される最低値と最大値の比に基づい
て適宜決定すればよい。
Here, in the above embodiment, the capacitance ratio of the capacitor 20 and the capacitor 21 or the supply current ratio of the constant current circuit 48 and the constant current circuit 51 is set to 1: 2. This is an example of the case where the ratio of the assumed minimum value and the maximum value of the voltage is about 1: 3, and may be appropriately determined based on the ratio of the assumed minimum value and the maximum value of the voltage.

【0033】[0033]

【発明の効果】以上の通り、この発明によれば、直流電
源電圧を検出してPWM演算用の関数電圧の波高値を変
化させることによって、電源電圧の変化時に生じるトラ
ンスの異常音を低減させることができ、待機時など軽負
荷時における消費電力を低減することが必要な用途にお
いては、待機専用の特別なコンバータを省略することが
可能となり、低価格の電源システムを提供することがで
きる。
As described above, according to the present invention, by detecting the DC power supply voltage and changing the peak value of the function voltage for PWM calculation, the abnormal noise of the transformer generated when the power supply voltage changes can be reduced. Therefore, in applications where it is necessary to reduce power consumption during light loads such as during standby, a special converter dedicated for standby can be omitted, and a low-cost power supply system can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一の実施例における回路接続図FIG. 1 is a circuit connection diagram in a first embodiment of the present invention.

【図2】第一の実施例の動作波形図(直流電源電圧が低
い場合)
FIG. 2 is an operation waveform diagram of the first embodiment (when the DC power supply voltage is low).

【図3】第一の実施例の動作波形図(直流電源電圧が高
い場合)
FIG. 3 is an operation waveform diagram of the first embodiment (when the DC power supply voltage is high).

【図4】本発明の第二の実施例における回路接続図FIG. 4 is a circuit connection diagram in the second embodiment of the present invention.

【図5】第二の実施例の動作波形図(直流電源電圧が低
い場合)
FIG. 5 is an operation waveform diagram of the second embodiment (when the DC power supply voltage is low).

【図6】第二の実施例の動作波形図(直流電源電圧が高
い場合)
FIG. 6 is an operation waveform diagram of the second embodiment (when the DC power supply voltage is high).

【図7】本発明における関数電圧発生回路の異なる実施
例の回路接続図
FIG. 7 is a circuit connection diagram of another embodiment of the function voltage generating circuit according to the present invention.

【図8】従来の実施例の回路接続図FIG. 8 is a circuit connection diagram of a conventional example.

【図9】従来回路の動作波形図FIG. 9 is an operation waveform diagram of a conventional circuit.

【符号の説明】[Explanation of symbols]

1 直流電源 2 スイッチ素子 3 トランス 4 整流器 5 コンデンサ 6 電圧検出調整回路 7 コンパレータ 9 ゲートドライブ回路 10,23,33 矩形波信号発生回路 11 アンドゲート 18 関数電圧発生回路 39 インピーダンス変換回路 1 DC power supply 2 switch elements 3 transformers 4 rectifier 5 capacitors 6 Voltage detection adjustment circuit 7 comparator 9 Gate drive circuit 10, 23, 33 rectangular wave signal generation circuit 11 AND GATE 18 Function voltage generation circuit 39 Impedance conversion circuit

───────────────────────────────────────────────────── フロントページの続き (72)発明者 森谷 清志 石川県松任市下柏野町153番地 株式会社 ナナオ内 (72)発明者 桑原 今朝信 神奈川県川崎市川崎区田辺新田1番1号 富士電機株式会社内 Fターム(参考) 5H730 AA02 BB43 DD01 EE02 EE07 EE59 FD01 FD11 FF03 FG03 FG05    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kiyoshi Moriya             153 Shimo-Kashiwanocho, Matsuto City, Ishikawa Prefecture Co., Ltd.             In Nanao (72) Inventor Kuwahara Konasa             1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa             Within Fuji Electric Co., Ltd. F-term (reference) 5H730 AA02 BB43 DD01 EE02 EE07                       EE59 FD01 FD11 FF03 FG03                       FG05

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 直流電源電圧をスイッチ素子のオンオ
フ動作により一定電圧の直流出力に変換するものであっ
て、無負荷を含む軽負荷時に発振期間と強制停止期間を
設けてスイッチ素子を間欠発振動作させるDC/DCコ
ンバータにおいて、PWM信号の生成のために出力指令
値と比較される三角波電圧の波高値を直流電源電圧の高
低に応じて制御することにより、スイッチ素子のオン幅
を変化させることを特徴とするDC/DCコンバータの
制御方法。
1. A DC power supply voltage is converted into a DC output of a constant voltage by an ON / OFF operation of a switch element, and an intermittent oscillation operation of the switch element is provided by providing an oscillation period and a forced stop period at a light load including no load. In the DC / DC converter, the ON width of the switching element is changed by controlling the peak value of the triangular wave voltage that is compared with the output command value for generating the PWM signal according to the level of the DC power supply voltage. A characteristic method of controlling a DC / DC converter.
【請求項2】 三角波電圧の波高値を定めるために、定
電流で充放電されるコンデンサの容量を切り替えること
を特徴とする請求項1記載のDC/DCコンバータの制
御方法。
2. The method of controlling a DC / DC converter according to claim 1, wherein the capacity of a capacitor charged and discharged with a constant current is switched to determine the peak value of the triangular wave voltage.
【請求項3】 三角波電圧の波高値を定めるために、三
角波電圧を生成するコンデンサへの充電電流を切り替え
ることを特徴とする請求項1記載のDC/DCコンバー
タの制御方法。
3. The method of controlling a DC / DC converter according to claim 1, wherein the charging current to the capacitor for generating the triangular wave voltage is switched in order to determine the peak value of the triangular wave voltage.
JP2002098482A 2002-04-01 2002-04-01 Dc-dc converter control method Pending JP2003299356A (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publication Number Publication Date
JP2003299356A true JP2003299356A (en) 2003-10-17

Family

ID=29387955

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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EP1909382A2 (en) * 2006-10-04 2008-04-09 Power Integrations, Inc. Method and apparatus to reduce audio frequencies in a switching power supply
US7615984B2 (en) 2005-09-14 2009-11-10 Fuji Electric Device Technology Co., Ltd. DC-DC converter and method of controlling thereof
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JP2006174626A (en) * 2004-12-17 2006-06-29 Oki Electric Ind Co Ltd Switching regulator
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US7615984B2 (en) 2005-09-14 2009-11-10 Fuji Electric Device Technology Co., Ltd. DC-DC converter and method of controlling thereof
WO2007037033A1 (en) * 2005-09-27 2007-04-05 Mitsumi Electric Co., Ltd. Electric power supply device
US7965524B2 (en) 2006-10-04 2011-06-21 Power Integrations, Inc. Method and apparatus to reduce audio frequencies in a switching power supply
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JP2011109913A (en) * 2006-10-04 2011-06-02 Power Integrations Inc Controller used for power regulator
EP1909382A2 (en) * 2006-10-04 2008-04-09 Power Integrations, Inc. Method and apparatus to reduce audio frequencies in a switching power supply
US8194423B2 (en) 2006-10-04 2012-06-05 Power Integrations, Inc. Method and apparatus to reduce audio frequencies in a switching power supply
US9219418B2 (en) 2006-10-04 2015-12-22 Power Integrations, Inc. Method and apparatus to reduce audio frequencies in a switching power supply
EP1909382A3 (en) * 2006-10-04 2014-07-09 Power Integrations, Inc. Method and apparatus to reduce audio frequencies in a switching power supply
US8537570B2 (en) 2006-10-04 2013-09-17 Power Integrations, Inc. Method and apparatus to reduce audio frequencies in a switching power supply
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US8774669B2 (en) 2010-06-22 2014-07-08 Canon Kabushiki Kaisha Switching power source and image forming apparatus including the same
US8693217B2 (en) 2011-09-23 2014-04-08 Power Integrations, Inc. Power supply controller with minimum-sum multi-cycle modulation
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US9531279B2 (en) 2011-09-23 2016-12-27 Power Integrations, Inc. Power supply controller with minimum-sum multi-cycle modulation
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US9106148B2 (en) 2013-11-27 2015-08-11 Canon Kabushiki Kaisha Power supply apparatus and image forming apparatus

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