JP3525436B2 - Switching power supply - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply device, and more particularly to a switching power supply device which has improved power conversion efficiency by reducing power consumption during light load such as load standby.

[0002]

2. Description of the Related Art FIG. 4 shows a switching power supply device which has been widely used conventionally. The switching power supply device shown in FIG. 4 is a DC power supply (1) composed of a rectifying and smoothing circuit (1b) connected to an AC power supply (1a), a primary winding (2a) and a secondary winding (2b). (2) having a MOS, a MOS-FET (MOS field effect transistor) as a switching element (3), a rectifying diode (4) and a smoothing capacitor
A rectifying / smoothing circuit (6) having (5), and an output voltage detecting circuit (8) as an output voltage detecting means for detecting the voltage V _O of the load (7).
And the feedback winding (9) provided in the transformer (2) and the MOS-
A control circuit (10) for controlling on / off of the FET (3) is provided. Primary winding (2a) of transformer (2) and MOS-FET
(3) is connected in series to the DC power supply (1). The rectifying / smoothing circuit (6) is connected to the secondary winding (2b) of the transformer (2) and supplies the load (7) with DC power of the voltage V _O. Feedback winding (9)
Is connected to the power supply terminal (V _CC ) of the control circuit (10) via the rectifying diode (11) and the smoothing capacitor (12). The control circuit (10) is driven by the voltage applied to the power supply terminal (V _CC ), and is a signal for applying the ON / OFF signal V _G to the gate terminal of the MOS-FET (3) via the drive circuit (14). Generator circuit (1
3) and an ON period control circuit (15) for controlling the pulse width of the ON / OFF signal V _G output from the signal generation circuit (13) by the detection signal of the output voltage detection circuit (8). That is, the ON period control circuit (15) extends the pulse width of the ON / OFF signal V _G output from the signal generation circuit (13) when the detection voltage of the output voltage detection circuit (8) is lower than the target value, On the contrary, when it is higher than the target value, the pulse width of the on / off signal V _G output from the signal generation circuit (13) is shortened,
The level of the DC output voltage V _O applied to the load (7) from the secondary winding (2b) of the transformer (2) through the rectifying and smoothing circuit (6) is kept constant. In addition, the positive terminal of the DC power supply (1) and the control circuit
A startup resistor (16) is connected between the power supply terminal (V _CC ) of (10) and the power supply terminal (V) of the control circuit (10) from the DC power supply (1) via the startup resistor (16) at startup. _The voltage applied to ( _CC ) activates the control circuit (10) to make the MOS-FET (3) conductive.

The operation of the switching power supply device shown in FIG. 4 is as follows. When a voltage is applied from the DC power supply (1) to the power supply terminal (V _CC ) of the control circuit (10) via the starting resistor (16), the control circuit (10) starts and the signal generation circuit (13) A high voltage (H) level on / off signal V _G is output, and MO
The S-FET (3) becomes conductive. This makes the transformer
The voltage E [V] of the DC power supply (1) is applied to the primary winding (2a) of (2), and a voltage is generated in the feedback winding (9). Feedback winding
The voltage generated in (9) is applied to the power supply terminal (V _CC ) of the control circuit (10) via the rectifying diode (11) and smoothing capacitor (12), and is applied to the feedback winding (9) after startup. The control circuit (10) is driven by the generated voltage.

A high voltage (H) level on / off signal V _G is applied from the signal generation circuit (13) in the control circuit (10) to the gate terminal of the MOS-FET (3) through the drive circuit (14). And M
When the OS-FET (3) is turned on, a current flows from the DC power supply (1) through the primary winding (2a) of the transformer (2) and the MOS-FET (3), and the energy is supplied to the transformer (2). Is accumulated. At this time, since a reverse voltage is applied to the rectifying diode (4) that constitutes the rectifying and smoothing circuit (6) and the rectifying and smoothing circuit (6) becomes non-conductive, no current flows through the rectifying diode (4) and the transformer
Energy is not transferred to the secondary winding (2b) of (2). At the same time, the reverse voltage is applied to the rectifier diode (11) connected to the feedback winding (9) of the transformer (2), and the rectifier diode (11) becomes non-conductive, so that the MOS-FET (3) is turned on. The charging voltage of the smoothing capacitor (12) is applied to the power supply terminal (V _CC ) of the control circuit (10).

Next, from the control circuit (10) to the MOS-FET (3)
The ON / OFF signal V _G applied to the gate terminal of the MOS transistor changes from the high voltage (H) level to the low voltage (L) level, and the MOS-
When the FET (3) changes from the ON state to the OFF state, the transformer
Since a forward voltage is applied from the secondary winding (2b) of (2) to the rectifying diode (4) of the rectifying and smoothing circuit (6) to make it conductive, the energy stored in the transformer (2) is reduced to 2 Next winding (2b)
Is supplied to the load (7) through the rectifying / smoothing circuit (6), and the transformer (2) is reset. At the same time, the transformer (2)
Since a forward voltage is applied to the rectifying diode (11) connected to the feedback winding (9) of the MOS transistor, the MOS-
During the OFF period of the FET (3), a voltage is applied from the feedback winding (9) to the power supply terminal (V _CC ) of the control circuit (10) via the rectifying diode (11) and the smoothing capacitor (12). And the transformer
When the reset period of (2) ends and the current flowing through the rectifier diode (4) on the secondary side of the transformer (2) becomes almost zero, the control circuit (10) has a high voltage on the gate terminal of the MOS-FET (3). Voltage
The (H) level on / off signal V _G is applied to the MOS-F.
ET (3) is turned on again.

In the light load state in which the impedance of the load (7) is high, the detection voltage of the output voltage detection circuit (8) becomes higher than the target value, so the ON period control circuit in the control circuit (10). Drive circuit (14) from signal generation circuit (13) by (15)
The pulse width of the on / off signal V _G output via the control circuit is controlled to be narrow, and the ON period of the MOS-FET (3) is shortened. On the contrary, when the load (7) has a low impedance and is in a heavy load state, the detection voltage of the output voltage detection circuit (8) becomes lower than the target value, so the ON period control circuit (15) in the control circuit (10) is Thus, the ON / OFF signal V _G output from the signal generating circuit (13) via the drive circuit (14) is controlled to be wide, and the ON period of the MOS-FET (3) is lengthened.

[0007]

In the conventional switching power supply device shown in FIG. 4, the power loss generated in each electric component constituting the switching power supply device is greatly reduced when the load is light such as standby. The switching loss generated in the MOS-FET (3) is low and the load is low.
Since the ratio of the power consumed by the switching power supply device to the power consumed in (7) is large, the conversion efficiency is extremely lowered.

Therefore, it is an object of the present invention to provide a switching power supply device which can reduce the power consumption during a light load such as a load standby and improve the conversion efficiency.

[0009]

A switching power supply device according to the present invention comprises a DC power supply (1), a primary winding (2a) of a transformer (2) connected in series with the DC power supply (1), and A rectifying and smoothing circuit (6) connected to the switching element (3) and the secondary winding (2b) of the transformer (2) and supplying DC power to the load (7).
Output voltage detection means (8) for detecting the voltage (V _O ) of the DC power supplied to the load (7), the feedback winding (9) provided in the transformer (2), and the feedback winding (9 ) and from on-off signal to the control terminal of the receiving and switching element a detection signal of the driving power is supplied and the output voltage detection means (8) (3) (V _G) control circuit which imparts (10) I have it. The control circuit (10) controls the output voltage detection means (8) to supply the load (7) with a low DC power voltage.
When (V _O ) is detected, an output signal (V ₄ ) with a long pulse width is generated, and when the output voltage detection means (8) detects a high DC voltage (V _O ) supplied to the load (7). Output signal with short pulse width
Signal generating means (13) for generating (V ₄ ) and signal generating means (13)
Of the output signal determines the load state determining means for determining a light load state or heavier load conditions than light loads pulse width (V ₄₎ (19,
20) and the load condition judging means (19, 20) judges that the load condition is light, the output voltage detecting means (8) detects the signal.
Frequency control means for reducing the frequency of the OFF signal (V _G) (17)
It has and. The load state determination means (19, 20) uses a pulse signal of the _first minimum ON period (T ₁ ) and a first minimum ON period.
A minimum on period output means (19) for selectively outputting a pulse signal of a _second minimum on period (T ₂ ) having a pulse width narrower than the pulse signal of (T ₁ ) and a minimum on period output means (19) Equipped with an on-period comparison means (20) for comparing the pulse signal of the output signal (V ₄ ) of the signal generation means (13) with the on-period of the output signal (V ₄ ) to determine whether it is a light load state or a load state heavier than the light load. ing.

The ON period comparing means (20) switches from the pulse signal of the _second minimum ON period (T ₂ ) to the pulse signal of the first minimum ON period (T ₁ ) when it is determined that the load condition is light. , The switching element for the pulse signal of the _first minimum ON period (T ₁ ).
The ON / OFF signal (V _G ) is applied to the control terminal of (3), and the frequency of the ON / OFF signal (V _G ) is lowered by the frequency control means (17). Second minimum on period at light load
Since the pulse signal of (T ₂ ) is switched to the pulse signal of the first minimum ON period (T ₁ ), the ON period of the ON / OFF signal (V _G ) is shortened to the first minimum ON period (T ₁ ) or less. Instead, the ON period of the ON / OFF signal (V _G ) becomes constant. Further, the frequency control means (17) lowers the frequency of the on / off signal (V _G ) applied to the control terminal of the switching element (3), so that the number of switching decreases and the switching generated in the switching element (3). Since the loss is reduced, the power consumption of the switching power supply unit at the time of light load such as load standby is reduced,
The conversion efficiency can be improved.

Further, the on-period comparing means (20) determines the first minimum on-period (T
The pulse signal of ₁ ) is switched to the pulse signal of the second minimum on period (T ₂ ), and the pulse signal of the second minimum on period (T ₂ ) is used as an on / off signal (V _G ). ) And the operation of the frequency control means (17) is stopped. As a result, the switching frequency of the switching element (3) does not drop extremely, so the transformer (2)
It is possible to realize high conversion efficiency under normal load or heavy load without increasing the size of the above.

In one embodiment of the present invention, the control circuit (10)
When the load condition judging means (19, 20) judges that the load is heavier than the light load, the frequency of the ON / OFF signal (V _G ) is higher than that at the light load by the detection signal of the output voltage detecting means (8). An ON period control means (18) for controlling the pulse width in the state is provided. When the load (7) is in a heavier load state than the light load, the ON period control means (18) controls the pulse width in a state where the frequency of the ON / OFF signal (V _G ) is higher than that in the light load state. The switching frequency of the switching element (3) does not drop extremely, and high conversion efficiency can be realized even under normal load or heavy load without increasing the size of the transformer (2) and the like. In the embodiment of the present invention, the control circuit (10)
Outputs as the minimum ON period output means (19) of the output signal (V ₃₎ and the output signal (V ₄₎ and the logical OR signal on-off signal of the signal generating means (13) (V _G).

Further, the minimum ON period output means (19) in the embodiment of the present invention is the output signal (V ₄ ) of the signal generation means (13).
Minimum ON period (T ₂₎ when shorter than the second minimum ON period (T ₂₎ is longer than the first minimum on period of the ON period of the second (T ₁₎
Of the output signal (V) of the signal generating means (13).
Minimum ON period (T ₁₎ when longer shorter than the first minimum on period (T ₁₎ to a second minimum on period of the ON period is the first ₄₎ (T
_It has a hysteresis characteristic that outputs the pulse signal of ₂ ).
This enables smooth switching between the frequency control of the ON / OFF signal (V _G ) of the control circuit (10) and the ON period control.

Furthermore, the signal generating means (13) in the embodiment of the present invention is determined by the oscillation frequency setting capacitor (21) and the charging time or discharging time of the oscillation frequency setting capacitor (21). Oscillation means for outputting pulse signal of frequency
(22) and are provided. The frequency control means (17) directly charges the oscillation frequency setting capacitor (21) of the signal generation means (13) with a part of the detection signal of the output voltage detection means (8) or a current signal proportional to the detection signal. Discharge or charge. Here, the charging time of the oscillation frequency setting capacitor (21) indicates the time from when the voltage (V _CF ) of the oscillation frequency setting capacitor (21) reaches the minimum value to the maximum value, and the discharge time is the oscillation frequency setting capacitor (21). The time required for the voltage (V _CF ) of the capacitor (21) to drop from the maximum value to the minimum value is shown. When the load is light, the frequency control means (17) causes the signal generation means to generate a part of the detection signal of the output voltage detection means (8) or a current signal proportional to the detection signal.
Since the electric charge of the oscillation frequency setting capacitor (21) of (13) is directly discharged or charged and the charging time or the discharging time of the oscillation frequency setting capacitor (21) is extended, it is output from the oscillation means (22). The frequency of the pulse signal decreases. As a result, the number of times the switching element (3) is switched is reduced, the switching loss is reduced, and the power consumption of the switching power supply device is reduced, so that the conversion efficiency can be improved.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a switching power supply device according to the present invention will be described below with reference to FIGS. However, in these drawings, the substantially same portions as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted. The control circuit (10) of the switching power supply device according to the present embodiment is shown in FIG.
As shown in, when the output voltage detection circuit (8) is driven by the voltage applied to the power supply terminal (V _CC ) and the low voltage V _O of the load (7) is detected, the output signal V ₄ having a long pulse width is output. A signal generating circuit (13) as a signal generating means for generating an output signal V ₄ having a short pulse width when the output voltage detecting circuit (8) generates a high voltage V _O of the load (7), and a load ( A frequency control circuit (17) as a frequency control means for lowering the frequency of the output signal V ₄ of the signal generation circuit (13) by the detection signal output from the output voltage detection circuit (8) as 7) becomes lighter.
When the load is heavier than the light load (7), the signal generation circuit is generated by the detection signal of the output voltage detection circuit (8) when the frequency of the output signal V ₄ of the signal generation circuit (13) is higher than that of the light load.
An on period control circuit (18) as an on period control means for controlling the pulse width of the output signal V ₄ of (13), and a first minimum on period T corresponding to a light load state or a load state heavier than a light load. A minimum on-period output circuit (19) as minimum on-period output means for outputting the pulse signals V ₁ and V ₂ of the _first or second minimum on-period T ₂ and a minimum on-period output circuit (19). first minimum pulse signals V _1, V ₂ oN period T ₁ or second
Of the output signal V ₄ of the signal generating circuit (13) is compared with the minimum on-period T _{2 of the above-mentioned,} and an on-period comparison circuit as an on-period comparison means for determining a light load state or a load state heavier than the light load. (20), a switching means (26) for switching the frequency control circuit (17) to a driving state or a stopped state by an output signal of the ON period comparison circuit (20), and a pulse signal V _{1 of the} minimum ON period output circuit (19). , V ₂ and an output signal V ₄ of the signal generation circuit (13), an OR gate (14a) and an OR gate (14a) for outputting a logical sum signal
MOS-FET with output signal of ON / OFF signal V _G
And a drive circuit (14) having a driver (14b) applied to the gate terminal of (3). The minimum on-period output circuit (19) and the on-period comparison circuit (20) are in a load state in which it is determined whether the load state is a light load state or a load state heavier than the light load according to the pulse width of the output signal V ₄ of the signal generating circuit (13) It constitutes the judging means.

The minimum ON period output circuit (19) includes a first pulse generating circuit (23) which outputs a _first pulse signal V ₁ which defines a _first minimum ON period T _1, and a _first minimum ON period. Period T ₁
A second pulse generation circuit (24) that outputs a _second pulse signal V ₂ that defines a _second minimum ON period T ₂ that is shorter than
When the load (7) is in the light load state, the first pulse signal V ₁ is output by the output signal of the ON period comparison circuit (20), and when the load (7) is in the load state heavier than the light load, the ON period comparison circuit ( And a minimum ON period switching circuit (25) for outputting the _second pulse signal V _{2 in accordance} with the output signal of 20). First pulse generation circuit
Minimum ON period T ₁ of the first of the first pulse signal V ₁ output from (23), the magnetostriction of the transformer (2) even at light loads the frequency of the on-off signal V _G decreases to audible range Set to a value where no sound is heard. The ON period comparison circuit (20) has a second minimum ON period of the second pulse signal V ₂ output from the minimum ON period output circuit (19) of the ON period of the output signal V ₄ of the signal generation circuit (13). When it is shorter than T ₂ , an output signal indicating a light load state is applied to the minimum on-period switching circuit (25) in the minimum on-period output circuit (19) and to the switching means (26) to control the frequency control circuit ( 17) to the driving state, and the signal generation circuit (1
The output signal V ₄ of (3) has the minimum on-period output circuit (1
When the first pulse signal V ₁ output from 9) is longer than the first minimum on-period T _{1, the} output signal indicating a load state that is heavier than the light load is output to the minimum in the minimum on-period output circuit (19). It is applied to the ON period switching circuit (25) and to the switching means (26) to stop the frequency control circuit (17).

As shown in FIG. 2, the signal generating circuit (13) is
It is determined by the charging time of the oscillation frequency setting capacitor (21) and the oscillation frequency setting capacitor (21), that is, the time until the charging voltage V _{CF of the} oscillation frequency setting capacitor (21) reaches the minimum value to the maximum value. The pulse signal of the oscillating circuit (22) is P by the output signal of the oscillating circuit (22) as an oscillating means for outputting a pulse signal of a frequency
And a PWM control circuit (27) for controlling the WM (pulse width modulation) to generate the output signal V ₄ . PWM control circuit (27)
Is an RS flip-flop (27a) that is set by the pulse signal of the oscillator circuit (22) and is reset by the output signal of the ON period control circuit (18), and the oscillator circuit (22).
NOR gate (27b) which outputs an inversion signal V ₄ of the logical sum of the pulse signal of R and the output signal of the RS flip-flop (27a)
Composed of and. The ON period comparison circuit (20) is the minimum ON period output circuit that is input to the clock signal input terminal (CLK).
D which outputs a signal of the voltage level of the output signal V ₄ of the signal generation circuit (13) input to the control signal input terminal (D) and its inverted signal in synchronization with the falling of the output signal V ₃ of (19) It is composed of flip-flops. Minimum ON period switching circuit (2
5) outputs a logical product signal of the first pulse signal V ₁ output from the first pulse generation circuit (23) and the output signal V ₅ of the inverted signal output terminal of the ON period comparison circuit (20). First A
The ND gate (25a), the second pulse signal V ₂ output from the second pulse generation circuit (24) and the ON period comparison circuit (20)
Of the second AND gate (25b) that outputs a logical product signal of the output signal V ₆ of the non-inverted signal output terminal of the first AND gate (25a) and the second AND gate (25b). It is composed of an OR gate (25c) which outputs a logical sum signal V ₃ with the output signal. The frequency control circuit (17) uses a current signal proportional to the detection signal of the output voltage detection circuit (8) to generate the signal generation circuit (1
It is composed of a current mirror circuit that directly discharges the electric charge of the oscillation frequency setting capacitor (21) in (3). The switching means (26) is composed of a MOS-FET connected between the control terminal of the frequency control circuit (17) and the ground terminal, and the non-inverted output of the ON period comparison circuit (20) in the light load state. The non-inverted output of the ON period comparison circuit (20) when the load is heavier than the light load by turning off the frequency control circuit (17) by the low voltage (L) level signal V ₆ output from the terminal High voltage (H) level signal V ₆ output from the terminal
Turns on and stops the frequency control circuit (17). Other configurations are substantially the same as those of the conventional switching power supply device shown in FIG.

In the above construction, when the load (7) is in a heavier load state than the light load (time t _{1 to} t ₇ shown in FIG. 3),
As shown in FIG. 3B, the output signal V _{4 of the} signal generating circuit (13)
The minimum ON period output circuit (19) whose pulse width is shown in Fig. 3 (C)
Is longer than the pulse width of the output signal V ₃ . For this reason,
ON applied from the drive circuit (14) to the MOS-FET (3)
As shown in FIG. 3 (H), the off signal V _G has a longer pulse width than the output signal V _{3 of the} minimum on period output circuit (19) shown in FIG. 3 (C), and the signal generation shown in FIG. 3 (B) is generated. Output signal V of circuit (13)
The waveform is almost the same as ₄ . On the other hand, a high voltage (H) level signal V ₆ is supplied from the non-inverting output terminal of the ON period comparison circuit (20) composed of a D flip-flop as shown in FIG.
3 is output, and a signal V ₅ having a low voltage (L) level is output from the inverting output terminal as shown in FIG.
As shown in (C), from the minimum on-period switching circuit (25) of the minimum on-period output circuit (19), the second pulse signal V ₂ of the second pulse generating circuit (24) shown in FIG. Is output as the output signal V ₃ . Further, since the output signal V _{6 at} the non-inverting output terminal of the ON period comparison circuit (20) is at a high voltage (H) level,
The switching means (26) composed of MOS-FET is turned on, and the frequency control circuit composed of a current mirror circuit.
(17) is not driven. Therefore, the charging time of the oscillation frequency setting capacitor (21) forming the signal generating circuit (13), that is, the time until the charging voltage V _{CF of the} oscillation frequency setting capacitor (21) reaches the minimum value to the maximum value. It will be constant. Therefore, as shown in FIG. 3A, the frequency of the voltage V _CF of the oscillation frequency setting capacitor (21) of the signal generation circuit (13) becomes constant, and as shown in FIG. According to the output signal of 18), the PWM control circuit (2
The pulse width of the signal V ₄ output from 7) is controlled.

Next, when the load (7) is in a light load state at time t ₇ , the pulse width of the output signal V ₄ of the signal generating circuit (13) is as shown in FIG. 3 (C) as shown in FIG. 3 (B). ) Becomes shorter than the pulse width of the output signal V ₃ of the minimum ON period output circuit (19). Therefore, the on / off signal V _G given from the drive circuit (14) to the MOS-FET (3) is as shown in FIG.
The waveform is substantially the same as that of the output signal V _{3 of the} minimum on-period output circuit (19) shown in FIG. 3 (C), which has a longer pulse width than the output signal V _{4 of the} signal generation circuit (13) shown in (B). On the other hand, at the time t ₈ after the _second minimum on-period T ₂ has elapsed from the time t ₇ , the on-period comparison circuit composed of the D flip-flops.
Since (20) detects that the output signal V ₄ of the signal generation circuit (13) is shorter than the pulse width of the second pulse signal V ₂ of the second pulse generation circuit (24), the on-period comparison circuit (20 ), The output signal V ₆ of the non-inverting output terminal changes from the high voltage (H) level to the low voltage (L) level as shown in FIG. 3 (F), and the output signal V ₅ of the inverting output terminal becomes Low voltage as shown in
The voltage changes from the (L) level to a high voltage (H) level. For this reason,
The after time t ₈ the minimum ON period switching circuit of the minimum ON period output circuit (19) as shown in FIG. 3 (C) from (25) 3 of the first pulse generating circuit shown in (E) (23) The pulse signal V _{1 of 1} is output as the output signal V ₃ . Further, since the output signal V ₆ of the non-inverting output terminal of the after time t ₈ ON period comparison circuit (20) becomes the low voltage (L) level, the switching means being constituted by a MOS-FET (26) is from ON It is turned off, and the frequency control circuit (17) composed of the current mirror circuit is driven. As a result, the electric charge of the oscillation frequency setting capacitor (21) in the signal generation circuit (13) is directly discharged and extracted with a current signal proportional to the detection signal of the output voltage detection circuit (8),
The charging time of the oscillation frequency setting capacitor (21) is the load (7)
Is extended as it becomes lighter. Therefore, time t ₇
After that, the frequency of the voltage V _CF of the oscillation frequency setting capacitor (21) forming the signal generating circuit (13) decreases as the load (7) becomes lighter as shown in FIG. B)
PWM control circuit (27) in the signal generation circuit (13)
The frequency of the signal V ₄ output from the device is controlled.

After that, when the load (7) becomes heavy from the light load state to a certain extent at time t ₁₂ , the pulse width of the output signal V ₄ of the signal generating circuit (13) becomes as shown in FIG. It becomes longer than the pulse width of the output signal V ₃ of the minimum ON period output circuit (19) shown in C). Therefore, from the drive circuit (14) to the MOS-
The on / off signal V _G given to the FET (3) is shown in FIG.
As shown in Fig. 3C, the minimum ON period output circuit (19)
The output signal V ₄ long Figure 3 (B) are shown a signal generator pulse width than the output signal V ₃ (13) and substantially the same waveform.
At time t ₁₄ after the time t ₁₂ minimum ON period T ₁ first has elapsed, the ON period comparison circuit (20) composed of a D flip-flop output signal V ₄ of the signal generating circuit (13) Is the first pulse signal V ₁ of the first pulse generation circuit (23)
It is detected that the output signal V ₆ of the non-inversion output terminal of the ON period comparison circuit (20) is from a low voltage (L) level to a high voltage (H) as shown in FIG. 3F. 3G, the output signal V ₅ of the inverting output terminal changes from a high voltage (H) level to a low voltage (L) level as shown in FIG. Therefore, after the time t _14, the minimum on-period switching circuit (25) of the minimum on-period output circuit (19) to the second pulse generation circuit (24) shown in FIG. 3 (D) as shown in FIG. 3 (C). ) Second pulse signal V ₂ is output as the output signal V ₃ . Further, after the time t _14, the output signal V ₆ of the non-inversion output terminal of the ON period comparison circuit (20) becomes a high voltage (H) level, so that the MOS-
The frequency control circuit composed of a current mirror circuit, in which the switching means (26) composed of the FET is switched from the off state to the on state.
The operation of (17) stops. Accordingly, the oscillation frequency setting capacitor at time t ₁₂ after constituting the signal generation circuit (13)
Since the frequency of the voltage V _CF of (21) becomes constant as shown in FIG. 3 (A), the output signal of the ON period control circuit (18) causes the PWM control circuit (27) in the signal generation circuit (13) to The pulse width of the output signal V ₄ is controlled as shown in FIG.

[0021] Here, the load (7) the period and the time t ₁₂ after the time t ₁ ~t ₇ exhibit some heavy state, because frequency control circuit constituted by a current mirror circuit (17) is stopped As shown in FIG. 3B, the pulse width of the output signal V ₄ of the PWM control circuit (27) in the signal generation circuit (13) is controlled by the output signal of the ON period control circuit (18). Also, the period of time t ₇ ~t ₁₂ loads (7) indicates a mild state, the detection signal by the signal generation circuit of the current mirror circuit a frequency control circuit constituted by (17) the output voltage detection circuit (8) ( Although it operates so as to lower the frequency of the output signal V ₄ of 13), at the same time, the detection signal of the output voltage detection circuit (8) is also input to the ON period control circuit (18), so that FIG. As shown in, the signal generated by the output signal of the ON period control circuit (18)
The pulse width of the output signal V ₄ of (13) is also controlled. However, when the load is light, the first pulse signal V ₁ having the first minimum ON period T ₁ output from the first pulse generation circuit (23) is the output signal V ₃ of the minimum ON period output circuit (19). Drive circuit
Since it is inputted together with the output signal V ₄ of the signal generating circuit (13) to the OR gate (14a) which constitutes (14), it is given to the gate terminal of the MOS-FET (3) as shown in FIG. 3 (H). On
The ON period of the OFF signal V _G becomes equal to the first minimum ON period T ₁ . For this reason, the MOS-FET (3) is forced to be in the ON state for a longer period than necessary (T ₁ ), so that the amount of feedback of the detection signal of the output voltage detection circuit (8) increases, and FIG. As shown in FIG. 7, the pulse width of the output signal V ₄ of the signal generating circuit (13) is shorter than the second minimum ON period T ₂ just before the control system is switched from ON period control to frequency control.

In the present embodiment, the ON period of the ON / OFF signal V _G is kept constant so that the ON period of the ON / OFF signal V _G is not shortened to the first minimum ON period T ₁ or less when the load is light. Since the frequency of the off signal V _G is lowered, the switching loss of the MOS-FET (3) can be reduced and the conversion efficiency can be improved even when the load is light such as standby. Also the load
When (7) becomes heavy to some extent, the minimum ON period output circuit (19)
Output signal V ₃ is switched to a _second pulse signal V ₂ having a _second minimum ON period T ₂ shorter than the first minimum ON period T ₁ , and the frequency of the ON / OFF signal V _G is lower than that at light load. Since the ON period is controlled in a high state, high conversion efficiency can be realized even under normal load or heavy load without increasing the size of the transformer (2) and the like. The minimum ON period output circuit (19) is longer than the signal generating circuit (13) minimum ON period T ₂ output ON period of the signal V ₄ is a second when the second shorter than the minimum ON period T ₂ of the of the outputting a first pulse signal V ₁ having a minimum oN period T ₁ of the 1, the oN period of the output signal V ₄ of the signal generating circuit (13) is first when longer than the minimum on-period T ₁ first Since it has a hysteresis characteristic of outputting the _second pulse signal V ₂ having the second minimum on-period T ₂ shorter than the minimum on-period T ₁ , the control circuit (10) outputs the MOS-FE.
It is possible to smoothly switch between the frequency control and the ON period control of the ON / OFF signal V _G given to the gate terminal of T (3). Furthermore, on / off signal V _G at light load
Since the peak of the current flowing through the transformer (2) can be suppressed even when the frequency of is lowered to the audible range, noise such as magnetostrictive sound of the transformer (2) can be prevented.

The embodiment of the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above-described embodiment, when the load (7) is in a heavier load state than the light load, the oscillation frequency of the oscillation circuit (22) is kept constant and the pulse width of the on / off signal V _G is controlled. However, the output pulse signal of the oscillator circuit (22) is turned on with a constant off period.
The pulse width of the off signal V _G may be controlled. In the above embodiment, the current mirror circuit that directly discharges the electric charge of the oscillation frequency setting capacitor (21) in the signal generation circuit (13) with the current signal proportional to the detection signal of the output voltage detection circuit (8) is used. Although the configuration of the frequency control circuit (17) has been shown, the oscillation frequency setting capacitor (21) in the signal generation circuit (13) is controlled by a current signal proportional to the detection signal of the output voltage detection circuit (8) or a part thereof. The frequency control circuit (17) may be configured by using a current mirror circuit configured to directly charge the electric charge of (1). However, in this case, the oscillation frequency setting capacitor (2
An oscillation circuit (2) that outputs a pulse signal having a frequency determined by the discharge time of 1), that is, the time until the voltage V _{CF of the} oscillation frequency setting capacitor (21) decreases from the maximum value to the minimum value.
The signal generation circuit (13) provided with 2) is used. Further, in the above embodiment, the MOS-FET is used as the switching element.
Although a form using is shown, a bipolar transistor,
IGBT (Insulated Gate Bipolar Transistor), J
-A FET (junction field effect transistor), a thyristor or the like can also be used as the switching element.

[0024]

According to the present invention, by controlling the frequency of the on / off signal applied to the control terminal of the switching element at the time of light load such as standby of load, the switching loss generated in the switching element is reduced, Since the power consumption of the switching power supply device is reduced, it is possible to improve the conversion efficiency. In addition, under normal load condition or heavy load condition, by controlling the pulse width of the on / off signal applied to the control terminal of the switching element, it is possible to prevent the switching frequency from being extremely lowered. It is possible to achieve high conversion efficiency even under heavy load without increasing the size of the device.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of a switching power supply device according to the present invention.

FIG. 2 is an electric circuit diagram showing details of the internal configuration of the control circuit of FIG.

FIG. 3 is a timing chart of signals at various parts during the operation of FIG.

FIG. 4 is an electric circuit diagram showing a conventional switching power supply device.

[Explanation of symbols]

(1) ・ ・ DC power supply, (1a) ・ ・ AC power supply, (1b) ・ ・ Rectifying and smoothing circuit, (2) ・ ・ Transformer, (2a) ・ ・ Primary winding, (2b) ・ ・ Secondary winding Wire, (3) ・ ・ MOS-FET (switching element), (4) ・ ・ Rectifier diode, (5) ・
・ Smoothing capacitor, (6) ・ ・ Rectifying and smoothing circuit, (7) ・ ・ Load, (8) ・ ・ Output voltage detection circuit (output voltage detection means), (9) ・ ・ Feedback winding, (10) ・ ・Control circuit, (1
1) ・ ・ Rectifying diode, (12) ・ ・ Smoothing capacitor,
(13) .. signal generation circuit (signal generation means), (14) .. driving circuit, (14a) .. OR gate, (14b) .. driver, (15) .. on period control circuit, (16) ..Starting resistors, (17) .. Frequency control circuit (frequency control means),
(18) .. ON period control circuit (ON period control means), (1
9) ・ ・ Minimum on period output circuit (minimum on period output means), (20) ・ ・ On period comparison circuit (on period comparison means), (21) ・ ・ Oscillation frequency setting capacitor, (22)
..Oscillation circuit (oscillating means), (23) .. First pulse generation circuit, (24) .. Second pulse generation circuit, (25) ..
Minimum ON period switching circuit, (25a) -first AND gate, (25b) -second AND gate, (25c) -OR
Gate, (26) .. switching means, (27) .. PWM control circuit, (27a) .. RS flip-flop, (27b) ..
NOR gate

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H02M 3/28

Claims (5)

(57) [Claims] 1. A DC power supply, a primary winding and a switching element of a transformer connected in series to the DC power supply, and a rectifier connected to a secondary winding of the transformer and supplying DC power to a load. A smoothing circuit, an output voltage detecting means for detecting a voltage of DC power supplied to the load, a feedback winding provided in the transformer, and driving power supplied from the feedback winding and the output voltage detecting means. And a control circuit for applying an ON / OFF signal to the control terminal of the switching element, the control circuit detecting a low DC power voltage supplied to the load by the output voltage detection means. And a signal generating means for generating an output signal of a long pulse width when the output voltage detecting means detects a high voltage of DC power supplied to the load by the output voltage detecting means, and an output signal of a short pulse width. And determining the load state determining means for determining heavy load condition than the light load state or a light load by the pulse width of the output signal of the signal generating means,
A switching power supply device comprising: frequency control means for lowering the frequency of the on / off signal by a detection signal of the output voltage detection means when the load status determination means determines a light load state, wherein the load status determination means Is a minimum on period output means for selectively outputting a pulse signal of the first minimum on period and a pulse signal of a second minimum on period having a pulse width narrower than the pulse signal of the first minimum on period. An ON period comparison unit that compares the pulse signal of the minimum ON period output unit with the ON period of the output signal of the signal generation unit to determine whether the load state is a light load state or a load state that is heavier than the light load, When the on-duty comparison means determines that the load is light,
While switching from the pulse signal of the second minimum ON period to the pulse signal of the first minimum ON period, the pulse signal of the first minimum ON period is given to the control terminal of the switching element as an ON / OFF signal. The frequency control means lowers the frequency of the ON / OFF signal, and the ON period comparison means determines from the pulse signal of the first minimum ON period to the second minimum when the load state is determined to be heavier than the light load. It is characterized by switching to a pulse signal of the ON period, applying the pulse signal of the second minimum ON period to the control terminal of the switching element as an ON / OFF signal, and stopping the operation of the frequency control means. Switching power supply. 2. The control circuit, when the load condition judging means judges that the load condition is heavier than the light load, the control circuit detects that the ON / OFF signal has a higher frequency than the light load condition by the detection signal of the output voltage detecting device. 2. The switching power supply device according to claim 1, further comprising an on-period control unit that controls the pulse width by means of. 3. The switching according to claim 1, wherein the control circuit outputs a logical sum signal of an output signal of the minimum on period output means and an output signal of the signal generation means as the on / off signal. Power supply. 4. The minimum on-period output means has a first longer period than the second minimum on-period when the on-period of the output signal of the signal generating means is shorter than the second minimum on-period.
A pulse signal of a second minimum on period shorter than the first minimum on period when the on signal of the output signal of the signal generating means is longer than the first minimum on period. The switching power supply device according to claim 2, which has a hysteresis characteristic of outputting a signal. 5. The signal generation means includes an oscillation frequency setting capacitor, and an oscillation means for outputting a pulse signal having a frequency determined by a charging time or a discharging time of the oscillation frequency setting capacitor, the frequency control means. The means for directly discharging or charging the electric charge of the oscillation frequency setting capacitor of the signal generating means with a part of the detection signal of the output voltage detecting means or a current signal proportional to the detection signal. The switching power supply device according to item 1.