JPS5938614B2 - pulse multiplier - Google Patents

Description

[Detailed description of the invention] The present invention relates to a multiplier for digital signals.

Many of the physical quantities such as voltage, current, and various displacements that are naturally observed in actual systems are analog quantities.

Conventionally, for arithmetic processing of physical quantities that do not require accuracy, the analog signals are processed by analog circuits as they are; however, for arithmetic processing that requires accuracy, the analog quantities are converted into digital quantities. Processing by digital circuits is required. Therefore, the present invention provides a multiplier for two input digital signals D4 and D2 consisting of pulses with repetition frequencies (fl) and (f2) (where f2>f1). Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 shows a block diagram of a pulse multiplier, 1 is a pulse oscillation circuit, and the oscillation frequency (fo) [however, f2>f0>
f1] signal D.

This outputs the following. 2 is a first counter, which is a pulse generator circuit 1 output signal D;

The input digital signal D4 is passed through the first delay circuit 3 and used as a reset pulse for the first counter 2. 4 is a shift register,
The first counter 2 output signal (L) is input, and the input digital signals D and D1 are used as shift pulses.

A second counter 5 counts the number of pulses of the input digital signal D2 and outputs a counted value.

6 is a coincidence detection circuit which inputs the output signal of the second counter 5 and the output signal of the shift register 4, and outputs a pulse signal of a constant width when the two coincide.

T is a second delay circuit which inputs the output signal of the coincidence detection circuit 6 and outputs a reset signal for the second counter 5. Therefore, a + signal is generated at the output of the coincidence detection circuit 6. Here, the pulse generator circuit 1 output signal D.

is one pair, therefore, the output of the coincidence detection circuit 6 is a pulse signal corresponding to the product of the input signals D1 and D2. As explained above, according to the present invention, repeated cycles and
Of the two input digital signals D4 and D2 consisting of pulses with wave numbers (fl) and (f2) [however, f2>f1], the input digital signal D0 is used as a reset pulse, and the oscillation frequency (FO) [however, F2> A first counter that counts the pulse signal of the oscillation circuit output of FO〉f1], and the first counter output signal is inputted to the input digital signal D1.
a shift register with a shift pulse; a second counter that counts the number of pulses of the input digital signal D2 and outputs a counted value; the second counter output signal and the shift register output signal are input; A coincidence detection circuit is provided which outputs a pulse signal when the two match, and the coincidence detection circuit output signal is configured as the reset pulse of the second counter. An accurate multiplication value can be obtained.

[Brief explanation of the drawing]

The drawings show block diagrams for explaining the invention. 1... Pulse transmission circuit, 2... First counter, 4... Shift register, 5...
... Second counter, 6... Coincidence detection circuit, D
l, D2...Input digital signal.

Claims (1)

[Claims] 1 Frequencies are (f_1) and (f_2) [However, f_2≫
f_1], the oscillation frequency (f_0) [however, f_2>f_0≫f_1]
a first counter that counts the number of output pulses of the pulse generator circuit and uses an input pulse of the frequency (f_1) as a reset pulse;
a shift register that inputs the counter output signal of the frequency (f_1) and uses the input pulse of the frequency (f_1) as a shift pulse; and a second counter that counts the number of pulses of the input pulse signal of the frequency (f_2) and outputs the counted value. and inputting the second counter output signal and the shift register output signal,
a coincidence detection circuit that outputs a signal when the two match, the output signal of the coincidence detection circuit is taken out as a multiplication value of the two input pulse signals, and the output signal of the coincidence detection circuit is used to reset the second counter. A pulse multiplier characterized in that it is configured as a pulse.