SU849151A1 - Device for measuring amplitude phase frequency characteristics - Google Patents

Description

The invention relates to automatic control and regulation and is intended for the experimental study of the dynamic characteristics of linear automatic control systems (ACS). A spectrum analyzer based on the calculation of the Fourier series is known, which contains a generator of harmonic oscillations of orthogonal functions (sine and cosine oscillations), multiplication units, integrators, and recorders. When determining the amplitude-phase characteristics with this analyzer, the system is output to the forced oscillation mode, the output signal of the system is multiplied by the sine and cosine oscillations, and then the resulting product is integrated over the period. At the outputs of the integrators, the values of the real and imaginary components of the amplitude-phase characteristic tlj are obtained. The disadvantages of such a device are the duration of the determination of the amplitude-phase characteristics, since the points of the amplitude-phase characteristics are determined by sequential input to the system of a number of frequencies, as well as the difficulty in the implementation of multipliers. The closest to the proposed technical entity is a device for determining amplitude-phase characteristics, which contains a frequency generator, a driver, often, a Rodemacher function generator, a block of discrete-analog generators, an adder, a voltage-to-frequency converter, an integral interval setting unit, a key, a block character extraction, two blocks of logic elements, two blocks of frequency dividers and two blocks of correlators, the outputs of which are connected to the corresponding inputs of blocks of recording devices, in stroke sign extracting unit is connected to first inputs of AND gates G2 blocks}. A disadvantage of the known device is the duration of determining the amplitude-phase characteristics with a large number of points. The purpose of the invention is to improve the accuracy and speed of the device. This goal is achieved by the fact that in a device for measuring c 1-phase-phase frequency characteristics containing series-connected

master oscillator, decade frequency divider, octave frequency divider, polyharmonic signal generation unit, serially connected shift register, first AND element, first orthogonal signal generation unit, first multiplication unit, first digital integrator, second orthogonal signal generation unit sequentially connected, second multiplication unit , the second digital integrator, with the inputs of the orthogonal signal generation units connected, the output of the shift register is connected to the first input of the second And, the second input of the first element And is connected to the first input of the third element And and to the corresponding output of the octave Frequency Divider, the second input of the second element And is connected to the corresponding output of the program block, to the other output of which the second input of the ten-day frequency divider is connected, the second input of the first the multiplication unit is connected to the second input of the second multiplication unit and to the input of the device, the output of which is connected to the output of the polyharmonic signal shaping unit, the input of the pulse distributor, Yuchen to the corresponding output of the software block, the first output of the comparison block is connected to the corresponding input of the registration block, the first input of the decoder is connected to the corresponding output of the program block, as well as the registration control unit, the zero-body, quadrant calculator, the fourth element, AND, element OR, driver pulses, the output of the first digital integrator is connected to the input of the code comparison unit and the first input of the quadrant calculator, the second input of which is connected to the output of the second digital integrator Pa and the input of the null-organ, whose output and the second output of the comparison code block are connected to the inputs of the fourth element I, the output of which is connected to the corresponding input of the program block, the output of the quadrant calculator connected to the phase counter inputs, the output of the first orthogonal signal shaping unit through the driver impulses are connected to the second input of the impulse distributor, the first output of which is connected to the first input of the OR element, the second output is connected to the second input of the OR element and The input of the shift register, the third output through the third element AND is connected to the second input of the shift register, the output of the OR input is connected to the corresponding input of the program block and the second inputs of digital integrators, the output of the second element AND is connected to the corresponding input of the registration unit one of the inputs which, through the registration control unit, is connected to the output of the program unit.

The drawing shows a block diagram of the proposed device.

The device contains a master oscillator 1, decade 2 and octave 3 frequency dividers, a polyharmonic signal generation unit 4, an object 5, an octave channel processing channel, a discrete phase shifter 7, a control unit 8, a phase meter 9, a formation unit 10 and 11 of real and imaginary components, driver 12, shift register 13, first element AND 14, second element AND 15, third element AND 16, distributor 17, element OR 18, subtractive phase counter 19, decoder 20, first 21 and second 24 blocks forming orthogonal signals, first 22 and Torah multiplying blocks 25, 23, first and second digital integrators 26, a block 27 calculating the quadrant nulorgan 28, the fourth AND gate 29, the comparison block 30 code registration unit 31, the control unit 32 recording, the program block 33.

The device works as follows.

In the initial state, all the integrators and counters are in the zero state, and the distributor 17 is in position 111.

The processes occurring in each of the processing channels of the octave frequencies are identical.

In one of the channels on the Start signal, program block 33 turns on decade divider 2 for issuing the first decade of frequencies. The signal from the divider 2 is fed to the input of the octthonal divider 3, from the output of which signals are fed to the inputs of the polyharmonic signal-shaping unit and to the inputs of the octave frequency processing channels. In block 4, a polyharmonic signal is formed and fed to the input of control object 5. Volume 5 is output to the mode of forced oscillations, from its output we get the signal f (t).

On the Start signal, the software block 33 switches the distributor 17 to position 1. The signal from the output of the distributor 17 goes to the first input of the OR circuit 18 and from its output goes to the inputs of the digital integrators 23 and 26 and gives permission to turn them on. At the same time, the excitation pulses of the octave frequency through the open circuit 14 of the Inhibit enter the formation blocks 21 and 24 of orthogonal functions. Scheme 14 The ban works according to the C-ALV algorithm, where A is the octave frequency signal,

B - shift register signal In block 21, the signal cos w i t is generated, and in block 24 -sin wi the process is multiplied1; and integrating the signals in the formation blocks of a real component of 10 and imaginary component 11. At a significant moment — the end of the first half period of the cos wit function — distributor 17 by driver 12 switches to position 11, the integration process continues, and in register

13, the number corresponding to a single phase shift of the reference is recorded on the dF signal during the adjustment process. After the end of the second half period, the distributor 17 switches to position III, the integrators are disconnected from the multipliers through the circuit OR 18.

The number recorded in the integrator 23 is transferred to the code comparison block 30, and by the signs of the integrator signals 23 and 26, the quadrant block 27 through the decoder 20 of the quadrant records the initial angle value in the counter 21. During the half-period formation, the AND 16 element of the shift register 13 is supplied with clock pulses that prohibit the transmission of signals through the circuit 14 to the blocks 21 and 24 of the formation of orthogonal functions. After the release of register 13 scheme Prohibition

14, and the formation of the 3rd half period of the function continues.

Due to the described process, the 3rd half-cycle is shifted by the value of D f which corresponds to the phase shift of the reference signal and the component of this frequency contained in the signal f (t). In the 4th and 5th half periods, the effect of the scheme does not differ from that described for the 1st and 2nd half periods. When the distributor switches back to position 111, then from the output of the integrator 23 to block 30 the current value of the real component is received, which is compared with the previous value.

Such a comparison of equality of codes is necessary in order to record the arrival of a steady state. In the steady state, the codes are equal, and from block 30 the signal arrives at the first input of the AND 29 logic circuit. In the steady state, the phase control process lasts until the null organ 28 determines that the imaginary component is equal to zero, then the signals of the steady state and A zero imaginary component at the inputs of the AND circuit 29 causes an output signal of the AND circuit 29, which is fed to the program block 33 to allow single-time amplitude and phase registration through the block 32 of the registration operation control block. ke 31 registration and display of results, and the subsequent disconnection of this octave channel before moving to the next decade of frequencies. After the termination of the control and registration processes for all octave channels, the program device 33 switches the divider 2 to the next decade of frequencies, etc. until completion of the analysis in the entire study area,

The proposed device automatically adjusts the phase of the reference Orthogonal signals with the aim of obtaining a zero value, the imaginary component of the amplitude-phase frequency characteristic of the system at a given frequency in the steady state of the object 5, gives a signal at the output of block 30 of the code comparison, a signal corresponding to the amplitude of the amplitude L, a the total value of the phase shift in the process of such adjustment from the initial value gives the output of the subtracting counter 19 the value of the phase shift H,

0

The proposed device allows to increase the accuracy and shorten the measurement time of the amplitude-phase frequency response of the system on a given frequency range.

Claims (2)

Invention Formula A device for measuring the amplitudes of D-phase frequency characteristics, comprising a series-connected master oscillator, a decadal frequency divider, an octave frequency divider, a polyharmonic signal generating unit, a series-connected shift register, the first And element, the first multiplication unit, the first multiplication unit. first digital integrator 0 are connected in series to a second orthogonal signal generation unit, a second multiplication unit, a second digital integrator, and the inputs to the orthogonal sig- forming units. The signal is connected to the first input of the second element I, the second input of the first element I is connected to the first input of the third element Nick corresponding to the output of the octave frequency divider, the second input of the second element I is connected to the corresponding output of the program block, to another the output of which is connected to the second input of the ten-day frequency divider, the second input 5 of the first multiplication unit is connected to the second input of the second multiplication unit and to the input of the device to the output of which the output of the polyharmonic signal generation unit is connected, the input of the pulse distributor is connected to the corresponding output of the program block, the first output of the code comparison unit is connected to the corresponding input of the registration unit, the first input 5 of the decoder is connected to the corresponding output of the program block, as well as the registration control block, null organ, quadrant evaluator, fourth AND element, OR element, pulse maker, characterized in that, in order to improve the accuracy and speed of the device, the output of the first the digital integrator is connected to the input of the code comparison block and the first input in, the numerator of the quadrant, the second input of which is connected to the output of the second digital integrator and the input of the null organ, the output of which and the second output of the comparison block One is connected to the inputs of the fourth element, And the output of which is connected to the corresponding input of the program block, the output of the quadrant calculator is connected via the decoder to the inputs of the phase counter, the output of the first orthogonal signal generation unit is connected to the second pulse distributor, the first output of which is connected to the first input of the OR element, the second output is connected to the second input of the OR element and the first input of the shift register, the third output through the third element AND the connection on the second input of the shift register, the output of the OR element is connected to the corresponding input of the program block and the second inputs of the digital integrators, the output of the second element AND is connected via a subtracting phase counter to the corresponding input of the registration unit, one of the inputs of which is connected to the output of the program block . Sources of information taken into account in the examination 1. N. Ordintsev Automation of the mathematical description of control objects. M., Mechanical Engineering, 1969, p. 141-143. 2. USSR author's certificate number 2454270, cl. G 05 23/02, 1977 (prototype).