SU773917A1 - Staircase signal generator - Google Patents

Description

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The invention relates to a pulse technique and can be used in measuring devices.

Known generator step signal. containing linearly varying voltage drivers 5, trigger, two keys l.

The drawbacks of the device are its complexity, low (operation. About

The closest technical solution to the present invention is a step signal generator containing a series-connected amplifier with a smoothing filter; a reference frequency counter, the input of which is connected to the reference signal bus, a clock counter, a clock signal bus l2j.

The disadvantage of the device is 20 low reliability.

The purpose of the invention is to increase the reliability of work.

The goal is achieved by the fact that in the generator of a stepped signal 25, containing a series-connected pulse amplifier with a smoothing filter included at the output, is a reference counter, the input of which is connected to the reference bus 30

signal, clock counter, bus-clock signal, an odd-ness element introduced, the first input of which is connected to the output of the reference frequency counter, a second input with the output of the clock frequency counter, and the output is connected to the input of a pulse amplifier, and the frequency addition element connected to the reference signal bus, the second input of the clock signal bus, and the output to the input of the clock frequency counter.

The drawing shows a structural electrical circuit of the device.

The device contains a counter 1 of the reference frequency, a counter 2 of the clock frequency, an amplifier 3, a smoothing filter 4, an element 5 of the frequency addition, an element 6 of the control of oddness, a bus 7 of the reference signal, a bus 8 of the clock frequency.

The device works as follows.

The pulses of the reference frequency on the bus 7 are fed to the input of the counter 1 reference. frequencies, and shults at the clock input of the counter 2 arrive at a frequency equal to the difference (in this example) of the reference and clock frequencies, which are formed by frequency subtraction element 5. At the outputs of counters 1 and

2, square signals are generated with a duty cycle equal to two, which are fed to the inputs of the odd-ness element 6, and the frequency of the signal fed to the counter 2 of the clock frequency is lower than the frequency of the signal fed to the counter 1 of the reference frequency.

The output of the element b is oddness control, which implements a logical function. Exclusive OR, there is a low logic level, if its inputs have the same logic signals, and a high logic level, if they are different. In line with this, a square signal will be generated at the output of the accuracy element 6, the duty cycle of which will depend on the phase shift of the rectangular signals of the reference and clock counters.

After amplification of the received signal by amplifier 3 and extraction of the constant component from it by means of a smoothing filter 4, the signal will take the desired form.

Claims (2)

1. USSR author's certificate No. 499655, cl., H 03 K 4 / 06,15.01.76. 2. USSR author's certificate No. 451177, cl. N 03 K 4 / 02.06.04.73 (prototype).