JPS593787A - Complementary mis memory - Google Patents

Abstract

PURPOSE:To reduce power consumption, by connecting a level shifting element between a power source and the source of the P channel MIS transistor (TR) of an input inverter formed by connecting the P channel MIS-TR and an N channel MIS-TR in series. CONSTITUTION:A chip selection signal input part consists of the 1st stage inverter INV1 to which an external control signal -CS is inputted a P channel MISQ7 between it and the power source, the 2nd stage inverter INV2, and a P channel MISQ10 between it and the power source. The 1st stage inverter is constituted by connecting the P channel MISQ5 and N channel MISQ6 in series. The drain voltage of the Q5 drops below Vcc by the threshold voltage of the MISQ7 through the operation of the MISQ7, so the voltage range of the signal -CS is narrowed down. Consequently, the power consumption of the chip signal input part in still operation is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a complementary MIS memory, and particularly to a complementary MIS memory that reduces power consumption in a chip select signal input section when stationary. .

(2) Prior Art and Problems Generally, in complementary MIS memories, it is desired to further reduce power consumption even when the memory is at rest. In a conventional complementary MIS memory, the internal control signal CAB obtained by inputting an external signal plane (chip select signal) to control the entire memory to a static state into a dart circuit as shown in Figure 1 is used to control the memory. As shown in FIG. 2, a method is used to eliminate the DC-like current path by controlling the first-stage inverter dart of another input signal X1.

The dart circuit shown in FIG. 1 is composed of two stages of complementary MIS inverters INV, +INv2. The inverter dart in FIG. 2 consists of a complementary MIS inverter INV3 to which an input signal
In the complementary MIS memory described above, the memory operation is as follows: Sometimes, an L level signal is input as external signal 0. In this case, the signal Ov is outputted as the internal control signal CBS and inputted to the gates of the MIS transistors Q3 and Q4 of the input input part R in FIG. Therefore, M.I.
Since the S transistor Ql is on and Q2 is off, the second
The inverter dart shown in the figure operates as a normal inverter with respect to the input signal Xi. When the memory is at rest, an H level signal is input as the external signal CS, and the internal control signal C8B becomes Vco. Therefore, in the inverter gate of FIG. 2, when MIS transistor Q3 is turned off and Q4 is turned on, the current path is cut off and the output is fixed at QV, regardless of the level of input signal X1. In this way, in the complementary MIS memory described above, the power consumption of the inverter ff-) at the input terminal when the memory is at rest can be reduced.

By the way, the conventional complementary MI shown in FIGS. 1 and 2
In the S memory, an external signal CS is used to control the static state.
No reduction in power consumption has been made for the first-stage inverter itself, which inputs .

Therefore, the relationship between the input voltage at the first stage inverter INVl in FIG. 1 and the current flowing through the MIS (MIS) Lannostar Q1+Q2 is as shown in FIG.
A relatively large current flows with respect to rVHL=0.8 V max).

(3) Purpose of the Invention An object of the present invention is to provide a complementary MIS memory that reduces power consumption at the input section of the signal that controls the static state, in view of the problems of the conventional type described above. .

(4) Structure of the invention In the present invention, a P-channel MIS) transistor and an N
A complementary MIS memory that has an input input consisting of series-connected channel MIS transistors, and has a function to put the entire memory in a static state by a control signal input through the input inverter. Therefore, the P channel M
IS) A complementary MIS memory is provided which is characterized in that a level shift element is connected between the source of a transistor and a power supply.

(5) Embodiment of the Invention A complementary MIS memory as an embodiment of the invention will be described below with reference to FIGS. 4 and 5.

FIG. 4 shows a chip select signal input section in a complementary MIS memory according to the present invention. FIG. 5 shows the relationship between the input voltage and the current flowing through Qs and Q6-Qy in the circuit of FIG.

The chip select signal input section in FIG. 4 includes a first stage inverter Nv1 and a power source V to which a control signal (chip select signal) from the input section is input. A P-channel MIS transistor Q7 connected between C and the first-stage inverter INV1, a second-stage inverter INv2 to which the output of the first-stage inverter INV is input, and a power supply V. C
and a second inverter INV, and the dart is connected to the output of the second inverter INV.

In the chip select signal input section in Fig. 4, MIS
) Due to the action of transistor Q7, M-S transistor Q
Since the drain voltage of transistor Q5 is lowered by the threshold voltage of transistor Q7 (vCC), MIS transistor Q11 is turned off and the voltage at which transistor Q7 starts is apparently lower.
Since the voltage range of the cl signal through which current flows through MIS transistors Q5 and Qs is narrow, power consumption is reduced compared to the conventional circuit shown in FIG. That is, as shown in FIG. 5, the current for the same H level input is reduced, and the level v2 at which current consumption becomes zero is lower than vl in FIG. 3. In addition, the P-channel MIS) transistor QIO compensates for the drop in the high rail of the inverter INV1 due to the connection of the MIS transistor Q7, and becomes conductive when the output of the inverter INV2 becomes low level, and connects the input terminal of the inverter INV. pull up. In addition, in the above example, MIS) Lanzosta Q7
Although a P-channel MIS) lannoster is used as the P-channel MIS), a N-channel MIS) transistor or diode with dart connected to VCO may also be used.

(6) Effects of the Invention According to the present invention, it is possible to provide a complementary MIS memory that can reduce the power consumption when the memory is at rest in the chip select signal input section that controls the memory to be at rest.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the chip select signal input section in a conventional complementary FIMIs memory, FIG. 2 is a circuit diagram showing the first stage inverter of the input section in the complementary MIS memory, and FIG. 3 is the circuit diagram shown in FIG. 4 is a circuit diagram showing a chip select signal input section in a complementary MIS memory as an embodiment of the present invention; FIG. 5 is a diagram showing the relationship between input signal voltage and current in the circuit; FIG. 3 is a diagram showing the relationship between input signal voltage and current in the circuit of FIG. (Explanation of symbols) INVl, INVl t INVg --- Complementary MIS ear/guita, Q□ ~QIO... MIS transistor. -Figure 5

Claims (1)

[Claims] IP channel MIS) transistor and N channel MIS
) Complementary type M having an input inverter formed by connecting transistors in series, and having a function of bringing the entire memory into a static state by a control signal inputted through the input inverter.
1. A complementary MIS memory characterized in that a level shift element is connected between the source of the P-channel MIS transistor and a power supply. 2. The complementary MIS memory according to claim 1, wherein the level shift element is a P-channel or N-channel MIS transistor whose dart and drain are commonly connected.